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Code Issues Releases Activity

Fix instances of macros with improperly parenthasized arguments.

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Verified by: md5
This commit is contained in:
Alfred Perlstein 2002-11-09 12:55:07 +00:00
parent e07c0ca6c8
commit 29f194457c
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=106696
18 changed files with 95 additions and 93 deletions
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4
sys/cam/scsi/scsi_ses.c
View File

@ -1635,9 +1635,9 @@ struct scfg {
static char *safte_2little = "Too Little Data Returned (%d) at line %d\n";
#define SAFT_BAIL(r, x, k, l) \
if (r >= x) { \
if ((r) >= (x)) { \
SES_LOG(ssc, safte_2little, x, __LINE__);\
SES_FREE(k, l); \
SES_FREE((k), (l)); \
return (EIO); \
}

8
sys/dev/bge/if_bgereg.h
View File

@ -2044,14 +2044,14 @@ struct vpd_key {
bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg)
#define BGE_SETBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | x))
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
#define BGE_CLRBIT(sc, reg, x) \
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~x))
CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
#define PCI_SETBIT(dev, reg, x, s) \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | x), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
#define PCI_CLRBIT(dev, reg, x, s) \
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~x), s)
pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
/*
* Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS

18
sys/dev/gx/if_gxvar.h
View File

@ -53,22 +53,24 @@ struct mtx { int filler; };
/* CSR_WRITE_8 assumes the register is in low/high order */
#define CSR_WRITE_8(gx, reg, val) do { \
bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val & 0xffffffff); \
bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg + 4, val >> 32); \
bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \
reg, (val) & 0xffffffff); \
bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, \
(reg) + 4, (val) >> 32); \
} while (0)
#define CSR_WRITE_4(gx, reg, val) \
bus_space_write_4(gx->gx_btag, gx->gx_bhandle, reg, val)
bus_space_write_4((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
#define CSR_WRITE_2(gx, reg, val) \
bus_space_write_2(gx->gx_btag, gx->gx_bhandle, reg, val)
bus_space_write_2((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
#define CSR_WRITE_1(gx, reg, val) \
bus_space_write_1(gx->gx_btag, gx->gx_bhandle, reg, val)
bus_space_write_1((gx)->gx_btag, (gx)->gx_bhandle, reg, val)
#define CSR_READ_4(gx, reg) \
bus_space_read_4(gx->gx_btag, gx->gx_bhandle, reg)
bus_space_read_4((gx)->gx_btag, (gx)->gx_bhandle, reg)
#define CSR_READ_2(gx, reg) \
bus_space_read_2(gx->gx_btag, gx->gx_bhandle, reg)
bus_space_read_2((gx)->gx_btag, (gx)->gx_bhandle, reg)
#define CSR_READ_1(gx, reg) \
bus_space_read_1(gx->gx_btag, gx->gx_bhandle, reg)
bus_space_read_1((gx)->gx_btag, (gx)->gx_bhandle, reg)
#define GX_SETBIT(gx, reg, x) \
CSR_WRITE_4(gx, reg, (CSR_READ_4(gx, reg) | (x)))

4
sys/dev/my/if_my.c
View File

@ -148,8 +148,8 @@ static int my_list_rx_init(struct my_softc *);
static int my_list_tx_init(struct my_softc *);
static long my_send_cmd_to_phy(struct my_softc *, int, int);
#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
#define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
#define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
static device_method_t my_methods[] = {
/* Device interface */

4
sys/dev/nge/if_nge.c
View File

@ -238,10 +238,10 @@ DRIVER_MODULE(miibus, nge, miibus_driver, miibus_devclass, 0, 0);
CSR_READ_4(sc, reg) & ~(x))
#define SIO_SET(x) \
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | x)
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) | (x))
#define SIO_CLR(x) \
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~x)
CSR_WRITE_4(sc, NGE_MEAR, CSR_READ_4(sc, NGE_MEAR) & ~(x))
static void
nge_delay(sc)

42
sys/dev/ppbus/ppb_msq.h
View File

@ -106,53 +106,53 @@
*/
/* register operations */
#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ reg }, { assert }, { clear }}}
#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { reg }, { byte }}}
#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ reg }, { MS_ASSERT_NONE }, { clear }}}
#define MS_RSET(reg,assert,clear) { MS_OP_RSET, {{ (reg) }, { (assert) }, { (clear) }}}
#define MS_RASSERT(reg,byte) { MS_OP_RASSERT, { { (reg) }, { (byte) }}}
#define MS_RCLR(reg,clear) { MS_OP_RSET, {{ (reg) }, { MS_ASSERT_NONE }, { (clear) }}}
#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ reg }, { mask }, { ptr }}}
#define MS_RFETCH(reg,mask,ptr) { MS_OP_RFETCH, {{ (reg) }, { (mask) }, { (ptr) }}}
/* trigger the port with array[char, delay,...] */
#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ reg }, { len }, { array }}}
#define MS_TRIG(reg,len,array) { MS_OP_TRIG, {{ (reg) }, { (len) }, { (array) }}}
/* assert/fetch from/to ptr */
#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ n }, { reg }}}
#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ n }, { reg }, { mask }}}
#define MS_RASSERT_P(n,reg) { MS_OP_RASSERT_P, {{ (n) }, { (reg) }}}
#define MS_RFETCH_P(n,reg,mask) { MS_OP_RFETCH_P, {{ (n) }, { (reg) }, { (mask) }}}
/* ptr manipulation */
#define MS_PTR(ptr) { MS_OP_PTR, {{ ptr }}}
#define MS_PTR(ptr) { MS_OP_PTR, {{ (ptr) }}}
#define MS_DASS(byte) MS_RASSERT(MS_REG_DTR,byte)
#define MS_SASS(byte) MS_RASSERT(MS_REG_STR,byte)
#define MS_CASS(byte) MS_RASSERT(MS_REG_CTR,byte)
#define MS_SET(accum) { MS_OP_SET, {{ accum }}}
#define MS_BRSET(mask,offset) { MS_OP_BRSET, {{ mask }, { offset }}}
#define MS_DBRA(offset) { MS_OP_DBRA, {{ offset }}}
#define MS_BRCLEAR(mask,offset) { MS_OP_BRCLEAR, {{ mask }, { offset }}}
#define MS_SET(accum) { MS_OP_SET, {{ (accum) }}}
#define MS_BRSET(mask,offset) { MS_OP_BRSET, {{ (mask) }, { (offset) }}}
#define MS_DBRA(offset) { MS_OP_DBRA, {{ (offset) }}}
#define MS_BRCLEAR(mask,offset) { MS_OP_BRCLEAR, {{ (mask) }, { (offset) }}}
#define MS_BRSTAT(mask_set,mask_clr,offset) \
{ MS_OP_BRSTAT, {{ mask_set }, { mask_clr }, { offset }}}
{ MS_OP_BRSTAT, {{ mask_set }, { mask_clr }, { (offset) }}}
/* C function or submicrosequence call */
#define MS_C_CALL(function,parameter) \
{ MS_OP_C_CALL, {{ function }, { parameter }}}
#define MS_CALL(microseq) { MS_OP_CALL, {{ microseq }}}
{ MS_OP_C_CALL, {{ (function) }, { (parameter) }}}
#define MS_CALL(microseq) { MS_OP_CALL, {{ (microseq) }}}
/* mode dependent read/write operations
* ppb_MS_xxx_init() call required otherwise default is
* IEEE1284 operating mode */
#define MS_PUT(ptr,len) { MS_OP_PUT, {{ ptr }, { len }}}
#define MS_GET(ptr,len) { MS_OP_GET, {{ ptr }, { len }}}
#define MS_PUT(ptr,len) { MS_OP_PUT, {{ (ptr) }, { (len) }}}
#define MS_GET(ptr,len) { MS_OP_GET, {{ (ptr) }, { (len) }}}
/* delay in microseconds */
#define MS_DELAY(udelay) { MS_OP_DELAY, {{ udelay }}}
#define MS_DELAY(udelay) { MS_OP_DELAY, {{ (udelay) }}}
/* asynchroneous delay in ms */
#define MS_ADELAY(mdelay) { MS_OP_ADELAY, {{ mdelay }}}
#define MS_ADELAY(mdelay) { MS_OP_ADELAY, {{ (mdelay) }}}
/* return from submicrosequence execution or microseqence execution */
#define MS_SUBRET(code) { MS_OP_SUBRET, {{ code }}}
#define MS_RET(code) { MS_OP_RET, {{ code }}}
#define MS_SUBRET(code) { MS_OP_SUBRET, {{ (code) }}}
#define MS_RET(code) { MS_OP_RET, {{ (code) }}}
/*
* Function abstraction level

4
sys/dev/sym/sym_defs.h
View File

@ -798,10 +798,10 @@ struct sym_tblsel {
#define SCR_DSA_REL2 0x10000000
#define SCR_LOAD_R(reg, how, n) \
(0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
(0xe1000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_STORE_R(reg, how, n) \
(0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
(0xe0000000 | (how) | (SCR_REG_OFS2(REG(reg))) | (n))
#define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
#define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)

14
sys/dev/ti/if_tireg.h
View File

@ -807,16 +807,16 @@ struct ti_cmd_desc {
* that 'sc' and 'cmd' are in local scope.
*/
#define TI_DO_CMD(x, y, z) \
cmd.ti_cmd = x; \
cmd.ti_code = y; \
cmd.ti_idx = z; \
cmd.ti_cmd = (x); \
cmd.ti_code = (y); \
cmd.ti_idx = (z); \
ti_cmd(sc, &cmd);
#define TI_DO_CMD_EXT(x, y, z, v, w) \
cmd.ti_cmd = x; \
cmd.ti_code = y; \
cmd.ti_idx = z; \
ti_cmd_ext(sc, &cmd, v, w);
cmd.ti_cmd = (x); \
cmd.ti_code = (y); \
cmd.ti_idx = (z); \
ti_cmd_ext(sc, &cmd, (v), (w));
/*
* Other utility macros.

8
sys/dev/twe/twe_compat.h
View File

@ -95,10 +95,10 @@
/*
* Wrappers for bus-space actions
*/
#define TWE_CONTROL(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x0, (u_int32_t)val)
#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0x4)
#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4(sc->twe_btag, sc->twe_bhandle, 0x8, (u_int32_t)val)
#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4(sc->twe_btag, sc->twe_bhandle, 0xc)
#define TWE_CONTROL(sc, val) bus_space_write_4((sc)->twe_btag, (sc)->twe_bhandle, 0x0, (u_int32_t)val)
#define TWE_STATUS(sc) (u_int32_t)bus_space_read_4((sc)->twe_btag, (sc)->twe_bhandle, 0x4)
#define TWE_COMMAND_QUEUE(sc, val) bus_space_write_4((sc)->twe_btag, (sc)->twe_bhandle, 0x8, (u_int32_t)val)
#define TWE_RESPONSE_QUEUE(sc) (TWE_Response_Queue)bus_space_read_4((sc)->twe_btag, (sc)->twe_bhandle, 0xc)
/*
* FreeBSD-specific softc elements

4
sys/fs/msdosfs/denode.h
View File

@ -127,8 +127,8 @@ struct fatcache {
* Set a slot in the fat cache.
*/
#define fc_setcache(dep, slot, frcn, fsrcn) \
(dep)->de_fc[slot].fc_frcn = frcn; \
(dep)->de_fc[slot].fc_fsrcn = fsrcn;
(dep)->de_fc[(slot)].fc_frcn = (frcn); \
(dep)->de_fc[(slot)].fc_fsrcn = (fsrcn);
/*
* This is the in memory variant of a dos directory entry. It is usually

2
sys/i386/isa/gpib.c
View File

@ -35,7 +35,7 @@
#error "The gpib device requires the old isa compatibility shims"
#endif
#define MIN(a, b) ((a < b) ? a : b)
#define MIN(a, b) (((a) < (b)) ? (a) : (b))
#define GPIBPRI (PZERO + 8) | PCATCH
#define SLEEP_MAX 1000

2
sys/kern/uipc_socket.c
View File

@ -563,7 +563,7 @@ sosend(so, addr, uio, top, control, flags, td)
td->td_proc->p_stats->p_ru.ru_msgsnd++;
if (control)
clen = control->m_len;
#define snderr(errno) { error = errno; splx(s); goto release; }
#define snderr(errno) { error = (errno); splx(s); goto release; }
restart:
error = sblock(&so->so_snd, SBLOCKWAIT(flags));

2
sys/libkern/qsort.c
View File

@ -39,7 +39,7 @@ typedef int cmp_t(const void *, const void *);
static __inline char *med3(char *, char *, char *, cmp_t *);
static __inline void swapfunc(char *, char *, int, int);
#define min(a, b) (a) < (b) ? a : b
#define min(a, b) (a) < (b) ? (a) : (b)
/*
* Qsort routine from Bentley & McIlroy's "Engineering a Sort Function".

2
sys/net/radix.c
View File

@ -71,7 +71,7 @@ static char *rn_zeros, *rn_ones;
#define rn_masktop (mask_rnhead->rnh_treetop)
#undef Bcmp
#define Bcmp(a, b, l) \
(l == 0 ? 0 : bcmp((caddr_t)(a), (caddr_t)(b), (u_long)l))
((l) == 0 ? 0 : bcmp((caddr_t)(a), (caddr_t)(b), (u_long)(l)))
static int rn_lexobetter(void *m_arg, void *n_arg);
static struct radix_mask *

28
sys/net/zlib.c
View File

@ -1983,7 +1983,7 @@ local void copy_block OF((deflate_state *s, charf *buf, unsigned len,
int header));
#ifndef DEBUG_ZLIB
# define send_code(s, c, tree) send_bits(s, tree[c].Code, tree[c].Len)
# define send_code(s, c, tree) send_bits(s, tree[(c)].Code, tree[(c)].Len)
/* Send a code of the given tree. c and tree must not have side effects */
#else /* DEBUG_ZLIB */
@ -2041,16 +2041,16 @@ local void send_bits(s, value, length)
#else /* !DEBUG_ZLIB */
#define send_bits(s, value, length) \
{ int len = length;\
if (s->bi_valid > (int)Buf_size - len) {\
int val = value;\
s->bi_buf |= (val << s->bi_valid);\
put_short(s, s->bi_buf);\
s->bi_buf = (ush)val >> (Buf_size - s->bi_valid);\
s->bi_valid += len - Buf_size;\
{ int len = (length);\
if ((s)->bi_valid > (int)Buf_size - len) {\
int val = (value);\
(s)->bi_buf |= (val << (s)->bi_valid);\
put_short((s), (s)->bi_buf);\
(s)->bi_buf = (ush)val >> (Buf_size - (s)->bi_valid);\
(s)->bi_valid += len - Buf_size;\
} else {\
s->bi_buf |= (value) << s->bi_valid;\
s->bi_valid += len;\
(s)->bi_buf |= (value) << (s)->bi_valid;\
(s)->bi_valid += len;\
}\
}
#endif /* DEBUG_ZLIB */
@ -5345,10 +5345,10 @@ void zcfree (opaque, ptr)
#define NMAX 5552
/* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
#define DO1(buf,i) {s1 += buf[i]; s2 += s1;}
#define DO2(buf,i) DO1(buf,i); DO1(buf,i+1);
#define DO4(buf,i) DO2(buf,i); DO2(buf,i+2);
#define DO8(buf,i) DO4(buf,i); DO4(buf,i+4);
#define DO1(buf,i) {s1 += buf[(i)]; s2 += s1;}
#define DO2(buf,i) DO1(buf,i); DO1(buf,(i)+1);
#define DO4(buf,i) DO2(buf,i); DO2(buf,(i)+2);
#define DO8(buf,i) DO4(buf,i); DO4(buf,(i)+4);
#define DO16(buf) DO8(buf,0); DO8(buf,8);
/* ========================================================================= */

16
sys/netinet/tcp_syncache.c
View File

@ -179,14 +179,14 @@ static MALLOC_DEFINE(M_SYNCACHE, "syncache", "TCP syncache");
#define ENDPTS6_EQ(a, b) (memcmp(a, b, sizeof(*a)) == 0)
#define SYNCACHE_TIMEOUT(sc, slot) do { \
sc->sc_rxtslot = slot; \
sc->sc_rxttime = ticks + TCPTV_RTOBASE * tcp_backoff[slot]; \
TAILQ_INSERT_TAIL(&tcp_syncache.timerq[slot], sc, sc_timerq); \
if (!callout_active(&tcp_syncache.tt_timerq[slot])) \
callout_reset(&tcp_syncache.tt_timerq[slot], \
TCPTV_RTOBASE * tcp_backoff[slot], \
syncache_timer, (void *)((intptr_t)slot)); \
#define SYNCACHE_TIMEOUT(sc, slot) do { \
sc->sc_rxtslot = (slot); \
sc->sc_rxttime = ticks + TCPTV_RTOBASE * tcp_backoff[(slot)]; \
TAILQ_INSERT_TAIL(&tcp_syncache.timerq[(slot)], sc, sc_timerq); \
if (!callout_active(&tcp_syncache.tt_timerq[(slot)])) \
callout_reset(&tcp_syncache.tt_timerq[(slot)], \
TCPTV_RTOBASE * tcp_backoff[(slot)], \
syncache_timer, (void *)((intptr_t)(slot))); \
} while (0)
static void

12
sys/pci/if_ste.c
View File

@ -165,22 +165,22 @@ DRIVER_MODULE(if_ste, pci, ste_driver, ste_devclass, 0, 0);
DRIVER_MODULE(miibus, ste, miibus_driver, miibus_devclass, 0, 0);
#define STE_SETBIT4(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | (x))
#define STE_CLRBIT4(sc, reg, x) \
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~(x))
#define STE_SETBIT2(sc, reg, x) \
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | x)
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) | (x))
#define STE_CLRBIT2(sc, reg, x) \
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~x)
CSR_WRITE_2(sc, reg, CSR_READ_2(sc, reg) & ~(x))
#define STE_SETBIT1(sc, reg, x) \
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | x)
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) | (x))
#define STE_CLRBIT1(sc, reg, x) \
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~x)
CSR_WRITE_1(sc, reg, CSR_READ_1(sc, reg) & ~(x))
#define MII_SET(x) STE_SETBIT1(sc, STE_PHYCTL, x)

14
sys/pci/if_tireg.h
View File

@ -807,16 +807,16 @@ struct ti_cmd_desc {
* that 'sc' and 'cmd' are in local scope.
*/
#define TI_DO_CMD(x, y, z) \
cmd.ti_cmd = x; \
cmd.ti_code = y; \
cmd.ti_idx = z; \
cmd.ti_cmd = (x); \
cmd.ti_code = (y); \
cmd.ti_idx = (z); \
ti_cmd(sc, &cmd);
#define TI_DO_CMD_EXT(x, y, z, v, w) \
cmd.ti_cmd = x; \
cmd.ti_code = y; \
cmd.ti_idx = z; \
ti_cmd_ext(sc, &cmd, v, w);
cmd.ti_cmd = (x); \
cmd.ti_code = (y); \
cmd.ti_idx = (z); \
ti_cmd_ext(sc, &cmd, (v), (w));
/*
* Other utility macros.