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Code Issues Releases Activity

Fix pmap_dcache_wb_pou in the new armv6 pmap to correctly achieve icache

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consistency from ptrace.

PR:		199739
Submitted by:	Jurgen Weiss <weiss at uni-mainz.de> (original version)
Submitted by:	Svatopluk Kraus <onwahe at gmail.com>
This commit is contained in:
Andrew Turner 2015-04-28 16:47:34 +00:00
parent d8c37c3a16
commit 2a1803d048
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=282151
1 changed files with 4 additions and 5 deletions
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9
sys/arm/arm/pmap-v6-new.c
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@ -6094,13 +6094,13 @@ pmap_set_pcb_pagedir(pmap_t pmap, struct pcb *pcb)
/*
* Clean L1 data cache range on a single page, which is not mapped yet.
* Clean L1 data cache range by physical address.
* The range must be within a single page.
*/
static void
pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
{
struct sysmaps *sysmaps;
vm_offset_t va;
KASSERT(((pa & PAGE_MASK) + size) <= PAGE_SIZE,
("%s: not on single page", __func__));
@ -6111,9 +6111,8 @@ pmap_dcache_wb_pou(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
if (*sysmaps->CMAP3)
panic("%s: CMAP3 busy", __func__);
pte2_store(sysmaps->CMAP3, PTE2_KERN_NG(pa, PTE2_AP_KRW, ma));
va = (vm_offset_t)sysmaps->CADDR3;
tlb_flush_local(va);
dcache_wb_pou(va, size);
tlb_flush_local((vm_offset_t)sysmaps->CADDR3);
dcache_wb_pou((vm_offset_t)sysmaps->CADDR3 + (pa & PAGE_MASK), size);
pte2_clear(sysmaps->CMAP3);
sched_unpin();
mtx_unlock(&sysmaps->lock);