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Add support for the ServerWorks CSB5 chips
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b8fdc2f91e
commit
2c66127540
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=92573
@ -748,6 +748,49 @@ ata_dmainit(struct ata_channel *ch, int device,
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atadev->mode = ATA_PIO0 + apiomode;
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atadev->mode = ATA_PIO0 + apiomode;
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return;
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return;
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case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
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if (udmamode >= 5 && pci_get_revid(parent) >= 0x92) {
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error = ata_command(atadev, ATA_C_SETFEATURES, 0,
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ATA_UDMA5, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_prtdev(atadev, "%s setting UDMA5 on ServerWorks chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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u_int16_t reg56;
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pci_write_config(parent, 0x54,
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pci_read_config(parent, 0x54, 1) |
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(0x01 << devno), 1);
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reg56 = pci_read_config(parent, 0x56, 2);
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reg56 &= ~(0xf << (devno * 4));
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reg56 |= (0x5 << (devno * 4));
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pci_write_config(parent, 0x56, reg56, 2);
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atadev->mode = ATA_UDMA5;
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return;
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}
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}
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if (udmamode >= 4) {
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error = ata_command(atadev, ATA_C_SETFEATURES, 0,
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ATA_UDMA4, ATA_C_F_SETXFER, ATA_WAIT_READY);
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if (bootverbose)
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ata_prtdev(atadev, "%s setting UDMA4 on ServerWorks chip\n",
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(error) ? "failed" : "success");
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if (!error) {
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u_int16_t reg56;
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pci_write_config(parent, 0x54,
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pci_read_config(parent, 0x54, 1) |
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(0x01 << devno), 1);
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reg56 = pci_read_config(parent, 0x56, 2);
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reg56 &= ~(0xf << (devno * 4));
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reg56 |= (0x4 << (devno * 4));
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pci_write_config(parent, 0x56, reg56, 2);
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atadev->mode = ATA_UDMA4;
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return;
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}
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}
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/* FALLTHROUGH */
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case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
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case 0x02111166: /* ServerWorks ROSB4 ATA33 controller */
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if (udmamode >= 2) {
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if (udmamode >= 2) {
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error = ata_command(atadev, ATA_C_SETFEATURES, 0,
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error = ata_command(atadev, ATA_C_SETFEATURES, 0,
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@ -227,6 +227,12 @@ ata_pci_match(device_t dev)
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case 0x02111166:
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case 0x02111166:
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return "ServerWorks ROSB4 ATA33 controller";
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return "ServerWorks ROSB4 ATA33 controller";
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case 0x02121166:
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if (pci_get_revid(dev) >= 0x92)
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return "ServerWorks CSB5 ATA100 controller";
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else
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return "ServerWorks CSB5 ATA66 controller";
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case 0x4d33105a:
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case 0x4d33105a:
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return "Promise ATA33 controller";
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return "Promise ATA33 controller";
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@ -392,7 +398,7 @@ ata_pci_attach(device_t dev)
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ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
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ATA_OUTB(controller->bmio, 0x1f, ATA_INB(controller->bmio, 0x1f)|0x01);
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break;
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break;
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case 0x00041103: /* HighPoint HPT366/368/370/372 */
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case 0x00041103: /* HighPoint HPT366/368/370/372 */
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if (pci_get_revid(dev) < 2) { /* HPT 366 */
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if (pci_get_revid(dev) < 2) { /* HPT 366 */
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/* turn off interrupt prediction */
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/* turn off interrupt prediction */
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pci_write_config(dev, 0x51,
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pci_write_config(dev, 0x51,
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@ -410,8 +416,8 @@ ata_pci_attach(device_t dev)
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pci_write_config(dev, 0x5b, 0x22, 1);
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pci_write_config(dev, 0x5b, 0x22, 1);
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break;
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break;
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case 0x00051103: /* HighPoint HPT372 */
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case 0x00051103: /* HighPoint HPT372 */
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case 0x00081103: /* HighPoint HPT374 */
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case 0x00081103: /* HighPoint HPT374 */
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/* turn off interrupt prediction */
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/* turn off interrupt prediction */
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pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
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pci_write_config(dev, 0x51, (pci_read_config(dev, 0x51, 1) & ~0x03), 1);
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pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
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pci_write_config(dev, 0x55, (pci_read_config(dev, 0x55, 1) & ~0x03), 1);
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@ -459,9 +465,15 @@ ata_pci_attach(device_t dev)
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pci_write_config(dev, 0x68, DEV_BSIZE, 2);
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pci_write_config(dev, 0x68, DEV_BSIZE, 2);
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break;
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break;
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case 0x10001042: /* RZ 100? known bad, no DMA */
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case 0x02121166: /* ServerWorks CSB5 ATA66/100 controller */
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pci_write_config(dev, 0x5a,
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(pci_read_config(dev, 0x5a, 1) & ~0x40) |
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(pci_get_revid(dev) >= 0x92) ? 0x03 : 0x02, 1);
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break;
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case 0x10001042: /* RZ 100? known bad, no DMA */
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case 0x10011042:
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case 0x10011042:
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case 0x06401095: /* CMD 640 known bad, no DMA */
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case 0x06401095: /* CMD 640 known bad, no DMA */
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controller->bmio = NULL;
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controller->bmio = NULL;
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device_printf(dev, "Busmastering DMA disabled\n");
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device_printf(dev, "Busmastering DMA disabled\n");
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}
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}
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