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riscv: remove more riscv64sf support

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Remove a few more bits of riscv64sf support in libc and libm.

Reduce floating point ABI checks to requiring double hard float.

Reviewed by:	imp, jhb
Fixes:		1ca12bd927 Remove the riscv64sf architecture.
Differential Revision:	https://reviews.freebsd.org/D44334
This commit is contained in:
Brooks Davis 2024-03-21 23:46:28 +00:00
parent 1947a9383e
commit 312a05c39e
4 changed files with 2 additions and 47 deletions
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10
lib/libc/riscv/gen/flt_rounds.c
View File

@ -37,22 +37,12 @@
#include <fenv.h>
#include <float.h>
#ifdef __riscv_float_abi_soft
#include "softfloat-for-gcc.h"
#include "milieu.h"
#include "softfloat.h"
#endif
int
__flt_rounds(void)
{
uint64_t mode;
#ifdef __riscv_float_abi_soft
mode = __softfloat_float_rounding_mode;
#else
__asm __volatile("csrr %0, fcsr" : "=r" (mode));
#endif
switch (mode & _ROUND_MASK) {
case FE_TOWARDZERO:

1
lib/msun/riscv/Symbol.map
View File

@ -4,7 +4,6 @@ FBSD_1.3 {
fegetenv;
feholdexcept;
feupdateenv;
fegetexcept;
};
FBSD_1.8 {

8
lib/msun/riscv/fenv.c
View File

@ -37,14 +37,6 @@
*/
const fenv_t __fe_dfl_env = 0;
#ifdef __riscv_float_abi_soft
#define __set_env(env, flags, mask, rnd) env = ((flags) | (rnd) << 5)
#define __env_flags(env) ((env) & FE_ALL_EXCEPT)
#define __env_mask(env) (0) /* No exception traps. */
#define __env_round(env) (((env) >> 5) & _ROUND_MASK)
#include "fenv-softfloat.h"
#endif
extern inline int feclearexcept(int __excepts);
extern inline int fegetexceptflag(fexcept_t *__flagp, int __excepts);
extern inline int fesetexceptflag(const fexcept_t *__flagp, int __excepts);

30
lib/msun/riscv/fenv.h
View File

@ -71,32 +71,13 @@ __BEGIN_DECLS
extern const fenv_t __fe_dfl_env;
#define FE_DFL_ENV (&__fe_dfl_env)
#if !defined(__riscv_float_abi_soft) && !defined(__riscv_float_abi_double)
#if defined(__riscv_float_abi_single)
#error single precision floating point ABI not supported
#else
#error compiler did not set soft/hard float macros
#endif
#ifndef __riscv_float_abi_double
#error only double hard float ABI supported
#endif
#ifndef __riscv_float_abi_soft
#define __rfs(__fcsr) __asm __volatile("csrr %0, fcsr" : "=r" (__fcsr))
#define __wfs(__fcsr) __asm __volatile("csrw fcsr, %0" :: "r" (__fcsr))
#endif
#ifdef __riscv_float_abi_soft
int feclearexcept(int __excepts);
int fegetexceptflag(fexcept_t *__flagp, int __excepts);
int fesetexceptflag(const fexcept_t *__flagp, int __excepts);
int feraiseexcept(int __excepts);
int fetestexcept(int __excepts);
int fegetround(void);
int fesetround(int __round);
int fegetenv(fenv_t *__envp);
int feholdexcept(fenv_t *__envp);
int fesetenv(const fenv_t *__envp);
int feupdateenv(const fenv_t *__envp);
#else
__fenv_static inline int
feclearexcept(int __excepts)
{
@ -212,15 +193,9 @@ feupdateenv(const fenv_t *__envp)
return (0);
}
#endif /* !__riscv_float_abi_soft */
#if __BSD_VISIBLE
#ifdef __riscv_float_abi_soft
int feenableexcept(int __mask);
int fedisableexcept(int __mask);
int fegetexcept(void);
#else
__fenv_static inline int
feenableexcept(int __mask __unused)
{
@ -248,7 +223,6 @@ fegetexcept(void)
return (0);
}
#endif /* !__riscv_float_abi_soft */
#endif /* __BSD_VISIBLE */