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libcrypto: Update assembly build glue for x86 for OpenSSL 3.0.
Notably, define AES_ASM which is required for any AES acceleration (OpenSSL 1.0 gated all AES acceleration on OPENSSL_CPUID_OBJ instead). Enabling this exposed that new assembly files added in OpenSSL 3.0 needed to be included in the build (aes-x86-64.S and aes-586.S). Both of these files supplant both aes_core.c and aes_cbc.c. The last file had to be moved out of the MI SRCS line for aes and into each ASM_* for non-x86. As part of this I audited the generated configdata.pm for amd64, i386, and aarch64 and found the following additional discrepecancies that are fixed here as well: - Enabled BSAES_ASM on amd64 which requires bsase-x86_64.S - Enabled WHIRLPOOL_ASM on amd64 (asm sources already built) - Enabled CMLL_ASM on amd64 and i386 (asm sources already built) aarch64 had no discreprecancies in configdata.pm, and no *.pl asm generators were missing for aarch64 in Makefile.asm. I did not check powerpc or armv7, but for armv7 all of the asm generators seem to be present in Makefile.asm. Reported by: gallatin (AES-GCM using plain software on amd64) Reviewed by: gallatin, ngie, emaste Differential Revision: https://reviews.freebsd.org/D41539
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@ -41,25 +41,25 @@ SRCS+= mem_clr.c
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.endif
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# aes
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SRCS+= aes_cbc.c aes_cfb.c aes_ecb.c aes_ige.c aes_misc.c aes_ofb.c aes_wrap.c
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SRCS+= aes_cfb.c aes_ecb.c aes_ige.c aes_misc.c aes_ofb.c aes_wrap.c
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.if defined(ASM_aarch64)
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SRCS+= aes_core.c aesv8-armx.S vpaes-armv8.S
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SRCS+= aes_cbc.c aes_core.c aesv8-armx.S vpaes-armv8.S
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ACFLAGS.aesv8-armx.S= -march=armv8-a+crypto
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.elif defined(ASM_amd64)
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SRCS+= aes_core.c aesni-mb-x86_64.S aesni-sha1-x86_64.S aesni-sha256-x86_64.S
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SRCS+= aesni-x86_64.S vpaes-x86_64.S
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SRCS+= aes-x86_64.S aesni-mb-x86_64.S aesni-sha1-x86_64.S
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SRCS+= aesni-sha256-x86_64.S aesni-x86_64.S bsaes-x86_64.S vpaes-x86_64.S
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.elif defined(ASM_arm)
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SRCS+= aes-armv4.S aesv8-armx.S bsaes-armv7.S
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SRCS+= aes_cbc.c aes-armv4.S aesv8-armx.S bsaes-armv7.S
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.elif defined(ASM_i386)
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SRCS+= aes_core.c aesni-x86.S vpaes-x86.S
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SRCS+= aes-586.S aesni-x86.S vpaes-x86.S
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.elif defined(ASM_powerpc)
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SRCS+= aes_core.c aes-ppc.S vpaes-ppc.S aesp8-ppc.S
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SRCS+= aes_cbc.c aes_core.c aes-ppc.S vpaes-ppc.S aesp8-ppc.S
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.elif defined(ASM_powerpc64)
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SRCS+= aes_core.c aes-ppc.S vpaes-ppc.S aesp8-ppc.S
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SRCS+= aes_cbc.c aes_core.c aes-ppc.S vpaes-ppc.S aesp8-ppc.S
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.elif defined(ASM_powerpc64le)
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SRCS+= aes_core.c aes-ppc.S vpaes-ppc.S aesp8-ppc.S
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SRCS+= aes_cbc.c aes_core.c aes-ppc.S vpaes-ppc.S aesp8-ppc.S
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.else
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SRCS+= aes_core.c
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SRCS+= aes_cbc.c aes_core.c
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.endif
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# asn1
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@ -32,8 +32,12 @@ CFLAGS+= -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM
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CFLAGS+= -DKECCAK1600_ASM
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CFLAGS+= -DRC4_ASM
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CFLAGS+= -DMD5_ASM
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CFLAGS+= -DAES_ASM
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CFLAGS+= -DBSAES_ASM
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CFLAGS+= -DVPAES_ASM
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CFLAGS+= -DWHIRLPOOL_ASM
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CFLAGS+= -DGHASH_ASM
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CFLAGS+= -DCMLL_ASM
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CFLAGS+= -DECP_NISTZ256_ASM -DX25519_ASM
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CFLAGS+= -DPADLOCK_ASM
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CFLAGS+= -DPOLY1305_ASM
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@ -53,9 +57,11 @@ CFLAGS+= -DSHA1_ASM -DSHA256_ASM -DSHA512_ASM
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CFLAGS+= -DRC4_ASM
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CFLAGS+= -DMD5_ASM
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CFLAGS+= -DRMD160_ASM
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CFLAGS+= -DAES_ASM
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CFLAGS+= -DVPAES_ASM
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CFLAGS+= -DWHIRLPOOL_ASM
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CFLAGS+= -DGHASH_ASM
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CFLAGS+= -DCMLL_ASM
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CFLAGS+= -DECP_NISTZ256_ASM
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CFLAGS+= -DPADLOCK_ASM
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CFLAGS+= -DPOLY1305_ASM
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