mirror of
https://git.FreeBSD.org/src.git
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cxgbe(4): Update the bundled T4 and T5 firmwares to versions 1.11.27.0.
Obtained from: Chelsio MFC after: 3 days
This commit is contained in:
Navdeep Parhar
parent
298207c39a
commit
327235b3d6
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=267757
@ -1167,7 +1167,7 @@ t4fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t4fw.fwo"
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t4fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.9.12.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t4fw.fw"
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@ -1191,7 +1191,7 @@ t5fw.fwo optional cxgbe \
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no-implicit-rule \
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clean "t5fw.fwo"
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t5fw.fw optional cxgbe \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.9.12.0.bin.uu" \
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dependency "$S/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu" \
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compile-with "${NORMAL_FW}" \
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no-obj no-implicit-rule \
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clean "t5fw.fw"
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9019
sys/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu
Normal file
9019
sys/dev/cxgbe/firmware/t4fw-1.11.27.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
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# Chelsio T4 Factory Default configuration file.
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#
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# Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
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# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved.
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#
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# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
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# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
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@ -496,6 +496,8 @@
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# dwm: minimum delta between high and low watermark (in units of 100
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# Bytes)
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#
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#
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[port "0"]
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dcb = ppp, dcbx # configure for DCB PPP and enable DCBX offload
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bg_mem = 25
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@ -503,6 +505,9 @@
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hwm = 30
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lwm = 15
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dwm = 30
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dcb_app_tlv[0] = 0x8906, ethertype, 3
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dcb_app_tlv[1] = 0x8914, ethertype, 3
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dcb_app_tlv[2] = 3260, socketnum, 5
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[port "1"]
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dcb = ppp, dcbx
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@ -511,6 +516,9 @@
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hwm = 30
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lwm = 15
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dwm = 30
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dcb_app_tlv[0] = 0x8906, ethertype, 3
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dcb_app_tlv[1] = 0x8914, ethertype, 3
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dcb_app_tlv[2] = 3260, socketnum, 5
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[port "2"]
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dcb = ppp, dcbx
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@ -519,6 +527,9 @@
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hwm = 30
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lwm = 15
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dwm = 30
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dcb_app_tlv[0] = 0x8906, ethertype, 3
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dcb_app_tlv[1] = 0x8914, ethertype, 3
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dcb_app_tlv[2] = 3260, socketnum, 5
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[port "3"]
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dcb = ppp, dcbx
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@ -527,10 +538,13 @@
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hwm = 30
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lwm = 15
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dwm = 30
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dcb_app_tlv[0] = 0x8906, ethertype, 3
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dcb_app_tlv[1] = 0x8914, ethertype, 3
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dcb_app_tlv[2] = 3260, socketnum, 5
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[fini]
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version = 0x14250010
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checksum = 0x5a5526c3
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version = 0x14250012
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checksum = 0xd9ae0325
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# Total resources used by above allocations:
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# Virtual Interfaces: 104
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@ -1,5 +1,5 @@
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/*-
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* Copyright (c) 2012 Chelsio Communications, Inc.
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* Copyright (c) 2012-2014 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -100,7 +100,7 @@ enum fw_wr_opcodes {
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FW_ETH_TX_PKT_WR = 0x08,
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FW_ETH_TX_PKT2_WR = 0x44,
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FW_ETH_TX_PKTS_WR = 0x09,
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FW_ETH_TX_UO_WR = 0x1c,
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FW_ETH_TX_EO_WR = 0x1c,
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FW_EQ_FLUSH_WR = 0x1b,
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FW_OFLD_CONNECTION_WR = 0x2f,
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FW_FLOWC_WR = 0x0a,
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@ -647,21 +647,70 @@ struct fw_eth_tx_pkts_wr {
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__u8 type;
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};
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struct fw_eth_tx_uo_wr {
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enum fw_eth_tx_eo_type {
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FW_ETH_TX_EO_TYPE_UDPSEG,
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FW_ETH_TX_EO_TYPE_TCPSEG,
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FW_ETH_TX_EO_TYPE_NVGRESEG,
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};
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struct fw_eth_tx_eo_wr {
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__be32 op_immdlen;
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__be32 equiq_to_len16;
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__be64 r3;
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__u8 r4;
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__u8 ethlen;
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__be16 iplen;
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__u8 udplen;
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__u8 rtplen;
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__be16 r5;
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__be16 mss;
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__be16 schedpktsize;
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__be32 length;
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union fw_eth_tx_eo {
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struct fw_eth_tx_eo_udpseg {
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__u8 type;
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__u8 ethlen;
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__be16 iplen;
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__u8 udplen;
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__u8 rtplen;
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__be16 r4;
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__be16 mss;
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__be16 schedpktsize;
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__be32 plen;
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} udpseg;
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struct fw_eth_tx_eo_tcpseg {
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__u8 type;
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__u8 ethlen;
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__be16 iplen;
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__u8 tcplen;
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__u8 tsclk_tsoff;
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__be16 r4;
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__be16 mss;
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__be16 r5;
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__be32 plen;
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} tcpseg;
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struct fw_eth_tx_eo_nvgreseg {
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__u8 type;
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__u8 iphdroffout;
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__be16 grehdroff;
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__be16 iphdroffin;
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__be16 tcphdroffin;
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__be16 mss;
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__be16 r4;
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__be32 plen;
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} nvgreseg;
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} u;
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};
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#define S_FW_ETH_TX_EO_WR_IMMDLEN 0
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#define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff
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#define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN)
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#define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \
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(((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN)
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#define S_FW_ETH_TX_EO_WR_TSCLK 6
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#define M_FW_ETH_TX_EO_WR_TSCLK 0x3
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#define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK)
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#define G_FW_ETH_TX_EO_WR_TSCLK(x) \
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(((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK)
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#define S_FW_ETH_TX_EO_WR_TSOFF 0
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#define M_FW_ETH_TX_EO_WR_TSOFF 0x3f
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#define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF)
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#define G_FW_ETH_TX_EO_WR_TSOFF(x) \
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(((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF)
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struct fw_eq_flush_wr {
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__u8 opcode;
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__u8 r1[3];
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@ -794,13 +843,13 @@ enum fw_flowc_mnem_tcpstate {
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FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */
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};
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enum fw_flowc_mnem_uostate {
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FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */
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FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */
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FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending
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enum fw_flowc_mnem_eostate {
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FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */
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FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */
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FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending
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* outstanding payload
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*/
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FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after
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FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after
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* discarding outstanding payload
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*/
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};
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@ -816,7 +865,7 @@ enum fw_flowc_mnem {
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FW_FLOWC_MNEM_MSS = 7,
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FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8,
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FW_FLOWC_MNEM_TCPSTATE = 9,
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FW_FLOWC_MNEM_UOSTATE = 10,
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FW_FLOWC_MNEM_EOSTATE = 10,
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FW_FLOWC_MNEM_SCHEDCLASS = 11,
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FW_FLOWC_MNEM_DCBPRIO = 12,
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};
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@ -3525,6 +3574,15 @@ enum fw_caps_config_fcoe {
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FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010,
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};
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enum fw_memtype_cf {
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FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0,
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FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1,
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FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM,
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FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH,
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FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL,
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FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1,
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};
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struct fw_caps_config_cmd {
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__be32 op_to_write;
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__be32 cfvalid_to_len16;
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@ -3612,6 +3670,7 @@ enum fw_params_param_dev {
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FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15,
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FW_PARAMS_PARAM_DEV_MCINIT = 0x16,
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FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17,
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FW_PARAMS_PARAM_DEV_FWCACHE = 0x18,
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};
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/*
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@ -3691,14 +3750,19 @@ enum fw_params_param_dev_bypass {
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FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2,
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};
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enum fw_params_phyfw_actions {
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FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00,
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FW_PARAMS_PARAM_PHYFW_VERSION = 0x01,
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enum fw_params_param_dev_phyfw {
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FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00,
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FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01,
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};
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enum fw_params_param_dev_diag {
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FW_PARAM_DEV_DIAG_TMP = 0x00,
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FW_PARAM_DEV_DIAG_VDD = 0x01,
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FW_PARAM_DEV_DIAG_TMP = 0x00,
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FW_PARAM_DEV_DIAG_VDD = 0x01,
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};
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enum fw_params_param_dev_fwcache {
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FW_PARAM_DEV_FWCACHE_FLUSH = 0x00,
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FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01,
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};
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#define S_FW_PARAMS_MNEM 24
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@ -4553,7 +4617,7 @@ struct fw_eq_eth_cmd {
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__be32 fetchszm_to_iqid;
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__be32 dcaen_to_eqsize;
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__be64 eqaddr;
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__be32 viid_pkd;
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__be32 autoequiqe_to_viid;
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__be32 r8_lo;
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__be64 r9;
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};
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@ -4728,6 +4792,20 @@ struct fw_eq_eth_cmd {
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#define G_FW_EQ_ETH_CMD_EQSIZE(x) \
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(((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE)
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#define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31
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#define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1
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#define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE)
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#define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \
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(((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE)
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#define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U)
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#define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30
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#define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1
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#define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE)
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#define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \
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(((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE)
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#define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U)
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#define S_FW_EQ_ETH_CMD_VIID 16
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#define M_FW_EQ_ETH_CMD_VIID 0xfff
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#define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID)
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@ -5680,18 +5758,19 @@ enum fw_port_action {
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FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011,
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FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012,
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FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020,
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FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021,
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FW_PORT_ACTION_MAC_LPBK = 0x0022,
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FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023,
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FW_PORT_ACTION_L1_EXT_LPBK = 0x0026,
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FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022,
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FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023,
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FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025,
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FW_PORT_ACTION_LPBK_SS_EXT = 0x0026,
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FW_PORT_ACTION_DIAGNOSTICS = 0x0027,
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FW_PORT_ACTION_PCS_LPBK = 0x0028,
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FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028,
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FW_PORT_ACTION_PHY_RESET = 0x0040,
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FW_PORT_ACTION_PMA_RESET = 0x0041,
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FW_PORT_ACTION_PCS_RESET = 0x0042,
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FW_PORT_ACTION_PHYXS_RESET = 0x0043,
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FW_PORT_ACTION_DTEXS_REEST = 0x0044,
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FW_PORT_ACTION_AN_RESET = 0x0045,
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};
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enum fw_port_l2cfg_ctlbf {
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@ -5704,6 +5783,20 @@ enum fw_port_l2cfg_ctlbf {
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FW_PORT_L2_CTLBF_MTU = 0x40
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};
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enum fw_dcb_app_tlv_sf {
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FW_DCB_APP_SF_ETHERTYPE,
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FW_DCB_APP_SF_SOCKET_TCP,
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FW_DCB_APP_SF_SOCKET_UDP,
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FW_DCB_APP_SF_SOCKET_ALL,
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};
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enum fw_port_dcb_versions {
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FW_PORT_DCB_VER_CEE1D0,
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FW_PORT_DCB_VER_CEE1D01,
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FW_PORT_DCB_VER_IEEE,
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FW_PORT_DCB_VER_UNKNOWN=7
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};
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enum fw_port_dcb_cfg {
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FW_PORT_DCB_CFG_PG = 0x01,
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FW_PORT_DCB_CFG_PFC = 0x02,
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@ -5724,10 +5817,18 @@ enum fw_port_dcb_type {
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FW_PORT_DCB_TYPE_CONTROL = 0x05,
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};
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enum fw_port_dcb_feature_state {
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FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0,
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FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1,
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FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2,
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FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3,
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};
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enum fw_port_diag_ops {
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FW_PORT_DIAGS_TEMP = 0x00,
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FW_PORT_DIAGS_TX_POWER = 0x01,
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FW_PORT_DIAGS_RX_POWER = 0x02,
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FW_PORT_DIAGS_TX_DIS = 0x03,
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};
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struct fw_port_cmd {
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@ -5760,7 +5861,9 @@ struct fw_port_cmd {
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__be16 mtu;
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__u8 cbllen;
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__u8 auxlinfo;
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__be32 r8;
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__u8 dcbxdis_pkd;
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__u8 r8_lo;
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__be16 lpcap;
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__be64 r9;
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} info;
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struct fw_port_diags {
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@ -5792,7 +5895,8 @@ struct fw_port_cmd {
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struct fw_port_dcb_pfc {
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__u8 type;
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__u8 pfcen;
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__be16 r10[3];
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__u8 r10[5];
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__u8 max_pfc_tcs;
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__be64 r11;
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} pfc;
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struct fw_port_app_priority {
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@ -5807,8 +5911,9 @@ struct fw_port_cmd {
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struct fw_port_dcb_control {
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__u8 type;
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__u8 all_syncd_pkd;
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__be16 r10_lo[3];
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__be64 r11;
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__be16 pfc_state_to_app_state;
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__be32 r11;
|
||||
__be64 r12;
|
||||
} control;
|
||||
} dcb;
|
||||
} u;
|
||||
@ -5953,6 +6058,13 @@ struct fw_port_cmd {
|
||||
#define G_FW_PORT_CMD_MODTYPE(x) \
|
||||
(((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE)
|
||||
|
||||
#define S_FW_PORT_CMD_DCBXDIS 7
|
||||
#define M_FW_PORT_CMD_DCBXDIS 0x1
|
||||
#define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS)
|
||||
#define G_FW_PORT_CMD_DCBXDIS(x) \
|
||||
(((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS)
|
||||
#define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U)
|
||||
|
||||
#define S_FW_PORT_CMD_APPLY 7
|
||||
#define M_FW_PORT_CMD_APPLY 0x1
|
||||
#define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY)
|
||||
@ -5967,10 +6079,32 @@ struct fw_port_cmd {
|
||||
(((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD)
|
||||
#define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U)
|
||||
|
||||
#define S_FW_PORT_CMD_PFC_STATE 8
|
||||
#define M_FW_PORT_CMD_PFC_STATE 0xf
|
||||
#define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE)
|
||||
#define G_FW_PORT_CMD_PFC_STATE(x) \
|
||||
(((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE)
|
||||
|
||||
#define S_FW_PORT_CMD_ETS_STATE 4
|
||||
#define M_FW_PORT_CMD_ETS_STATE 0xf
|
||||
#define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE)
|
||||
#define G_FW_PORT_CMD_ETS_STATE(x) \
|
||||
(((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE)
|
||||
|
||||
#define S_FW_PORT_CMD_APP_STATE 0
|
||||
#define M_FW_PORT_CMD_APP_STATE 0xf
|
||||
#define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE)
|
||||
#define G_FW_PORT_CMD_APP_STATE(x) \
|
||||
(((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE)
|
||||
|
||||
/*
|
||||
* These are configured into the VPD and hence tools that generate
|
||||
* VPD may use this enumeration.
|
||||
* extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed
|
||||
*
|
||||
* REMEMBER:
|
||||
* Update the Common Code t4_hw.c:t4_get_port_type_description()
|
||||
* with any new Firmware Port Technology Types!
|
||||
*/
|
||||
enum fw_port_type {
|
||||
FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */
|
||||
@ -7657,6 +7791,17 @@ enum pcie_fw_eval {
|
||||
(((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED)
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* P C I E F W P F 0 R E G I S T E R
|
||||
**********************************************/
|
||||
|
||||
/*
|
||||
* this register is available as 32-bit of persistent storage (accross
|
||||
* PL_RST based chip-reset) for boot drivers (i.e. firmware and driver
|
||||
* will not write it)
|
||||
*/
|
||||
|
||||
|
||||
/******************************************************************************
|
||||
* B I N A R Y H E A D E R F O R M A T
|
||||
**********************************************/
|
||||
@ -7720,13 +7865,13 @@ enum fw_hdr_chip {
|
||||
|
||||
enum {
|
||||
T4FW_VERSION_MAJOR = 0x01,
|
||||
T4FW_VERSION_MINOR = 0x09,
|
||||
T4FW_VERSION_MICRO = 0x0c,
|
||||
T4FW_VERSION_MINOR = 0x0b,
|
||||
T4FW_VERSION_MICRO = 0x1b,
|
||||
T4FW_VERSION_BUILD = 0x00,
|
||||
|
||||
T5FW_VERSION_MAJOR = 0x01,
|
||||
T5FW_VERSION_MINOR = 0x09,
|
||||
T5FW_VERSION_MICRO = 0x0c,
|
||||
T5FW_VERSION_MINOR = 0x0b,
|
||||
T5FW_VERSION_MICRO = 0x1b,
|
||||
T5FW_VERSION_BUILD = 0x00,
|
||||
};
|
||||
|
||||
|
||||
9028
sys/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu
Normal file
9028
sys/dev/cxgbe/firmware/t5fw-1.11.27.0.bin.uu
Normal file
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -1,6 +1,6 @@
|
||||
# Chelsio T5 Factory Default configuration file.
|
||||
#
|
||||
# Copyright (C) 2010-2013 Chelsio Communications. All rights reserved.
|
||||
# Copyright (C) 2010-2014 Chelsio Communications. All rights reserved.
|
||||
#
|
||||
# DO NOT MODIFY THIS FILE UNDER ANY CIRCUMSTANCES. MODIFICATION OF
|
||||
# THIS FILE WILL RESULT IN A NON-FUNCTIONAL T4 ADAPTER AND MAY RESULT
|
||||
@ -177,6 +177,9 @@
|
||||
# TP_GLOBAL_CONFIG
|
||||
reg[0x7d08] = 0x00000800/0x00000800 # set IssFromCplEnable
|
||||
|
||||
# TP_PC_CONFIG
|
||||
reg[0x7d48] = 0x00000000/0x00000400 # clear EnableFLMError
|
||||
|
||||
# TP_PARA_REG0
|
||||
reg[0x7d60] = 0x06000000/0x07000000 # set InitCWND to 6
|
||||
|
||||
@ -433,7 +436,7 @@
|
||||
pmask = all # access to all four ports ...
|
||||
nserver = 16
|
||||
nhash = 2048
|
||||
tp_l2t = 1024
|
||||
tp_l2t = 1020
|
||||
protocol = iscsi_initiator_fofld
|
||||
tp_ddp_iscsi = 2
|
||||
iscsi_ntask = 2048
|
||||
@ -454,6 +457,7 @@
|
||||
cmask = all # access to all channels
|
||||
pmask = all # access to all four ports ...
|
||||
nhash = 2048
|
||||
tp_l2t = 4
|
||||
protocol = fcoe_initiator
|
||||
tp_ddp = 2
|
||||
fcoe_nfcf = 16
|
||||
@ -544,6 +548,9 @@
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
[port "1"]
|
||||
dcb = ppp, dcbx
|
||||
@ -552,6 +559,9 @@
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
[port "2"]
|
||||
dcb = ppp, dcbx
|
||||
@ -560,6 +570,9 @@
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
[port "3"]
|
||||
dcb = ppp, dcbx
|
||||
@ -568,10 +581,13 @@
|
||||
hwm = 30
|
||||
lwm = 15
|
||||
dwm = 30
|
||||
dcb_app_tlv[0] = 0x8906, ethertype, 3
|
||||
dcb_app_tlv[1] = 0x8914, ethertype, 3
|
||||
dcb_app_tlv[2] = 3260, socketnum, 5
|
||||
|
||||
[fini]
|
||||
version = 0x14250013
|
||||
checksum = 0xd66f5b23
|
||||
version = 0x14250016
|
||||
checksum = 0x5d740273
|
||||
|
||||
# Total resources used by above allocations:
|
||||
# Virtual Interfaces: 104
|
||||
|
||||
@ -351,7 +351,7 @@ alloc_nm_txq_hwq(struct port_info *pi, struct sge_nm_txq *nm_txq)
|
||||
V_FW_EQ_ETH_CMD_VFN(0));
|
||||
c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
|
||||
F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
|
||||
c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->nm_viid));
|
||||
c.autoequiqe_to_viid = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->nm_viid));
|
||||
c.fetchszm_to_iqid =
|
||||
htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
|
||||
V_FW_EQ_ETH_CMD_PCIECHN(pi->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
|
||||
|
||||
@ -2827,7 +2827,7 @@ eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
|
||||
V_FW_EQ_ETH_CMD_VFN(0));
|
||||
c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
|
||||
F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
|
||||
c.viid_pkd = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
|
||||
c.autoequiqe_to_viid = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
|
||||
c.fetchszm_to_iqid =
|
||||
htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
|
||||
V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS += ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T4FW_VER = 1.9.12.0
|
||||
T4FW_VER = 1.11.27.0
|
||||
FIRMWS += t4fw.fw:t4fw:${T4FW_VER}
|
||||
CLEANFILES += t4fw.fw
|
||||
|
||||
|
||||
@ -17,7 +17,7 @@ FIRMWS += ${F}:${F:C/.txt//}:1.0.0.0
|
||||
.endif
|
||||
.endfor
|
||||
|
||||
T5FW_VER = 1.9.12.0
|
||||
T5FW_VER = 1.11.27.0
|
||||
FIRMWS += t5fw.fw:t5fw:${T5FW_VER}
|
||||
CLEANFILES += t5fw.fw
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user