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Use more specific local variable pointers to narrow some expressions.
MFC after: 1 week
This commit is contained in:
John Baldwin
parent
e11cc001a9
commit
361cf3bd02
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=169219
@ -1013,29 +1013,29 @@ void
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pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msix *msix = &dinfo->cfg.msix;
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uint32_t offset;
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KASSERT(cfg->msix.msix_alloc > index, ("bogus index"));
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offset = cfg->msix.msix_table_offset + index * 16;
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bus_write_4(cfg->msix.msix_table_res, offset, address & 0xffffffff);
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bus_write_4(cfg->msix.msix_table_res, offset + 4, address >> 32);
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bus_write_4(cfg->msix.msix_table_res, offset + 8, data);
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KASSERT(msix->msix_alloc > index, ("bogus index"));
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offset = msix->msix_table_offset + index * 16;
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bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
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bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
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bus_write_4(msix->msix_table_res, offset + 8, data);
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}
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void
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pci_mask_msix(device_t dev, u_int index)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msix *msix = &dinfo->cfg.msix;
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uint32_t offset, val;
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KASSERT(cfg->msix.msix_msgnum > index, ("bogus index"));
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offset = cfg->msix.msix_table_offset + index * 16 + 12;
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val = bus_read_4(cfg->msix.msix_table_res, offset);
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KASSERT(msix->msix_msgnum > index, ("bogus index"));
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offset = msix->msix_table_offset + index * 16 + 12;
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val = bus_read_4(msix->msix_table_res, offset);
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if (!(val & PCIM_MSIX_VCTRL_MASK)) {
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val |= PCIM_MSIX_VCTRL_MASK;
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bus_write_4(cfg->msix.msix_table_res, offset, val);
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bus_write_4(msix->msix_table_res, offset, val);
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}
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}
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@ -1043,15 +1043,15 @@ void
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pci_unmask_msix(device_t dev, u_int index)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msix *msix = &dinfo->cfg.msix;
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uint32_t offset, val;
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KASSERT(cfg->msix.msix_alloc > index, ("bogus index"));
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offset = cfg->msix.msix_table_offset + index * 16 + 12;
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val = bus_read_4(cfg->msix.msix_table_res, offset);
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KASSERT(msix->msix_alloc > index, ("bogus index"));
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offset = msix->msix_table_offset + index * 16 + 12;
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val = bus_read_4(msix->msix_table_res, offset);
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if (val & PCIM_MSIX_VCTRL_MASK) {
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val &= ~PCIM_MSIX_VCTRL_MASK;
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bus_write_4(cfg->msix.msix_table_res, offset, val);
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bus_write_4(msix->msix_table_res, offset, val);
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}
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}
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@ -1059,13 +1059,13 @@ int
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pci_pending_msix(device_t dev, u_int index)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msix *msix = &dinfo->cfg.msix;
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uint32_t offset, bit;
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KASSERT(cfg->msix.msix_alloc > index, ("bogus index"));
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offset = cfg->msix.msix_pba_offset + (index / 32) * 4;
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KASSERT(msix->msix_alloc > index, ("bogus index"));
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offset = msix->msix_pba_offset + (index / 32) * 4;
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bit = 1 << index % 32;
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return (bus_read_4(cfg->msix.msix_pba_res, offset) & bit);
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return (bus_read_4(msix->msix_pba_res, offset) & bit);
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}
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/*
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@ -1285,16 +1285,16 @@ static int
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pci_release_msix(device_t dev, device_t child)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msix *msix = &dinfo->cfg.msix;
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struct resource_list_entry *rle;
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int count, i;
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/* Do we have any messages to release? */
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if (cfg->msix.msix_alloc == 0)
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if (msix->msix_alloc == 0)
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return (ENODEV);
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/* Make sure none of the resources are allocated. */
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for (i = 1, count = 0; count < cfg->msix.msix_alloc; i++) {
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for (i = 1, count = 0; count < msix->msix_alloc; i++) {
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rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i);
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if (rle == NULL)
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continue;
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@ -1303,13 +1303,13 @@ pci_release_msix(device_t dev, device_t child)
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count++;
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}
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/* Update control register with to disable MSI-X. */
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cfg->msix.msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
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pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
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cfg->msix.msix_ctrl, 2);
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/* Update control register to disable MSI-X. */
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msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
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pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
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msix->msix_ctrl, 2);
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/* Release the messages. */
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for (i = 1, count = 0; count < cfg->msix.msix_alloc; i++) {
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for (i = 1, count = 0; count < msix->msix_alloc; i++) {
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rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i);
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if (rle == NULL)
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continue;
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@ -1320,7 +1320,7 @@ pci_release_msix(device_t dev, device_t child)
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}
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/* Update alloc count. */
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cfg->msix.msix_alloc = 0;
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msix->msix_alloc = 0;
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return (0);
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}
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@ -1334,10 +1334,10 @@ int
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pci_msix_count_method(device_t dev, device_t child)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msix *msix = &dinfo->cfg.msix;
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if (pci_do_msix && cfg->msix.msix_location != 0)
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return (cfg->msix.msix_msgnum);
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if (pci_do_msix && msix->msix_location != 0)
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return (msix->msix_msgnum);
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return (0);
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}
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@ -1348,26 +1348,26 @@ void
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pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msi *msi = &dinfo->cfg.msi;
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/* Write data and address values. */
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cfg->msi.msi_addr = address;
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cfg->msi.msi_data = data;
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pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR,
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msi->msi_addr = address;
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msi->msi_data = data;
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pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
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address & 0xffffffff, 4);
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if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) {
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pci_write_config(dev, cfg->msi.msi_location +
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PCIR_MSI_ADDR_HIGH, address >> 32, 4);
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pci_write_config(dev, cfg->msi.msi_location +
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PCIR_MSI_DATA_64BIT, data, 2);
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if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
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pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
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address >> 32, 4);
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pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
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data, 2);
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} else
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pci_write_config(dev, cfg->msi.msi_location +
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PCIR_MSI_DATA, data, 2);
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pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
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2);
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/* Enable MSI in the control register. */
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cfg->msi.msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
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pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL,
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cfg->msi.msi_ctrl, 2);
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msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
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pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
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2);
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}
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/*
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@ -1379,26 +1379,26 @@ static void
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pci_resume_msi(device_t dev)
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{
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struct pci_devinfo *dinfo = device_get_ivars(dev);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msi *msi = &dinfo->cfg.msi;
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uint64_t address;
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uint16_t data;
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if (cfg->msi.msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
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address = cfg->msi.msi_addr;
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data = cfg->msi.msi_data;
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pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_ADDR,
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if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
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address = msi->msi_addr;
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data = msi->msi_data;
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pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
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address & 0xffffffff, 4);
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if (cfg->msi.msi_ctrl & PCIM_MSICTRL_64BIT) {
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pci_write_config(dev, cfg->msi.msi_location +
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if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
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pci_write_config(dev, msi->msi_location +
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PCIR_MSI_ADDR_HIGH, address >> 32, 4);
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pci_write_config(dev, cfg->msi.msi_location +
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pci_write_config(dev, msi->msi_location +
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PCIR_MSI_DATA_64BIT, data, 2);
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} else
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pci_write_config(dev, cfg->msi.msi_location +
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PCIR_MSI_DATA, data, 2);
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pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
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data, 2);
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}
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pci_write_config(dev, cfg->msi.msi_location + PCIR_MSI_CTRL,
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cfg->msi.msi_ctrl, 2);
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pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
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2);
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}
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/*
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@ -1556,7 +1556,7 @@ pci_alloc_msi_method(device_t dev, device_t child, int *count)
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}
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}
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/* Update control register with actual count and enable MSI. */
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/* Update control register with actual count. */
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ctrl = cfg->msi.msi_ctrl;
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ctrl &= ~PCIM_MSICTRL_MME_MASK;
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ctrl |= (ffs(actual) - 1) << 4;
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@ -1574,7 +1574,7 @@ int
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pci_release_msi_method(device_t dev, device_t child)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msi *msi = &dinfo->cfg.msi;
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struct resource_list_entry *rle;
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int error, i, irqs[32];
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@ -1584,12 +1584,12 @@ pci_release_msi_method(device_t dev, device_t child)
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return (error);
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/* Do we have any messages to release? */
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if (cfg->msi.msi_alloc == 0)
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if (msi->msi_alloc == 0)
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return (ENODEV);
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KASSERT(cfg->msi.msi_alloc <= 32, ("more than 32 alloc'd messages"));
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KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
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/* Make sure none of the resources are allocated. */
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for (i = 0; i < cfg->msi.msi_alloc; i++) {
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for (i = 0; i < msi->msi_alloc; i++) {
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rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
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KASSERT(rle != NULL, ("missing MSI resource"));
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if (rle->res != NULL)
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@ -1598,18 +1598,17 @@ pci_release_msi_method(device_t dev, device_t child)
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}
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/* Update control register with 0 count and disable MSI. */
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cfg->msi.msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE);
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pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL,
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cfg->msi.msi_ctrl, 2);
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msi->msi_ctrl &= ~(PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE);
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pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
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msi->msi_ctrl, 2);
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/* Release the messages. */
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PCIB_RELEASE_MSI(device_get_parent(dev), child, cfg->msi.msi_alloc,
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irqs);
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for (i = 0; i < cfg->msi.msi_alloc; i++)
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PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
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for (i = 0; i < msi->msi_alloc; i++)
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resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
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/* Update alloc count. */
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cfg->msi.msi_alloc = 0;
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msi->msi_alloc = 0;
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return (0);
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}
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@ -1623,10 +1622,10 @@ int
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pci_msi_count_method(device_t dev, device_t child)
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{
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struct pci_devinfo *dinfo = device_get_ivars(child);
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pcicfgregs *cfg = &dinfo->cfg;
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struct pcicfg_msi *msi = &dinfo->cfg.msi;
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if (pci_do_msi && cfg->msi.msi_location != 0)
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return (cfg->msi.msi_msgnum);
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if (pci_do_msi && msi->msi_location != 0)
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return (msi->msi_msgnum);
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return (0);
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}
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