mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-02 08:42:48 +00:00
Merge latest (commit c8c1b3a77934768c7f7a4a9c10140c8bec529059) files
from the git tree. This merges a lot that we're not using, but there's too many files to be selective and have a hope of catching everything. If there are conflicts with the rest of the tree, we'll resolve them on a case by case basis. MFC after: 2 weeks Sponsored by: Netflix, Inc.
This commit is contained in:
Warner Losh
commit
3a6a9a3bcc
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279385
119
sys/gnu/dts/arm/aks-cdu.dts
Normal file
119
sys/gnu/dts/arm/aks-cdu.dts
Normal file
@ -0,0 +1,119 @@
|
||||
/*
|
||||
* aks-cdu.dts - Device Tree file for AK signal CDU
|
||||
*
|
||||
* Copyright (C) 2012 AK signal Brno a.s.
|
||||
* 2012 Jiri Prchal <jiri.prchal@aksignal.cz>
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "ge863-pro3.dtsi"
|
||||
|
||||
/ {
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 ubi.mtd=4 root=ubi0:rootfs rootfstype=ubifs";
|
||||
};
|
||||
|
||||
clocks {
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
usart0: serial@fffb0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart1: serial@fffb4000 {
|
||||
status = "okay";
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-delay = <0 0>;
|
||||
};
|
||||
|
||||
usart2: serial@fffb8000 {
|
||||
status = "okay";
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-delay = <0 0>;
|
||||
};
|
||||
|
||||
usart3: serial@fffd0000 {
|
||||
status = "okay";
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
rs485-rts-delay = <0 0>;
|
||||
};
|
||||
|
||||
macb0: ethernet@fffc4000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: gadget@fffa4000 {
|
||||
atmel,vbus-gpio = <&pioC 15 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "soft";
|
||||
nand-on-flash-bbt;
|
||||
status = "okay";
|
||||
|
||||
bootstrap@0 {
|
||||
label = "bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
uboot@40000 {
|
||||
label = "uboot";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
ubootenv@c0000 {
|
||||
label = "ubootenv";
|
||||
reg = <0xc0000 0x40000>;
|
||||
};
|
||||
kernel@100000 {
|
||||
label = "kernel";
|
||||
reg = <0x100000 0x400000>;
|
||||
};
|
||||
rootfs@500000 {
|
||||
label = "rootfs";
|
||||
reg = <0x500000 0x7b00000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
red {
|
||||
gpios = <&pioC 10 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
green {
|
||||
gpios = <&pioA 5 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
yellow {
|
||||
gpios = <&pioB 20 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
|
||||
blue {
|
||||
gpios = <&pioB 21 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "none";
|
||||
};
|
||||
};
|
||||
};
|
||||
13
sys/gnu/dts/arm/alphascale-asm9260-devkit.dts
Normal file
13
sys/gnu/dts/arm/alphascale-asm9260-devkit.dts
Normal file
@ -0,0 +1,13 @@
|
||||
/*
|
||||
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
|
||||
*
|
||||
* Licensed under the X11 license or the GPL v2 (or later)
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "alphascale-asm9260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Alphascale asm9260 Development Kit";
|
||||
compatible = "alphascale,asm9260devkit", "alphascale,asm9260";
|
||||
};
|
||||
63
sys/gnu/dts/arm/alphascale-asm9260.dtsi
Normal file
63
sys/gnu/dts/arm/alphascale-asm9260.dtsi
Normal file
@ -0,0 +1,63 @@
|
||||
/*
|
||||
* Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
|
||||
*
|
||||
* Licensed under the X11 license or the GPL v2 (or later)
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/clock/alphascale,asm9260.h>
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&icoll>;
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x20000000 0x2000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu {
|
||||
compatible = "arm,arm926ej-s";
|
||||
device_type = "cpu";
|
||||
clocks = <&acc CLKID_SYS_CPU>;
|
||||
};
|
||||
};
|
||||
|
||||
osc24m: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <24000000>;
|
||||
clock-accuracy = <30000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
acc: clock-controller@80040000 {
|
||||
compatible = "alphascale,asm9260-clock-controller";
|
||||
#clock-cells = <1>;
|
||||
clocks = <&osc24m>;
|
||||
reg = <0x80040000 0x204>;
|
||||
};
|
||||
|
||||
icoll: interrupt-controller@80054000 {
|
||||
compatible = "alphascale,asm9260-icoll";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x80054000 0x200>;
|
||||
};
|
||||
|
||||
timer0: timer@80088000 {
|
||||
compatible = "alphascale,asm9260-timer";
|
||||
reg = <0x80088000 0x4000>;
|
||||
clocks = <&acc CLKID_AHB_TIMER0>;
|
||||
interrupts = <29>;
|
||||
};
|
||||
};
|
||||
};
|
||||
95
sys/gnu/dts/arm/am335x-base0033.dts
Normal file
95
sys/gnu/dts/arm/am335x-base0033.dts
Normal file
@ -0,0 +1,95 @@
|
||||
/*
|
||||
* am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
|
||||
*
|
||||
* Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include "am335x-igep0033.dtsi"
|
||||
|
||||
/ {
|
||||
model = "IGEP COM AM335x on AQUILA Expansion";
|
||||
compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
|
||||
|
||||
hdmi {
|
||||
compatible = "ti,tilcdc,slave";
|
||||
i2c = <&i2c0>;
|
||||
pinctrl-names = "default", "off";
|
||||
pinctrl-0 = <&nxp_hdmi_pins>;
|
||||
pinctrl-1 = <&nxp_hdmi_off_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds_base {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_base_pins>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@0 {
|
||||
label = "base:red:user";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; /* gpio1_21 */
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "base:green:user";
|
||||
gpios = <&gpio2 0 GPIO_ACTIVE_HIGH>; /* gpio2_0 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
nxp_hdmi_pins: pinmux_nxp_hdmi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
|
||||
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0 */
|
||||
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1 */
|
||||
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2 */
|
||||
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3 */
|
||||
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4 */
|
||||
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5 */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6 */
|
||||
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7 */
|
||||
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8 */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9 */
|
||||
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10 */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11 */
|
||||
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12 */
|
||||
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13 */
|
||||
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14 */
|
||||
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15 */
|
||||
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync */
|
||||
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync */
|
||||
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk */
|
||||
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en */
|
||||
>;
|
||||
};
|
||||
nxp_hdmi_off_pins: pinmux_nxp_hdmi_off_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_OUTPUT | MUX_MODE3) /* xdma_event_intr0.clkout1 */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_base_pins: pinmux_leds_base_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x88 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_csn3.gpio2_0 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "at,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
302
sys/gnu/dts/arm/am335x-bone-common.dtsi
Normal file
302
sys/gnu/dts/arm/am335x-bone-common.dtsi
Normal file
@ -0,0 +1,302 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&dcdc2_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@2 {
|
||||
label = "beaglebone:green:heartbeat";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "beaglebone:green:mmc0";
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "beaglebone:green:usr2";
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@5 {
|
||||
label = "beaglebone:green:usr3";
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc1";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&clkout2_pin>;
|
||||
|
||||
user_leds_s0: user_leds_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
|
||||
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
|
||||
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
|
||||
0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
|
||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins: pinmux_emmc_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
|
||||
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
|
||||
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
|
||||
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
|
||||
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
|
||||
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
regulator-name = "vdds_dpr";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
regulator-name = "vio,vrtc,vdds";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
regulator-name = "vdd_3v3aux";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
regulator-name = "vdd_1v8";
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
regulator-name = "vdd_3v3a";
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "mii";
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
bus-width = <0x4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
cd-inverted;
|
||||
};
|
||||
34
sys/gnu/dts/arm/am335x-bone.dts
Normal file
34
sys/gnu/dts/arm/am335x-bone.dts
Normal file
@ -0,0 +1,34 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include "am335x-bone-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x BeagleBone";
|
||||
compatible = "ti,am335x-bone", "ti,am33xx";
|
||||
};
|
||||
|
||||
&ldo3_reg {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&ldo3_reg>;
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
86
sys/gnu/dts/arm/am335x-boneblack.dts
Normal file
86
sys/gnu/dts/arm/am335x-boneblack.dts
Normal file
@ -0,0 +1,86 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include "am335x-bone-common.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x BeagleBone Black";
|
||||
compatible = "ti,am335x-bone-black", "ti,am335x-bone", "ti,am33xx";
|
||||
};
|
||||
|
||||
&ldo3_reg {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
|
||||
0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
|
||||
0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
|
||||
0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
|
||||
0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
|
||||
0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
|
||||
>;
|
||||
};
|
||||
nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/ {
|
||||
hdmi {
|
||||
compatible = "ti,tilcdc,slave";
|
||||
i2c = <&i2c0>;
|
||||
pinctrl-names = "default", "off";
|
||||
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
|
||||
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
system-power-controller;
|
||||
};
|
||||
680
sys/gnu/dts/arm/am335x-evm.dts
Normal file
680
sys/gnu/dts/arm/am335x-evm.dts
Normal file
@ -0,0 +1,680 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM335x EVM";
|
||||
compatible = "ti,am335x-evm", "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vdd1_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
lis3_reg: fixedregulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lis3_reg";
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */
|
||||
&gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */
|
||||
&gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */
|
||||
|
||||
col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */
|
||||
&gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */
|
||||
|
||||
linux,keymap = <0x0000008b /* MENU */
|
||||
0x0100009e /* BACK */
|
||||
0x02000069 /* LEFT */
|
||||
0x0001006a /* RIGHT */
|
||||
0x0101001c /* ENTER */
|
||||
0x0201006c>; /* DOWN */
|
||||
};
|
||||
|
||||
gpio_keys: volume_keys@0 {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
autorepeat;
|
||||
|
||||
switch@9 {
|
||||
label = "volume-up";
|
||||
linux,code = <115>;
|
||||
gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
switch@10 {
|
||||
label = "volume-down";
|
||||
linux,code = <114>;
|
||||
gpios = <&gpio0 3 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 0>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "ti,tilcdc,panel";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins_s0>;
|
||||
panel-info {
|
||||
ac-bias = <255>;
|
||||
ac-bias-intrpt = <0>;
|
||||
dma-burst-sz = <16>;
|
||||
bpp = <32>;
|
||||
fdd = <0x80>;
|
||||
sync-edge = <0>;
|
||||
sync-ctrl = <1>;
|
||||
raster-order = <0>;
|
||||
fifo-th = <0>;
|
||||
};
|
||||
|
||||
display-timings {
|
||||
800x480p62 {
|
||||
clock-frequency = <30000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <39>;
|
||||
hback-porch = <39>;
|
||||
hsync-len = <47>;
|
||||
vback-porch = <29>;
|
||||
vfront-porch = <13>;
|
||||
vsync-len = <2>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,da830-evm-audio";
|
||||
ti,model = "AM335x-EVM";
|
||||
ti,audio-codec = <&tlv320aic3106>;
|
||||
ti,mcasp-controller = <&mcasp1>;
|
||||
ti,codec-clock-rate = <12000000>;
|
||||
ti,audio-routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"LINE1L", "Line In",
|
||||
"LINE1R", "Line In";
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
|
||||
|
||||
matrix_keypad_s0: matrix_keypad_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
|
||||
>;
|
||||
};
|
||||
|
||||
volume_keys_s0: volume_keys_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
|
||||
0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: pinmux_i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins_s0: nandflash_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins_s0: lcd_pins_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
|
||||
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
|
||||
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
|
||||
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
|
||||
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
|
||||
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
|
||||
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
|
||||
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
|
||||
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
|
||||
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
|
||||
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
|
||||
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
|
||||
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
|
||||
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
|
||||
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
|
||||
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
|
||||
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
|
||||
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
|
||||
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
|
||||
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
|
||||
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
|
||||
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
|
||||
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
|
||||
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
|
||||
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
|
||||
>;
|
||||
};
|
||||
|
||||
am335x_evm_audio_pins: am335x_evm_audio_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
||||
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_pins_default: dcan1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */
|
||||
0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
lis331dlh: lis331dlh@18 {
|
||||
compatible = "st,lis331dlh", "st,lis3lv02d";
|
||||
reg = <0x18>;
|
||||
Vdd-supply = <&lis3_reg>;
|
||||
Vdd_IO-supply = <&lis3_reg>;
|
||||
|
||||
st,click-single-x;
|
||||
st,click-single-y;
|
||||
st,click-single-z;
|
||||
st,click-thresh-x = <10>;
|
||||
st,click-thresh-y = <10>;
|
||||
st,click-thresh-z = <10>;
|
||||
st,irq1-click;
|
||||
st,irq2-click;
|
||||
st,wakeup-x-lo;
|
||||
st,wakeup-x-hi;
|
||||
st,wakeup-y-lo;
|
||||
st,wakeup-y-hi;
|
||||
st,wakeup-z-lo;
|
||||
st,wakeup-z-hi;
|
||||
st,min-limit-x = <120>;
|
||||
st,min-limit-y = <120>;
|
||||
st,min-limit-z = <140>;
|
||||
st,max-limit-x = <550>;
|
||||
st,max-limit-y = <550>;
|
||||
st,max-limit-z = <750>;
|
||||
};
|
||||
|
||||
tsl2550: tsl2550@39 {
|
||||
compatible = "taos,tsl2550";
|
||||
reg = <0x39>;
|
||||
};
|
||||
|
||||
tmp275: tmp275@48 {
|
||||
compatible = "ti,tmp275";
|
||||
reg = <0x48>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@1b {
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&vaux2_reg>;
|
||||
IOVDD-supply = <&vaux2_reg>;
|
||||
DRVDD-supply = <&vaux2_reg>;
|
||||
DVDD-supply = <&vbat>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins_s0>;
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x000020000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x00020000 0x00020000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x00040000 0x00020000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x00060000 0x00020000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot-spl-os";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x000C0000 0x00100000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x001C0000 0x00020000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.u-boot-env.backup1";
|
||||
reg = <0x001E0000 0x00020000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x00200000 0x00800000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00A00000 0x0F600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&mcasp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&am335x_evm_audio_pins>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
/* 4 serializers */
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
0 0 1 2
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii-txid";
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
tsc {
|
||||
ti,wires = <4>;
|
||||
ti,x-plate-resistance = <200>;
|
||||
ti,coordinate-readouts = <5>;
|
||||
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
||||
ti,charge-delay = <0x400>;
|
||||
};
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcan1 {
|
||||
status = "disabled"; /* Enable only if Profile 1 is selected */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan1_pins_default>;
|
||||
};
|
||||
680
sys/gnu/dts/arm/am335x-evmsk.dts
Normal file
680
sys/gnu/dts/arm/am335x-evmsk.dts
Normal file
@ -0,0 +1,680 @@
|
||||
/*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/*
|
||||
* AM335x Starter Kit
|
||||
* http://www.ti.com/tool/tmdssk3358
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM335x EVM-SK";
|
||||
compatible = "ti,am335x-evmsk", "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vdd1_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
lis3_reg: fixedregulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "lis3_reg";
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
wl12xx_vmmc: fixedregulator@2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wl12xx_gpio>;
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vwl1271";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
gpio = <&gpio1 29 0>;
|
||||
startup-delay-us = <70000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator@3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
gpio = <&gpio0 7 GPIO_ACTIVE_HIGH>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_s0>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@1 {
|
||||
label = "evmsk:green:usr0";
|
||||
gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "evmsk:green:usr1";
|
||||
gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "evmsk:green:mmc0";
|
||||
gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@4 {
|
||||
label = "evmsk:green:heartbeat";
|
||||
gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_buttons: gpio_buttons@0 {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@1 {
|
||||
label = "button0";
|
||||
linux,code = <0x100>;
|
||||
gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
switch@2 {
|
||||
label = "button1";
|
||||
linux,code = <0x101>;
|
||||
gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
switch@3 {
|
||||
label = "button2";
|
||||
linux,code = <0x102>;
|
||||
gpios = <&gpio0 30 GPIO_ACTIVE_HIGH>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
switch@4 {
|
||||
label = "button3";
|
||||
linux,code = <0x103>;
|
||||
gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 58 61 66 75 90 125 170 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,da830-evm-audio";
|
||||
ti,model = "AM335x-EVMSK";
|
||||
ti,audio-codec = <&tlv320aic3106>;
|
||||
ti,mcasp-controller = <&mcasp1>;
|
||||
ti,codec-clock-rate = <24000000>;
|
||||
ti,audio-routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT";
|
||||
};
|
||||
|
||||
panel {
|
||||
compatible = "ti,tilcdc,panel";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&lcd_pins_default>;
|
||||
pinctrl-1 = <&lcd_pins_sleep>;
|
||||
status = "okay";
|
||||
panel-info {
|
||||
ac-bias = <255>;
|
||||
ac-bias-intrpt = <0>;
|
||||
dma-burst-sz = <16>;
|
||||
bpp = <32>;
|
||||
fdd = <0x80>;
|
||||
sync-edge = <0>;
|
||||
sync-ctrl = <1>;
|
||||
raster-order = <0>;
|
||||
fifo-th = <0>;
|
||||
};
|
||||
display-timings {
|
||||
480x272 {
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hback-porch = <43>;
|
||||
hfront-porch = <8>;
|
||||
hsync-len = <4>;
|
||||
vback-porch = <12>;
|
||||
vfront-porch = <4>;
|
||||
vsync-len = <10>;
|
||||
clock-frequency = <9000000>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
|
||||
|
||||
lcd_pins_default: lcd_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */
|
||||
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */
|
||||
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */
|
||||
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */
|
||||
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */
|
||||
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */
|
||||
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */
|
||||
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */
|
||||
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
|
||||
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
|
||||
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
|
||||
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
|
||||
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
|
||||
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
|
||||
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
|
||||
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
|
||||
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
|
||||
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
|
||||
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
|
||||
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
|
||||
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
|
||||
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
|
||||
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
|
||||
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
|
||||
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins_sleep: lcd_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x20 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */
|
||||
0x24 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */
|
||||
0x28 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */
|
||||
0x2c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */
|
||||
0x30 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */
|
||||
0x34 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */
|
||||
0x38 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */
|
||||
0x3c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */
|
||||
0xa0 (PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */
|
||||
0xa4 (PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */
|
||||
0xa8 (PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */
|
||||
0xac (PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */
|
||||
0xb0 (PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */
|
||||
0xb4 (PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */
|
||||
0xb8 (PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */
|
||||
0xbc (PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */
|
||||
0xc0 (PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */
|
||||
0xc4 (PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */
|
||||
0xc8 (PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */
|
||||
0xcc (PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */
|
||||
0xd0 (PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */
|
||||
0xd4 (PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */
|
||||
0xd8 (PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */
|
||||
0xdc (PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */
|
||||
0xe0 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */
|
||||
0xe4 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */
|
||||
0xe8 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */
|
||||
0xec (PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */
|
||||
>;
|
||||
};
|
||||
|
||||
|
||||
user_leds_s0: user_leds_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
|
||||
0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
|
||||
0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
|
||||
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpio_keys_s0: gpio_keys_s0 {
|
||||
pinctrl-single,pins = <
|
||||
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
|
||||
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
|
||||
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
|
||||
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
clkout2_pin: pinmux_clkout2_pin {
|
||||
pinctrl-single,pins = <
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap2_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
|
||||
0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
|
||||
0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
|
||||
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
|
||||
0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
|
||||
/* Slave 2 reset value*/
|
||||
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp1_pins: mcasp1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
||||
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins: pinmux_mmc2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
|
||||
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
|
||||
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
|
||||
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
|
||||
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
|
||||
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
|
||||
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
wl12xx_gpio: pinmux_wl12xx_gpio {
|
||||
pinctrl-single,pins = <
|
||||
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_csn0.gpio1_29 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
|
||||
lis331dlh: lis331dlh@18 {
|
||||
compatible = "st,lis331dlh", "st,lis3lv02d";
|
||||
reg = <0x18>;
|
||||
Vdd-supply = <&lis3_reg>;
|
||||
Vdd_IO-supply = <&lis3_reg>;
|
||||
|
||||
st,click-single-x;
|
||||
st,click-single-y;
|
||||
st,click-single-z;
|
||||
st,click-thresh-x = <10>;
|
||||
st,click-thresh-y = <10>;
|
||||
st,click-thresh-z = <10>;
|
||||
st,irq1-click;
|
||||
st,irq2-click;
|
||||
st,wakeup-x-lo;
|
||||
st,wakeup-x-hi;
|
||||
st,wakeup-y-lo;
|
||||
st,wakeup-y-hi;
|
||||
st,wakeup-z-lo;
|
||||
st,wakeup-z-hi;
|
||||
st,min-limit-x = <120>;
|
||||
st,min-limit-y = <120>;
|
||||
st,min-limit-z = <140>;
|
||||
st,max-limit-x = <550>;
|
||||
st,max-limit-y = <550>;
|
||||
st,max-limit-z = <750>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@1b {
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&vaux2_reg>;
|
||||
IOVDD-supply = <&vaux2_reg>;
|
||||
DRVDD-supply = <&vaux2_reg>;
|
||||
DVDD-supply = <&vbat>;
|
||||
};
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&epwmss2 {
|
||||
status = "okay";
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap2_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii-txid";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii-txid";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmc_reg>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&wl12xx_vmmc>;
|
||||
ti,non-removable;
|
||||
bus-width = <4>;
|
||||
cap-power-off-card;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins>;
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcasp1_pins>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>; /* MCASP_IIS_MODE */
|
||||
tdm-slots = <2>;
|
||||
/* 4 serializers */
|
||||
serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */
|
||||
0 0 1 2
|
||||
>;
|
||||
tx-num-evt = <32>;
|
||||
rx-num-evt = <32>;
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
tsc {
|
||||
ti,wires = <4>;
|
||||
ti,x-plate-resistance = <200>;
|
||||
ti,coordinate-readouts = <5>;
|
||||
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
320
sys/gnu/dts/arm/am335x-igep0033.dtsi
Normal file
320
sys/gnu/dts/arm/am335x-igep0033.dtsi
Normal file
@ -0,0 +1,320 @@
|
||||
/*
|
||||
* am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
|
||||
*
|
||||
* Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vdd1_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins>;
|
||||
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@0 {
|
||||
label = "com:green:user";
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
vmmc: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
nandflash_pins: pinmux_nandflash_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins: pinmux_leds_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext;
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nandflash_pins>;
|
||||
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
nand-bus-width = <8>;
|
||||
ti,nand-ecc-opt = "bch8";
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <44>;
|
||||
gpmc,cs-wr-off-ns = <44>;
|
||||
gpmc,adv-on-ns = <6>;
|
||||
gpmc,adv-rd-off-ns = <34>;
|
||||
gpmc,adv-wr-off-ns = <44>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <40>;
|
||||
gpmc,oe-on-ns = <0>;
|
||||
gpmc,oe-off-ns = <54>;
|
||||
gpmc,access-ns = <64>;
|
||||
gpmc,rd-cycle-ns = <82>;
|
||||
gpmc,wr-cycle-ns = <82>;
|
||||
gpmc,wait-on-read = "true";
|
||||
gpmc,wait-on-write = "true";
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
elm_id = <&elm>;
|
||||
|
||||
/* MTD partition table */
|
||||
partition@0 {
|
||||
label = "SPL";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "U-boot";
|
||||
reg = <0x00080000 0x001e0000>;
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "U-Boot Env";
|
||||
reg = <0x00260000 0x00020000>;
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "Kernel";
|
||||
reg = <0x00280000 0x00500000>;
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "File System";
|
||||
reg = <0x00780000 0x007880000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmc>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1312500>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912500>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd3_reg: regulator@4 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig1_reg: regulator@5 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
362
sys/gnu/dts/arm/am335x-lxm.dts
Normal file
362
sys/gnu/dts/arm/am335x-lxm.dts
Normal file
@ -0,0 +1,362 @@
|
||||
/*
|
||||
* Copyright (C) 2014 NovaTech LLC - http://www.novatechweb.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NovaTech OrionLXm";
|
||||
compatible = "novatech,am335x-lxm", "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&vdd1_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
/* Power supply provides a fixed 5V @2A */
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* Power supply provides a fixed 3.3V @3A */
|
||||
vmmcsd_fixed: fixedregulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3 */
|
||||
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2 */
|
||||
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1 */
|
||||
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0 */
|
||||
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk */
|
||||
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_crs_dv */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rxer */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_txen */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* rmii1_td0 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii1_rd0 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk */
|
||||
|
||||
/* Slave 2 */
|
||||
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_txen */
|
||||
0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td1 */
|
||||
0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* rmii2_td0 */
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd1 */
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rd0 */
|
||||
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_crs_dv */
|
||||
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* rmii2_rxer */
|
||||
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
|
||||
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* rmii2_refclk */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_int */
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_crs_dv */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rxer */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_txen */
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td1 */
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_td0 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_rd0 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii1_refclk */
|
||||
|
||||
/* Slave 2 reset value*/
|
||||
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_txen */
|
||||
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td1 */
|
||||
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_td0 */
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd1 */
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rd0 */
|
||||
0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_crs_dv */
|
||||
0x74 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_rxer */
|
||||
0x78 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_int */
|
||||
0x108 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* rmii2_refclk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins: pinmux_emmc_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
|
||||
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
|
||||
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
|
||||
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
|
||||
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
|
||||
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: pinmux_uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
serial_config1: serial_config1@20 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
serial_config2: serial_config2@21 {
|
||||
compatible = "nxp,pca9539";
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
tps: tps@2d {
|
||||
compatible = "ti,tps65910";
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "tps65910.dtsi"
|
||||
|
||||
&tps {
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
/* vrtc - unused */
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-name = "vio_1v5,ddr";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
regulator-name = "vdd1,mpu";
|
||||
regulator-min-microvolt = <600000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
regulator-name = "vdd2_1v1,core";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vdd3 - unused */
|
||||
|
||||
/* vdig1 - unused */
|
||||
|
||||
vdig2_reg: regulator@6 {
|
||||
regulator-name = "vdig2_1v8,vdds_pll";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* vpll - unused */
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
regulator-name = "vdac_1v8,vdds";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
regulator-name = "vaux1_1v8,usb";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
regulator-name = "vaux2_3v3,io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux33_reg: regulator@11 {
|
||||
regulator-name = "vaux33_3v3,usb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
regulator-name = "vmmc_3v3,io";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&sham {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&aes {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <5>;
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <4>;
|
||||
phy-mode = "rmii";
|
||||
dual_emac_res_vlan = <3>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
436
sys/gnu/dts/arm/am335x-nano.dts
Normal file
436
sys/gnu/dts/arm/am335x-nano.dts
Normal file
@ -0,0 +1,436 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Newflow Ltd - http://www.newflow.co.uk/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Newflow AM335x NanoBone";
|
||||
compatible = "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&dcdc2_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led@0 {
|
||||
label = "nanobone:green:usr1";
|
||||
gpios = <&gpio1 5 0>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&misc_pins>;
|
||||
|
||||
misc_pins: misc_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_OUTPUT | MUX_MODE7) /* spi0_cs0.gpio0_5 */
|
||||
>;
|
||||
};
|
||||
|
||||
gpmc_pins: gpmc_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x20 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad8.gpmc_ad8 */
|
||||
0x24 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad9.gpmc_ad9 */
|
||||
0x28 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad10.gpmc_ad10 */
|
||||
0x2c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad11.gpmc_ad11 */
|
||||
0x30 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad12.gpmc_ad12 */
|
||||
0x34 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad13.gpmc_ad13 */
|
||||
0x38 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad14.gpmc_ad14 */
|
||||
0x3c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad15.gpmc_ad15 */
|
||||
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x80 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn1.gpmc_csn1 */
|
||||
0x84 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn2.gpmc_csn2 */
|
||||
0x88 (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn3.gpmc_csn3 */
|
||||
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_ben0_cle.gpmc_ben0_cle */
|
||||
|
||||
0xa4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data1.gpmc_a1 */
|
||||
0xa8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data2.gpmc_a2 */
|
||||
0xac (PIN_OUTPUT | MUX_MODE1) /* lcd_data3.gpmc_a3 */
|
||||
0xb0 (PIN_OUTPUT | MUX_MODE1) /* lcd_data4.gpmc_a4 */
|
||||
0xb4 (PIN_OUTPUT | MUX_MODE1) /* lcd_data5.gpmc_a5 */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE1) /* lcd_data6.gpmc_a6 */
|
||||
0xbc (PIN_OUTPUT | MUX_MODE1) /* lcd_data7.gpmc_a7 */
|
||||
|
||||
0xe0 (PIN_OUTPUT | MUX_MODE1) /* lcd_vsync.gpmc_a8 */
|
||||
0xe4 (PIN_OUTPUT | MUX_MODE1) /* lcd_hsync.gpmc_a9 */
|
||||
0xe8 (PIN_OUTPUT | MUX_MODE1) /* lcd_pclk.gpmc_a10 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart0_pins: uart0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
uart1_pins: uart1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x178 (PIN_OUTPUT | MUX_MODE7) /* uart1_ctsn.uart1_ctsn */
|
||||
0x17c (PIN_OUTPUT | MUX_MODE7) /* uart1_rtsn.uart1_rtsn */
|
||||
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
|
||||
0x184 (PIN_OUTPUT | MUX_MODE0) /* uart1_txd.uart1_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
uart2_pins: uart2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xc0 (PIN_INPUT_PULLUP | MUX_MODE7) /* lcd_data8.gpio2[14] */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE7) /* lcd_data9.gpio2[15] */
|
||||
0x150 (PIN_INPUT | MUX_MODE1) /* spi0_sclk.uart2_rxd */
|
||||
0x154 (PIN_OUTPUT | MUX_MODE1) /* spi0_d0.uart2_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins: uart3_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xc8 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data10.uart3_ctsn */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE6) /* lcd_data11.uart3_rtsn */
|
||||
0x160 (PIN_INPUT | MUX_MODE1) /* spi0_cs1.uart3_rxd */
|
||||
0x164 (PIN_OUTPUT | MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
uart4_pins: uart4_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xd0 (PIN_INPUT_PULLUP | MUX_MODE6) /* lcd_data12.uart4_ctsn */
|
||||
0xd4 (PIN_OUTPUT | MUX_MODE6) /* lcd_data13.uart4_rtsn */
|
||||
0x168 (PIN_INPUT | MUX_MODE1) /* uart0_ctsn.uart4_rxd */
|
||||
0x16c (PIN_OUTPUT | MUX_MODE1) /* uart0_rtsn.uart4_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
uart5_pins: uart5_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xd8 (PIN_INPUT | MUX_MODE4) /* lcd_data14.uart5_rxd */
|
||||
0x144 (PIN_OUTPUT | MUX_MODE3) /* rmiii1_refclk.uart5_txd */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
0x1e8 (PIN_INPUT_PULLUP | MUX_MODE7) /* emu1.gpio3[8] */
|
||||
0x1a0 (PIN_INPUT_PULLUP | MUX_MODE7) /* mcasp0_aclkr.gpio3[18] */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
rts-gpio = <&gpio0 13 GPIO_ACTIVE_HIGH>;
|
||||
rs485-rts-active-high;
|
||||
rs485-rx-during-tx;
|
||||
rs485-rts-delay = <1 1>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
status = "okay";
|
||||
rts-gpio = <&gpio2 15 GPIO_ACTIVE_HIGH>;
|
||||
rs485-rts-active-high;
|
||||
rs485-rts-delay = <1 1>;
|
||||
linux,rs485-enabled-at-boot-time;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart4 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart4_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart5 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart5_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
gpio@20 {
|
||||
compatible = "mcp,mcp23017";
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
eeprom@53 {
|
||||
compatible = "mcp,24c02";
|
||||
reg = <0x53>;
|
||||
pagesize = <8>;
|
||||
};
|
||||
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds1307";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
status = "okay";
|
||||
gpmc,num-waitpins = <2>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpmc_pins>;
|
||||
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0 0x08000000 0x08000000>; /* CS0: NOR 128M */
|
||||
|
||||
nor@0,0 {
|
||||
reg = <0 0x00000000 0x08000000>;
|
||||
compatible = "cfi-flash";
|
||||
linux,mtd-name = "spansion,s29gl010p11t";
|
||||
bank-width = <2>;
|
||||
|
||||
gpmc,mux-add-data = <2>;
|
||||
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <160>;
|
||||
gpmc,cs-wr-off-ns = <160>;
|
||||
gpmc,adv-on-ns = <10>;
|
||||
gpmc,adv-rd-off-ns = <30>;
|
||||
gpmc,adv-wr-off-ns = <30>;
|
||||
gpmc,oe-on-ns = <40>;
|
||||
gpmc,oe-off-ns = <160>;
|
||||
gpmc,we-on-ns = <40>;
|
||||
gpmc,we-off-ns = <160>;
|
||||
gpmc,rd-cycle-ns = <160>;
|
||||
gpmc,wr-cycle-ns = <160>;
|
||||
gpmc,access-ns = <150>;
|
||||
gpmc,page-burst-access-ns = <10>;
|
||||
gpmc,cycle2cycle-samecsen;
|
||||
gpmc,cycle2cycle-delay-ns = <20>;
|
||||
gpmc,wr-data-mux-bus-ns = <70>;
|
||||
gpmc,wr-access-ns = <80>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
MTD partition table
|
||||
===================
|
||||
+------------+-->0x00000000-> U-Boot start
|
||||
| |
|
||||
| |-->0x000BFFFF-> U-Boot end
|
||||
| |-->0x000C0000-> ENV1 start
|
||||
| |
|
||||
| |-->0x000DFFFF-> ENV1 end
|
||||
| |-->0x000E0000-> ENV2 start
|
||||
| |
|
||||
| |-->0x000FFFFF-> ENV2 end
|
||||
| |-->0x00100000-> Kernel start
|
||||
| |
|
||||
| |-->0x004FFFFF-> Kernel end
|
||||
| |-->0x00500000-> File system start
|
||||
| |
|
||||
| |-->0x014FFFFF-> File system end
|
||||
| |-->0x01500000-> User data start
|
||||
| |
|
||||
| |-->0x03FFFFFF-> User data end
|
||||
| |-->0x04000000-> Data storage start
|
||||
| |
|
||||
+------------+-->0x08000000-> NOR end (Free end)
|
||||
*/
|
||||
partition@0 {
|
||||
label = "boot";
|
||||
reg = <0x00000000 0x000c0000>; /* 768KB */
|
||||
};
|
||||
|
||||
partition@1 {
|
||||
label = "env1";
|
||||
reg = <0x000c0000 0x00020000>; /* 128KB */
|
||||
};
|
||||
|
||||
partition@2 {
|
||||
label = "env2";
|
||||
reg = <0x000e0000 0x00020000>; /* 128KB */
|
||||
};
|
||||
|
||||
partition@3 {
|
||||
label = "kernel";
|
||||
reg = <0x00100000 0x00400000>; /* 4MB */
|
||||
};
|
||||
|
||||
partition@4 {
|
||||
label = "rootfs";
|
||||
reg = <0x00500000 0x01000000>; /* 16MB */
|
||||
};
|
||||
|
||||
partition@5 {
|
||||
label = "user";
|
||||
reg = <0x01500000 0x02b00000>; /* 43MB */
|
||||
};
|
||||
|
||||
partition@6 {
|
||||
label = "data";
|
||||
reg = <0x04000000 0x04000000>; /* 64MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
dual_emac = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&ldo4_reg>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio3 8 0>;
|
||||
wp-gpios = <&gpio3 18 0>;
|
||||
};
|
||||
|
||||
#include "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
/* +1.5V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1450000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.1V with ±4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <915000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.1V with ±4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <915000>;
|
||||
regulator-max-microvolt = <1140000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
/* +1.8V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1870000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
/* +3.3V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <3175000>;
|
||||
regulator-max-microvolt = <3430000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
/* +1.8V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <1750000>;
|
||||
regulator-max-microvolt = <1870000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
/* +3.3V voltage with ±4% tolerance */
|
||||
regulator-min-microvolt = <3175000>;
|
||||
regulator-max-microvolt = <3430000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
653
sys/gnu/dts/arm/am335x-pepper.dts
Normal file
653
sys/gnu/dts/arm/am335x-pepper.dts
Normal file
@ -0,0 +1,653 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Gumstix, Inc. - https://www.gumstix.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "am33xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Gumstix Pepper";
|
||||
compatible = "gumstix,am335x-pepper", "ti,am33xx";
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
cpu0-supply = <&dcdc3_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
buttons: user_buttons {
|
||||
compatible = "gpio-keys";
|
||||
};
|
||||
|
||||
leds: user_leds {
|
||||
compatible = "gpio-leds";
|
||||
};
|
||||
|
||||
panel: lcd_panel {
|
||||
compatible = "ti,tilcdc,panel";
|
||||
};
|
||||
|
||||
sound: sound_iface {
|
||||
compatible = "ti,da830-evm-audio";
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
};
|
||||
|
||||
v3v3c_reg: fixedregulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
};
|
||||
|
||||
vdd5_reg: fixedregulator@2 {
|
||||
compatible = "regulator-fixed";
|
||||
};
|
||||
};
|
||||
|
||||
/* I2C Busses */
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps@24 {
|
||||
reg = <0x24>;
|
||||
};
|
||||
|
||||
eeprom: eeprom@50 {
|
||||
compatible = "at,24c256";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
audio_codec: tlv320aic3106@1b {
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
};
|
||||
|
||||
accel: lis331dlh@1d {
|
||||
compatible = "st,lis3lv02d";
|
||||
reg = <0x1d>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
i2c0_pins: pinmux_i2c0 {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
i2c1_pins: pinmux_i2c1 {
|
||||
pinctrl-single,pins = <
|
||||
0x10C (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_crs,i2c1_sda */
|
||||
0x110 (PIN_INPUT_PULLUP | MUX_MODE3) /* mii1_rxerr,i2c1_scl */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Accelerometer */
|
||||
&accel {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&accel_pins>;
|
||||
|
||||
Vdd-supply = <&ldo3_reg>;
|
||||
Vdd_IO-supply = <&ldo3_reg>;
|
||||
st,irq1-click;
|
||||
st,wakeup-x-lo;
|
||||
st,wakeup-x-hi;
|
||||
st,wakeup-y-lo;
|
||||
st,wakeup-y-hi;
|
||||
st,wakeup-z-lo;
|
||||
st,wakeup-z-hi;
|
||||
st,min-limit-x = <92>;
|
||||
st,max-limit-x = <14>;
|
||||
st,min-limit-y = <14>;
|
||||
st,max-limit-y = <92>;
|
||||
st,min-limit-z = <92>;
|
||||
st,max-limit-z = <14>;
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
accel_pins: pinmux_accel {
|
||||
pinctrl-single,pins = <
|
||||
0x98 (PIN_INPUT | MUX_MODE7) /* gpmc_wen.gpio2_4 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Audio */
|
||||
&audio_codec {
|
||||
status = "okay";
|
||||
|
||||
gpio-reset = <&gpio1 16 GPIO_ACTIVE_LOW>;
|
||||
AVDD-supply = <&ldo3_reg>;
|
||||
IOVDD-supply = <&ldo3_reg>;
|
||||
DRVDD-supply = <&ldo3_reg>;
|
||||
DVDD-supply = <&dcdc1_reg>;
|
||||
};
|
||||
|
||||
&sound {
|
||||
ti,model = "AM335x-EVM";
|
||||
ti,audio-codec = <&audio_codec>;
|
||||
ti,mcasp-controller = <&mcasp0>;
|
||||
ti,codec-clock-rate = <12000000>;
|
||||
ti,audio-routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT",
|
||||
"LINE1L", "Line In";
|
||||
};
|
||||
|
||||
&mcasp0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&audio_pins>;
|
||||
|
||||
op-mode = <0>; /* MCASP_ISS_MODE */
|
||||
tdm-slots = <2>;
|
||||
serial-dir = <
|
||||
1 2 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
0 0 0 0
|
||||
>;
|
||||
tx-num-evt = <1>;
|
||||
rx-num-evt = <1>;
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
audio_pins: pinmux_audio {
|
||||
pinctrl-single,pins = <
|
||||
0x1AC (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_ahcklx.mcasp0_ahclkx */
|
||||
0x194 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_fsx.mcasp0_fsx */
|
||||
0x190 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_aclkx.mcasp0_aclkx */
|
||||
0x198 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr0.mcasp0_axr0 */
|
||||
0x1A8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* mcasp0_axr1.mcasp0_axr1 */
|
||||
0x40 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a0.gpio1_16 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Display: 24-bit LCD Screen */
|
||||
&panel {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins>;
|
||||
panel-info {
|
||||
ac-bias = <255>;
|
||||
ac-bias-intrpt = <0>;
|
||||
dma-burst-sz = <16>;
|
||||
bpp = <32>;
|
||||
fdd = <0x80>;
|
||||
sync-edge = <0>;
|
||||
sync-ctrl = <1>;
|
||||
raster-order = <0>;
|
||||
fifo-th = <0>;
|
||||
};
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: 480x272 {
|
||||
clock-frequency = <18400000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <8>;
|
||||
hback-porch = <4>;
|
||||
hsync-len = <41>;
|
||||
vfront-porch = <4>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <1>;
|
||||
vsync-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
lcd_pins: pinmux_lcd {
|
||||
pinctrl-single,pins = <
|
||||
0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */
|
||||
0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */
|
||||
0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */
|
||||
0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */
|
||||
0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */
|
||||
0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */
|
||||
0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */
|
||||
0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */
|
||||
0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */
|
||||
0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */
|
||||
0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */
|
||||
0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */
|
||||
0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */
|
||||
0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */
|
||||
0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */
|
||||
0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */
|
||||
0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data16 */
|
||||
0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data17 */
|
||||
0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data18 */
|
||||
0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data19 */
|
||||
0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data20 */
|
||||
0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data21 */
|
||||
0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data22 */
|
||||
0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data23 */
|
||||
0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */
|
||||
0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */
|
||||
0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */
|
||||
0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */
|
||||
/* Display Enable */
|
||||
0x6c (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a11.gpio1_27 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Ethernet */
|
||||
&cpsw_emac0 {
|
||||
status = "okay";
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
status = "okay";
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <ðernet_pins>;
|
||||
};
|
||||
|
||||
|
||||
&am33xx_pinmux {
|
||||
ethernet_pins: pinmux_ethernet {
|
||||
pinctrl-single,pins = <
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x118 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x12c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd3.rgmii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd2.rgmii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLUP | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
|
||||
/* ethernet interrupt */
|
||||
0x144 (PIN_INPUT_PULLUP | MUX_MODE7) /* rmii2_refclk.gpio0_29 */
|
||||
/* ethernet PHY nReset */
|
||||
0x108 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* mii1_col.gpio3_0 */
|
||||
>;
|
||||
};
|
||||
|
||||
mdio_pins: pinmux_mdio {
|
||||
pinctrl-single,pins = <
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* MMC */
|
||||
&mmc1 {
|
||||
/* Bootable SD card slot */
|
||||
status = "okay";
|
||||
vmmc-supply = <&ldo3_reg>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sd_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
/* eMMC (not populated) on MMC #2 */
|
||||
status = "disabled";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&emmc_pins>;
|
||||
vmmc-supply = <&ldo3_reg>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
};
|
||||
|
||||
&edma {
|
||||
/* Map eDMA MMC2 Events from Crossbar */
|
||||
ti,edma-xbar-event-map = /bits/ 16 <1 12
|
||||
2 13>;
|
||||
};
|
||||
|
||||
|
||||
&mmc3 {
|
||||
/* Wifi & Bluetooth on MMC #3 */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wireless_pins>;
|
||||
vmmmc-supply = <&v3v3c_reg>;
|
||||
bus-width = <4>;
|
||||
ti,non-removable;
|
||||
dmas = <&edma 12
|
||||
&edma 13>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
|
||||
&am33xx_pinmux {
|
||||
sd_pins: pinmux_sd_card {
|
||||
pinctrl-single,pins = <
|
||||
0xf0 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
0xf4 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
0xf8 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
0xfc (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
0x100 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
0x104 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
emmc_pins: pinmux_emmc {
|
||||
pinctrl-single,pins = <
|
||||
0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
|
||||
0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
|
||||
0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
|
||||
0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
|
||||
0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
|
||||
0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
|
||||
0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
|
||||
0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
|
||||
0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
|
||||
0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
|
||||
/* EMMC nReset */
|
||||
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
|
||||
>;
|
||||
};
|
||||
wireless_pins: pinmux_wireless {
|
||||
pinctrl-single,pins = <
|
||||
0x44 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a1.mmc2_dat0 */
|
||||
0x48 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a2.mmc2_dat1 */
|
||||
0x4c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_a3.mmc2_dat2 */
|
||||
0x78 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_ben1.mmc2_dat3 */
|
||||
0x88 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_csn3.mmc2_cmd */
|
||||
0x8c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_clk.mmc1_clk */
|
||||
/* WLAN nReset */
|
||||
0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
|
||||
/* WLAN nPower down */
|
||||
0x70 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
|
||||
/* 32kHz Clock */
|
||||
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Power */
|
||||
&vbat {
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
};
|
||||
|
||||
&v3v3c_reg {
|
||||
regulator-name = "v3v3c_reg";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vin-supply = <&vbat>;
|
||||
};
|
||||
|
||||
&vdd5_reg {
|
||||
regulator-name = "vdd5_reg";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
vin-supply = <&vbat>;
|
||||
};
|
||||
|
||||
/include/ "tps65217.dtsi"
|
||||
|
||||
&tps {
|
||||
backlight {
|
||||
isel = <1>; /* ISET1 */
|
||||
fdim = <200>; /* TPS65217_BL_FDIM_200HZ */
|
||||
default-brightness = <80>;
|
||||
};
|
||||
|
||||
regulators {
|
||||
dcdc1_reg: regulator@0 {
|
||||
/* VDD_1V8 system supply */
|
||||
};
|
||||
|
||||
dcdc2_reg: regulator@1 {
|
||||
/* VDD_CORE voltage limits 0.95V - 1.26V with +/-4% tolerance */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1325000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
dcdc3_reg: regulator@2 {
|
||||
/* VDD_MPU voltage limits 0.95V - 1.1V with +/-4% tolerance */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <925000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo1_reg: regulator@3 {
|
||||
/* VRTC 1.8V always-on supply */
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo2_reg: regulator@4 {
|
||||
/* 3.3V rail */
|
||||
};
|
||||
|
||||
ldo3_reg: regulator@5 {
|
||||
/* VDD_3V3A 3.3V rail */
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
ldo4_reg: regulator@6 {
|
||||
/* VDD_3V3B 3.3V rail */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* SPI Busses */
|
||||
&spi0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
spi0_pins: pinmux_spi0 {
|
||||
pinctrl-single,pins = <
|
||||
0x150 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_sclk.spi0_sclk */
|
||||
0x15C (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
|
||||
0x154 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d0.spi0_d0 */
|
||||
0x158 (PIN_INPUT_PULLUP | MUX_MODE0) /* spi0_d1.spi0_d1 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Touch Screen */
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
tsc {
|
||||
ti,wires = <4>;
|
||||
ti,x-plate-resistance = <200>;
|
||||
ti,coordinate-readouts = <5>;
|
||||
ti,wire-config = <0x00 0x11 0x22 0x33>;
|
||||
};
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
/* UARTs */
|
||||
&uart0 {
|
||||
/* Serial Console */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
/* Broken out to J6 header */
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
uart0_pins: pinmux_uart0 {
|
||||
pinctrl-single,pins = <
|
||||
0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
|
||||
0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
|
||||
>;
|
||||
};
|
||||
uart1_pins: pinmux_uart1 {
|
||||
pinctrl-single,pins = <
|
||||
0x178 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_ctsn.uart1_ctsn */
|
||||
0x17C (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_rtsn.uart1_rtsn */
|
||||
0x180 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart1_rxd.uart1_rxd */
|
||||
0x184 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart1_txd.uart1_txd */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* USB */
|
||||
&usb {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb_pins>;
|
||||
};
|
||||
|
||||
&usb_ctrl_mod {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb0 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
status = "okay";
|
||||
dr_mode = "host";
|
||||
};
|
||||
|
||||
&cppi41dma {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
usb_pins: pinmux_usb {
|
||||
pinctrl-single,pins = <
|
||||
/* USB0 Over-Current (active low) */
|
||||
0x64 (PIN_INPUT | MUX_MODE7) /* gpmc_a9.gpio1_25 */
|
||||
/* USB1 Over-Current (active low) */
|
||||
0x68 (PIN_INPUT | MUX_MODE7) /* gpmc_a10.gpio1_26 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* User IO */
|
||||
&leds {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_leds_pins>;
|
||||
|
||||
led@0 {
|
||||
label = "pepper:user0:blue";
|
||||
gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "pepper:user1:red";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "none";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
&buttons {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&user_buttons_pins>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
button@0 {
|
||||
label = "home";
|
||||
linux,code = <KEY_HOME>;
|
||||
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
button@1 {
|
||||
label = "menu";
|
||||
linux,code = <KEY_MENU>;
|
||||
gpios = <&gpio1 23 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
|
||||
buttons@2 {
|
||||
label = "power";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
|
||||
&am33xx_pinmux {
|
||||
user_leds_pins: pinmux_user_leds {
|
||||
pinctrl-single,pins = <
|
||||
0x50 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a4.gpio1_20 */
|
||||
0x54 (PIN_OUTPUT | MUX_MODE7) /* gpmc_a5.gpio1_21 */
|
||||
>;
|
||||
};
|
||||
|
||||
user_buttons_pins: pinmux_user_buttons {
|
||||
pinctrl-single,pins = <
|
||||
0x58 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
|
||||
0x5C (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a7.gpio1_21 */
|
||||
0x164 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio0_7 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
646
sys/gnu/dts/arm/am33xx-clocks.dtsi
Normal file
646
sys/gnu/dts/arm/am33xx-clocks.dtsi
Normal file
@ -0,0 +1,646 @@
|
||||
/*
|
||||
* Device Tree Source for AM33xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
adc_tsc_fck: adc_tsc_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan0_fck: dcan0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan1_fck: dcan1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp0_fck: mcasp0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp1_fck: mcasp1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex0_fck: smartreflex0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex1_fck: smartreflex1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sha0_fck: sha0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes0_fck: aes0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
rng_fck: rng_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
};
|
||||
&prcm_clocks {
|
||||
clk_32768_ck: clk_32768_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32000>;
|
||||
};
|
||||
|
||||
virt_19200000_ck: virt_19200000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
virt_24000000_ck: virt_24000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
virt_25000000_ck: virt_25000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
virt_26000000_ck: virt_26000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0490>, <0x045c>, <0x0468>;
|
||||
};
|
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_core_ck>;
|
||||
};
|
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0480>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x0484>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04d8>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0488>, <0x0420>, <0x042c>;
|
||||
};
|
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a8>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0494>, <0x0434>, <0x0440>;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a0>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_ddr_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x0498>, <0x0448>, <0x0454>;
|
||||
};
|
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_disp_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04a4>;
|
||||
ti,index-starts-at-one;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-no-gate-j-type-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x048c>, <0x0470>, <0x049c>;
|
||||
};
|
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,max-div = <31>;
|
||||
reg = <0x04ac>;
|
||||
ti,index-starts-at-one;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
cefuse_fck: cefuse_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0a20>;
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_24mhz>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <732>;
|
||||
};
|
||||
|
||||
clkdiv32k_ick: clkdiv32k_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x014c>;
|
||||
};
|
||||
|
||||
l3_gclk: l3_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&l3_gclk>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x0530>;
|
||||
};
|
||||
|
||||
mmu_fck: mmu_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0914>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>;
|
||||
reg = <0x0528>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0508>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x050c>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0510>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0518>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x051c>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0504>;
|
||||
};
|
||||
|
||||
usbotg_fck: usbotg_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x047c>;
|
||||
};
|
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
ieee5000_fck: ieee5000_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x00e4>;
|
||||
};
|
||||
|
||||
wdt1_fck: wdt1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x0538>;
|
||||
};
|
||||
|
||||
l4_rtc_gclk: l4_rtc_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
l4hs_gclk: l4hs_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l3s_gclk: l3s_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4fw_gclk: l4fw_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4ls_gclk: l4ls_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sysclk_div_ck: sysclk_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>;
|
||||
reg = <0x0520>;
|
||||
};
|
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x053c>;
|
||||
};
|
||||
|
||||
gpio0_dbclk: gpio0_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&gpio0_dbclk_mux_ck>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x0408>;
|
||||
};
|
||||
|
||||
gpio1_dbclk: gpio1_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x00ac>;
|
||||
};
|
||||
|
||||
gpio2_dbclk: gpio2_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x00b0>;
|
||||
};
|
||||
|
||||
gpio3_dbclk: gpio3_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <18>;
|
||||
reg = <0x00b4>;
|
||||
};
|
||||
|
||||
lcd_gclk: lcd_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
||||
reg = <0x0534>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
mmc_clk: mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x052c>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
reg = <0x052c>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
sysclkout_pre_ck: sysclkout_pre_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
|
||||
clkout2_div_ck: clkout2_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sysclkout_pre_ck>;
|
||||
ti,bit-shift = <3>;
|
||||
ti,max-div = <8>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
|
||||
dbg_sysclk_ck: dbg_sysclk_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
ti,bit-shift = <19>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
dbg_clka_ck: dbg_clka_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
ti,bit-shift = <30>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>;
|
||||
ti,bit-shift = <20>;
|
||||
reg = <0x0414>;
|
||||
};
|
||||
|
||||
stm_clk_div_ck: stm_clk_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&stm_pmd_clock_mux_ck>;
|
||||
ti,bit-shift = <27>;
|
||||
ti,max-div = <64>;
|
||||
reg = <0x0414>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
trace_clk_div_ck: trace_clk_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&trace_pmd_clk_mux_ck>;
|
||||
ti,bit-shift = <24>;
|
||||
ti,max-div = <64>;
|
||||
reg = <0x0414>;
|
||||
ti,index-power-of-two;
|
||||
};
|
||||
|
||||
clkout2_ck: clkout2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkout2_div_ck>;
|
||||
ti,bit-shift = <7>;
|
||||
reg = <0x0700>;
|
||||
};
|
||||
};
|
||||
|
||||
&prcm_clockdomains {
|
||||
clk_24mhz_clkdm: clk_24mhz_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
};
|
||||
};
|
||||
869
sys/gnu/dts/arm/am33xx.dtsi
Normal file
869
sys/gnu/dts/arm/am33xx.dtsi
Normal file
@ -0,0 +1,869 @@
|
||||
/*
|
||||
* Device Tree Source for AM33XX SoC
|
||||
*
|
||||
* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pinctrl/am33xx.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am33xx";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
d_can0 = &dcan0;
|
||||
d_can1 = &dcan1;
|
||||
usb0 = &usb0;
|
||||
usb1 = &usb1;
|
||||
phy0 = &usb0_phy;
|
||||
phy1 = &usb1_phy;
|
||||
ethernet0 = &cpsw_emac0;
|
||||
ethernet1 = &cpsw_emac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
/*
|
||||
* To consider voltage drop between PMIC and SoC,
|
||||
* tolerance value is reduced to 2% from 4% and
|
||||
* voltage value is increased as a precaution.
|
||||
*/
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
720000 1285000
|
||||
600000 1225000
|
||||
500000 1125000
|
||||
275000 1125000
|
||||
>;
|
||||
voltage-tolerance = <2>; /* 2 percentage */
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
};
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a8-pmu";
|
||||
interrupts = <3>;
|
||||
};
|
||||
|
||||
/*
|
||||
* The soc node represents the soc top level view. It is used for IPs
|
||||
* that are not memory mapped in the MPU view or for the MPU itself.
|
||||
*/
|
||||
soc {
|
||||
compatible = "ti,omap-infra";
|
||||
mpu {
|
||||
compatible = "ti,omap3-mpu";
|
||||
ti,hwmods = "mpu";
|
||||
};
|
||||
};
|
||||
|
||||
am33xx_control_module: control_module@4a002000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x44e10000 0x7fc>;
|
||||
};
|
||||
|
||||
am33xx_pinmux: pinmux@44e10800 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x44e10800 0x0238>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x7f>;
|
||||
};
|
||||
|
||||
/*
|
||||
* XXX: Use a flat representation of the AM33XX interconnect.
|
||||
* The real AM33XX interconnect network is quite complex. Since
|
||||
* it will not bring real advantage to represent that in DT
|
||||
* for the moment, just use a fake OCP bus entry to represent
|
||||
* the whole bus hierarchy.
|
||||
*/
|
||||
ocp {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
|
||||
prcm: prcm@44e00000 {
|
||||
compatible = "ti,am3-prcm";
|
||||
reg = <0x44e00000 0x4000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@44e10000 {
|
||||
compatible = "ti,am3-scrm";
|
||||
reg = <0x44e10000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
cm: syscon@44e10000 {
|
||||
compatible = "ti,am33xx-controlmodule", "syscon";
|
||||
reg = <0x44e10000 0x800>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@48200000 {
|
||||
compatible = "ti,am33xx-intc";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0x48200000 0x1000>;
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
|
||||
reg = <0x49000000 0x10000>,
|
||||
<0x44e10f90 0x40>;
|
||||
interrupts = <12 13 14>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
gpio0: gpio@44e07000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio1";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x44e07000 0x1000>;
|
||||
interrupts = <96>;
|
||||
};
|
||||
|
||||
gpio1: gpio@4804c000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio2";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupts = <98>;
|
||||
};
|
||||
|
||||
gpio2: gpio@481ac000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio3";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x481ac000 0x1000>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
|
||||
gpio3: gpio@481ae000 {
|
||||
compatible = "ti,omap4-gpio";
|
||||
ti,hwmods = "gpio4";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x481ae000 0x1000>;
|
||||
interrupts = <62>;
|
||||
};
|
||||
|
||||
uart0: serial@44e09000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart1";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupts = <72>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 26>, <&edma 27>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart1: serial@48022000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart2";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48022000 0x2000>;
|
||||
interrupts = <73>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 28>, <&edma 29>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart2: serial@48024000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart3";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x48024000 0x2000>;
|
||||
interrupts = <74>;
|
||||
status = "disabled";
|
||||
dmas = <&edma 30>, <&edma 31>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
uart3: serial@481a6000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a6000 0x2000>;
|
||||
interrupts = <44>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481a8000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart5";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481a8000 0x2000>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481aa000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart6";
|
||||
clock-frequency = <48000000>;
|
||||
reg = <0x481aa000 0x2000>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c1";
|
||||
reg = <0x44e0b000 0x1000>;
|
||||
interrupts = <70>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@4802a000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c2";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
interrupts = <71>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@4819c000 {
|
||||
compatible = "ti,omap4-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "i2c3";
|
||||
reg = <0x4819c000 0x1000>;
|
||||
interrupts = <30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@48060000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
ti,needs-special-reset;
|
||||
ti,needs-special-hs-handling;
|
||||
dmas = <&edma 24
|
||||
&edma 25>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <64>;
|
||||
interrupt-parent = <&intc>;
|
||||
reg = <0x48060000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@481d8000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc2";
|
||||
ti,needs-special-reset;
|
||||
dmas = <&edma 2
|
||||
&edma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <28>;
|
||||
interrupt-parent = <&intc>;
|
||||
reg = <0x481d8000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc3: mmc@47810000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <29>;
|
||||
interrupt-parent = <&intc>;
|
||||
reg = <0x47810000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@480ca000 {
|
||||
compatible = "ti,omap4-hwspinlock";
|
||||
reg = <0x480ca000 0x1000>;
|
||||
ti,hwmods = "spinlock";
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
wdt2: wdt@44e35000 {
|
||||
compatible = "ti,omap3-wdt";
|
||||
ti,hwmods = "wd_timer2";
|
||||
reg = <0x44e35000 0x1000>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
dcan0: can@481cc000 {
|
||||
compatible = "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can0";
|
||||
reg = <0x481cc000 0x2000>;
|
||||
clocks = <&dcan0_fck>;
|
||||
clock-names = "fck";
|
||||
syscon-raminit = <&am33xx_control_module 0x644 0>;
|
||||
interrupts = <52>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcan1: can@481d0000 {
|
||||
compatible = "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can1";
|
||||
reg = <0x481d0000 0x2000>;
|
||||
clocks = <&dcan1_fck>;
|
||||
clock-names = "fck";
|
||||
syscon-raminit = <&am33xx_control_module 0x644 1>;
|
||||
interrupts = <55>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480C8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480C8000 0x200>;
|
||||
interrupts = <77>;
|
||||
ti,hwmods = "mailbox";
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_wkupm3: wkup_m3 {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <0 0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
compatible = "ti,am335x-timer-1ms";
|
||||
reg = <0x44e31000 0x400>;
|
||||
interrupts = <67>;
|
||||
ti,hwmods = "timer1";
|
||||
ti,timer-alwon;
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48040000 0x400>;
|
||||
interrupts = <68>;
|
||||
ti,hwmods = "timer2";
|
||||
};
|
||||
|
||||
timer3: timer@48042000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48042000 0x400>;
|
||||
interrupts = <69>;
|
||||
ti,hwmods = "timer3";
|
||||
};
|
||||
|
||||
timer4: timer@48044000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48044000 0x400>;
|
||||
interrupts = <92>;
|
||||
ti,hwmods = "timer4";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer5: timer@48046000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48046000 0x400>;
|
||||
interrupts = <93>;
|
||||
ti,hwmods = "timer5";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer6: timer@48048000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x48048000 0x400>;
|
||||
interrupts = <94>;
|
||||
ti,hwmods = "timer6";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
timer7: timer@4804a000 {
|
||||
compatible = "ti,am335x-timer";
|
||||
reg = <0x4804a000 0x400>;
|
||||
interrupts = <95>;
|
||||
ti,hwmods = "timer7";
|
||||
ti,timer-pwm;
|
||||
};
|
||||
|
||||
rtc: rtc@44e3e000 {
|
||||
compatible = "ti,am3352-rtc", "ti,da830-rtc";
|
||||
reg = <0x44e3e000 0x1000>;
|
||||
interrupts = <75
|
||||
76>;
|
||||
ti,hwmods = "rtc";
|
||||
};
|
||||
|
||||
spi0: spi@48030000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x48030000 0x400>;
|
||||
interrupts = <65>;
|
||||
ti,spi-num-cs = <2>;
|
||||
ti,hwmods = "spi0";
|
||||
dmas = <&edma 16
|
||||
&edma 17
|
||||
&edma 18
|
||||
&edma 19>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@481a0000 {
|
||||
compatible = "ti,omap4-mcspi";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x481a0000 0x400>;
|
||||
interrupts = <125>;
|
||||
ti,spi-num-cs = <2>;
|
||||
ti,hwmods = "spi1";
|
||||
dmas = <&edma 42
|
||||
&edma 43
|
||||
&edma 44
|
||||
&edma 45>;
|
||||
dma-names = "tx0", "rx0", "tx1", "rx1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb: usb@47400000 {
|
||||
compatible = "ti,am33xx-usb";
|
||||
reg = <0x47400000 0x1000>;
|
||||
ranges;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,hwmods = "usb_otg_hs";
|
||||
status = "disabled";
|
||||
|
||||
usb_ctrl_mod: control@44e10620 {
|
||||
compatible = "ti,am335x-usb-ctrl-module";
|
||||
reg = <0x44e10620 0x10
|
||||
0x44e10648 0x4>;
|
||||
reg-names = "phy_ctrl", "wakeup";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb0_phy: usb-phy@47401300 {
|
||||
compatible = "ti,am335x-usb-phy";
|
||||
reg = <0x47401300 0x100>;
|
||||
reg-names = "phy";
|
||||
status = "disabled";
|
||||
ti,ctrl_mod = <&usb_ctrl_mod>;
|
||||
};
|
||||
|
||||
usb0: usb@47401000 {
|
||||
compatible = "ti,musb-am33xx";
|
||||
status = "disabled";
|
||||
reg = <0x47401400 0x400
|
||||
0x47401000 0x200>;
|
||||
reg-names = "mc", "control";
|
||||
|
||||
interrupts = <18>;
|
||||
interrupt-names = "mc";
|
||||
dr_mode = "otg";
|
||||
mentor,multipoint = <1>;
|
||||
mentor,num-eps = <16>;
|
||||
mentor,ram-bits = <12>;
|
||||
mentor,power = <500>;
|
||||
phys = <&usb0_phy>;
|
||||
|
||||
dmas = <&cppi41dma 0 0 &cppi41dma 1 0
|
||||
&cppi41dma 2 0 &cppi41dma 3 0
|
||||
&cppi41dma 4 0 &cppi41dma 5 0
|
||||
&cppi41dma 6 0 &cppi41dma 7 0
|
||||
&cppi41dma 8 0 &cppi41dma 9 0
|
||||
&cppi41dma 10 0 &cppi41dma 11 0
|
||||
&cppi41dma 12 0 &cppi41dma 13 0
|
||||
&cppi41dma 14 0 &cppi41dma 0 1
|
||||
&cppi41dma 1 1 &cppi41dma 2 1
|
||||
&cppi41dma 3 1 &cppi41dma 4 1
|
||||
&cppi41dma 5 1 &cppi41dma 6 1
|
||||
&cppi41dma 7 1 &cppi41dma 8 1
|
||||
&cppi41dma 9 1 &cppi41dma 10 1
|
||||
&cppi41dma 11 1 &cppi41dma 12 1
|
||||
&cppi41dma 13 1 &cppi41dma 14 1>;
|
||||
dma-names =
|
||||
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
||||
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
||||
"rx14", "rx15",
|
||||
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
||||
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
||||
"tx14", "tx15";
|
||||
};
|
||||
|
||||
usb1_phy: usb-phy@47401b00 {
|
||||
compatible = "ti,am335x-usb-phy";
|
||||
reg = <0x47401b00 0x100>;
|
||||
reg-names = "phy";
|
||||
status = "disabled";
|
||||
ti,ctrl_mod = <&usb_ctrl_mod>;
|
||||
};
|
||||
|
||||
usb1: usb@47401800 {
|
||||
compatible = "ti,musb-am33xx";
|
||||
status = "disabled";
|
||||
reg = <0x47401c00 0x400
|
||||
0x47401800 0x200>;
|
||||
reg-names = "mc", "control";
|
||||
interrupts = <19>;
|
||||
interrupt-names = "mc";
|
||||
dr_mode = "otg";
|
||||
mentor,multipoint = <1>;
|
||||
mentor,num-eps = <16>;
|
||||
mentor,ram-bits = <12>;
|
||||
mentor,power = <500>;
|
||||
phys = <&usb1_phy>;
|
||||
|
||||
dmas = <&cppi41dma 15 0 &cppi41dma 16 0
|
||||
&cppi41dma 17 0 &cppi41dma 18 0
|
||||
&cppi41dma 19 0 &cppi41dma 20 0
|
||||
&cppi41dma 21 0 &cppi41dma 22 0
|
||||
&cppi41dma 23 0 &cppi41dma 24 0
|
||||
&cppi41dma 25 0 &cppi41dma 26 0
|
||||
&cppi41dma 27 0 &cppi41dma 28 0
|
||||
&cppi41dma 29 0 &cppi41dma 15 1
|
||||
&cppi41dma 16 1 &cppi41dma 17 1
|
||||
&cppi41dma 18 1 &cppi41dma 19 1
|
||||
&cppi41dma 20 1 &cppi41dma 21 1
|
||||
&cppi41dma 22 1 &cppi41dma 23 1
|
||||
&cppi41dma 24 1 &cppi41dma 25 1
|
||||
&cppi41dma 26 1 &cppi41dma 27 1
|
||||
&cppi41dma 28 1 &cppi41dma 29 1>;
|
||||
dma-names =
|
||||
"rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
|
||||
"rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
|
||||
"rx14", "rx15",
|
||||
"tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
|
||||
"tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
|
||||
"tx14", "tx15";
|
||||
};
|
||||
|
||||
cppi41dma: dma-controller@47402000 {
|
||||
compatible = "ti,am3359-cppi41";
|
||||
reg = <0x47400000 0x1000
|
||||
0x47402000 0x1000
|
||||
0x47403000 0x1000
|
||||
0x47404000 0x4000>;
|
||||
reg-names = "glue", "controller", "scheduler", "queuemgr";
|
||||
interrupts = <17>;
|
||||
interrupt-names = "glue";
|
||||
#dma-cells = <2>;
|
||||
#dma-channels = <30>;
|
||||
#dma-requests = <256>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48300000 0x10>;
|
||||
ti,hwmods = "epwmss0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48300100 0x48300100 0x80 /* ECAP */
|
||||
0x48300180 0x48300180 0x80 /* EQEP */
|
||||
0x48300200 0x48300200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
interrupts = <31>;
|
||||
interrupt-names = "ecap0";
|
||||
ti,hwmods = "ecap0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: ehrpwm@48300200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
ti,hwmods = "ehrpwm0";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss1: epwmss@48302000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48302000 0x10>;
|
||||
ti,hwmods = "epwmss1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48302100 0x48302100 0x80 /* ECAP */
|
||||
0x48302180 0x48302180 0x80 /* EQEP */
|
||||
0x48302200 0x48302200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
interrupts = <47>;
|
||||
interrupt-names = "ecap1";
|
||||
ti,hwmods = "ecap1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: ehrpwm@48302200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
ti,hwmods = "ehrpwm1";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48304000 {
|
||||
compatible = "ti,am33xx-pwmss";
|
||||
reg = <0x48304000 0x10>;
|
||||
ti,hwmods = "epwmss2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
ranges = <0x48304100 0x48304100 0x80 /* ECAP */
|
||||
0x48304180 0x48304180 0x80 /* EQEP */
|
||||
0x48304200 0x48304200 0x80>; /* EHRPWM */
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
interrupts = <61>;
|
||||
interrupt-names = "ecap2";
|
||||
ti,hwmods = "ecap2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: ehrpwm@48304200 {
|
||||
compatible = "ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
ti,hwmods = "ehrpwm2";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
mac: ethernet@4a100000 {
|
||||
compatible = "ti,cpsw";
|
||||
ti,hwmods = "cpgmac0";
|
||||
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
|
||||
clock-names = "fck", "cpts";
|
||||
cpdma_channels = <8>;
|
||||
ale_entries = <1024>;
|
||||
bd_ram_size = <0x2000>;
|
||||
no_bd_ram = <0>;
|
||||
rx_descs = <64>;
|
||||
mac_control = <0x20>;
|
||||
slaves = <2>;
|
||||
active_slave = <0>;
|
||||
cpts_clock_mult = <0x80000000>;
|
||||
cpts_clock_shift = <29>;
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a101200 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
/*
|
||||
* c0_rx_thresh_pend
|
||||
* c0_rx_pend
|
||||
* c0_tx_pend
|
||||
* c0_misc_pend
|
||||
*/
|
||||
interrupts = <40 41 42 43>;
|
||||
ranges;
|
||||
syscon = <&cm>;
|
||||
status = "disabled";
|
||||
|
||||
davinci_mdio: mdio@4a101000 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "davinci_mdio";
|
||||
bus_freq = <1000000>;
|
||||
reg = <0x4a101000 0x100>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpsw_emac0: slave@4a100200 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
cpsw_emac1: slave@4a100300 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
phy_sel: cpsw-phy-sel@44e10650 {
|
||||
compatible = "ti,am3352-cpsw-phy-sel";
|
||||
reg= <0x44e10650 0x4>;
|
||||
reg-names = "gmii-sel";
|
||||
};
|
||||
};
|
||||
|
||||
ocmcram: ocmcram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x10000>; /* 64k */
|
||||
};
|
||||
|
||||
wkup_m3: wkup_m3@44d00000 {
|
||||
compatible = "ti,am3353-wkup-m3";
|
||||
reg = <0x44d00000 0x4000 /* M3 UMEM */
|
||||
0x44d80000 0x2000>; /* M3 DMEM */
|
||||
ti,hwmods = "wkup_m3";
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,am3352-elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <4>;
|
||||
ti,hwmods = "elm";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdc: lcdc@4830e000 {
|
||||
compatible = "ti,am33xx-tilcdc";
|
||||
reg = <0x4830e000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <36>;
|
||||
ti,hwmods = "lcdc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tscadc: tscadc@44e0d000 {
|
||||
compatible = "ti,am3359-tscadc";
|
||||
reg = <0x44e0d000 0x1000>;
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <16>;
|
||||
ti,hwmods = "adc_tsc";
|
||||
status = "disabled";
|
||||
|
||||
tsc {
|
||||
compatible = "ti,am3359-tsc";
|
||||
};
|
||||
am335x_adc: adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
ti,no-idle-on-init;
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <100>;
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sham: sham@53100000 {
|
||||
compatible = "ti,omap4-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x53100000 0x200>;
|
||||
interrupts = <109>;
|
||||
dmas = <&edma 36>;
|
||||
dma-names = "rx";
|
||||
};
|
||||
|
||||
aes: aes@53500000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x53500000 0xa0>;
|
||||
interrupts = <103>;
|
||||
dmas = <&edma 6>,
|
||||
<&edma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mcasp0: mcasp@48038000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp0";
|
||||
reg = <0x48038000 0x2000>,
|
||||
<0x46000000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <80>, <81>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 8>,
|
||||
<&edma 9>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@4803C000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp1";
|
||||
reg = <0x4803C000 0x2000>,
|
||||
<0x46400000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <82>, <83>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 10>,
|
||||
<&edma 11>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
rng: rng@48310000 {
|
||||
compatible = "ti,omap4-rng";
|
||||
ti,hwmods = "rng";
|
||||
reg = <0x48310000 0x2000>;
|
||||
interrupts = <111>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "am33xx-clocks.dtsi"
|
||||
174
sys/gnu/dts/arm/am3517-craneboard.dts
Normal file
174
sys/gnu/dts/arm/am3517-craneboard.dts
Normal file
@ -0,0 +1,174 @@
|
||||
/*
|
||||
* See craneboard.org for more details
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am3517.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM3517 CraneBoard (TMDSEVM3517)";
|
||||
compatible = "ti,am3517-craneboard", "ti,am3517", "ti,omap3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vbat: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vbat";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
&davinci_emac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <2600000>;
|
||||
|
||||
tps: tps@2d {
|
||||
reg = <0x2d>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
/* goes to expansion connector */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
/* goes to expansion connector */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vdd2_reg>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
/* goes to expansion connector */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
/* goes to expansion connector */
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
#include "tps65910.dtsi"
|
||||
|
||||
&omap3_pmx_core {
|
||||
tps_pins: pinmux_tps_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq.sys_nirq */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&tps {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps_pins>;
|
||||
|
||||
interrupts = <7>; /* SYS_NIRQ cascaded to intc */
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
ti,en-ck32k-xtal;
|
||||
|
||||
vcc1-supply = <&vbat>;
|
||||
vcc2-supply = <&vbat>;
|
||||
vcc3-supply = <&vbat>;
|
||||
vcc4-supply = <&vbat>;
|
||||
vcc5-supply = <&vbat>;
|
||||
vcc6-supply = <&vbat>;
|
||||
vcc7-supply = <&vbat>;
|
||||
vccio-supply = <&vbat>;
|
||||
|
||||
regulators {
|
||||
vrtc_reg: regulator@0 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vio_reg: regulator@1 {
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/*
|
||||
* Unused:
|
||||
* VDIG1=2.7V,300mA max
|
||||
* VDIG2=1.8V,300mA max
|
||||
*/
|
||||
|
||||
vpll_reg: regulator@7 {
|
||||
/* VDDS_DPLL_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux1_reg: regulator@9 {
|
||||
/* VDDS_SRAM_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vaux2_reg: regulator@10 {
|
||||
/* VDDA1P8V_USBPHY */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* VAUX33 unused */
|
||||
|
||||
vdac_reg: regulator@8 {
|
||||
/* VDDA_DAC_1V8 */
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vmmc_reg: regulator@12 {
|
||||
/* VDDA3P3V_USBPHY */
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd1_reg: regulator@2 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vdd2_reg: regulator@3 {
|
||||
/* VDDSHV_3V3 */
|
||||
regulator-name = "vdd_shv";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
/* VDD3 unused */
|
||||
};
|
||||
};
|
||||
61
sys/gnu/dts/arm/am3517-evm.dts
Normal file
61
sys/gnu/dts/arm/am3517-evm.dts
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "am3517.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TI AM3517 EVM (AM3517/05 TMDSEVM3517)";
|
||||
compatible = "ti,am3517-evm", "ti,am3517", "ti,omap3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
vmmc_fixed: vmmc {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
};
|
||||
|
||||
&davinci_emac {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
vmmc-supply = <&vmmc_fixed>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmc3 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
83
sys/gnu/dts/arm/am3517.dtsi
Normal file
83
sys/gnu/dts/arm/am3517.dtsi
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* Device Tree Source for am3517 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include "omap3.dtsi"
|
||||
|
||||
/ {
|
||||
aliases {
|
||||
serial3 = &uart4;
|
||||
};
|
||||
|
||||
ocp {
|
||||
am35x_otg_hs: am35x_otg_hs@5c040000 {
|
||||
compatible = "ti,omap3-musb";
|
||||
ti,hwmods = "am35x_otg_hs";
|
||||
status = "disabled";
|
||||
reg = <0x5c040000 0x1000>;
|
||||
interrupts = <71>;
|
||||
interrupt-names = "mc";
|
||||
};
|
||||
|
||||
davinci_emac: ethernet@0x5c000000 {
|
||||
compatible = "ti,am3517-emac";
|
||||
ti,hwmods = "davinci_emac";
|
||||
status = "disabled";
|
||||
reg = <0x5c000000 0x30000>;
|
||||
interrupts = <67 68 69 70>;
|
||||
syscon = <&omap3_scm_general>;
|
||||
ti,davinci-ctrl-reg-offset = <0x10000>;
|
||||
ti,davinci-ctrl-mod-reg-offset = <0>;
|
||||
ti,davinci-ctrl-ram-offset = <0x20000>;
|
||||
ti,davinci-ctrl-ram-size = <0x2000>;
|
||||
ti,davinci-rmii-en = /bits/ 8 <1>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
davinci_mdio: ethernet@0x5c030000 {
|
||||
compatible = "ti,davinci_mdio";
|
||||
ti,hwmods = "davinci_mdio";
|
||||
status = "disabled";
|
||||
reg = <0x5c030000 0x1000>;
|
||||
bus_freq = <1000000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
uart4: serial@4809e000 {
|
||||
compatible = "ti,omap3-uart";
|
||||
ti,hwmods = "uart4";
|
||||
status = "disabled";
|
||||
reg = <0x4809e000 0x400>;
|
||||
interrupts = <84>;
|
||||
dmas = <&sdma 55 &sdma 54>;
|
||||
dma-names = "tx", "rx";
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iva {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mailbox {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&mmu_isp {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
&smartreflex_mpu_iva {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/include/ "am35xx-clocks.dtsi"
|
||||
/include/ "omap36xx-am35xx-omap3430es2plus-clocks.dtsi"
|
||||
27
sys/gnu/dts/arm/am3517_mt_ventoux.dts
Normal file
27
sys/gnu/dts/arm/am3517_mt_ventoux.dts
Normal file
@ -0,0 +1,27 @@
|
||||
/*
|
||||
* Copyright (C) 2011 Ilya Yanok, EmCraft Systems
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "omap34xx.dtsi"
|
||||
|
||||
/ {
|
||||
model = "TeeJet Mt.Ventoux";
|
||||
compatible = "teejet,mt_ventoux", "ti,omap3";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
/* AM35xx doesn't have IVA */
|
||||
soc {
|
||||
iva {
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
128
sys/gnu/dts/arm/am35xx-clocks.dtsi
Normal file
128
sys/gnu/dts/arm/am35xx-clocks.dtsi
Normal file
@ -0,0 +1,128 @@
|
||||
/*
|
||||
* Device Tree Source for OMAP3 clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
emac_ick: emac_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <1>;
|
||||
};
|
||||
|
||||
emac_fck: emac_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&rmii_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <9>;
|
||||
};
|
||||
|
||||
vpfe_ick: vpfe_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <2>;
|
||||
};
|
||||
|
||||
vpfe_fck: vpfe_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&pclk_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <10>;
|
||||
};
|
||||
|
||||
hsotgusb_ick_am35xx: hsotgusb_ick_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&ipss_ick>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <0>;
|
||||
};
|
||||
|
||||
hsotgusb_fck_am35xx: hsotgusb_fck_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <8>;
|
||||
};
|
||||
|
||||
hecc_ck: hecc_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-gate-clock";
|
||||
clocks = <&sys_ck>;
|
||||
reg = <0x059c>;
|
||||
ti,bit-shift = <3>;
|
||||
};
|
||||
};
|
||||
&cm_clocks {
|
||||
ipss_ick: ipss_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am35xx-interface-clock";
|
||||
clocks = <&core_l3_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <4>;
|
||||
};
|
||||
|
||||
rmii_ck: rmii_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
pclk_ck: pclk_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <27000000>;
|
||||
};
|
||||
|
||||
uart4_ick_am35xx: uart4_ick_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,omap3-interface-clock";
|
||||
clocks = <&core_l4_ick>;
|
||||
reg = <0x0a10>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
|
||||
uart4_fck_am35xx: uart4_fck_am35xx {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,wait-gate-clock";
|
||||
clocks = <&core_48m_fck>;
|
||||
reg = <0x0a00>;
|
||||
ti,bit-shift = <23>;
|
||||
};
|
||||
};
|
||||
|
||||
&cm_clockdomains {
|
||||
core_l3_clkdm: core_l3_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&sdrc_ick>, <&ipss_ick>, <&emac_ick>, <&vpfe_ick>,
|
||||
<&hsotgusb_ick_am35xx>, <&hsotgusb_fck_am35xx>,
|
||||
<&hecc_ck>;
|
||||
};
|
||||
|
||||
core_l4_clkdm: core_l4_clkdm {
|
||||
compatible = "ti,clockdomain";
|
||||
clocks = <&cpefuse_fck>, <&ts_fck>, <&usbtll_fck>,
|
||||
<&usbtll_ick>, <&mmchs3_ick>, <&mmchs3_fck>,
|
||||
<&mmchs2_fck>, <&mmchs1_fck>, <&i2c3_fck>, <&i2c2_fck>,
|
||||
<&i2c1_fck>, <&mcspi4_fck>, <&mcspi3_fck>,
|
||||
<&mcspi2_fck>, <&mcspi1_fck>, <&uart2_fck>,
|
||||
<&uart1_fck>, <&hdq_fck>, <&mmchs2_ick>, <&mmchs1_ick>,
|
||||
<&hdq_ick>, <&mcspi4_ick>, <&mcspi3_ick>,
|
||||
<&mcspi2_ick>, <&mcspi1_ick>, <&i2c3_ick>, <&i2c2_ick>,
|
||||
<&i2c1_ick>, <&uart2_ick>, <&uart1_ick>, <&gpt11_ick>,
|
||||
<&gpt10_ick>, <&mcbsp5_ick>, <&mcbsp1_ick>,
|
||||
<&omapctrl_ick>, <&aes2_ick>, <&sha12_ick>,
|
||||
<&uart4_ick_am35xx>, <&uart4_fck_am35xx>;
|
||||
};
|
||||
};
|
||||
970
sys/gnu/dts/arm/am4372.dtsi
Normal file
970
sys/gnu/dts/arm/am4372.dtsi
Normal file
@ -0,0 +1,970 @@
|
||||
/*
|
||||
* Device Tree Source for AM4372 SoC
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public License
|
||||
* version 2. This program is licensed "as is" without any warranty of any
|
||||
* kind, whether express or implied.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "ti,am4372", "ti,am43";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
|
||||
aliases {
|
||||
i2c0 = &i2c0;
|
||||
i2c1 = &i2c1;
|
||||
i2c2 = &i2c2;
|
||||
serial0 = &uart0;
|
||||
ethernet0 = &cpsw_emac0;
|
||||
ethernet1 = &cpsw_emac1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu: cpu@0 {
|
||||
compatible = "arm,cortex-a9";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
clock-names = "cpu";
|
||||
|
||||
clock-latency = <300000>; /* From omap-cpufreq driver */
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@48241000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x48241000 0x1000>,
|
||||
<0x48240100 0x0100>;
|
||||
};
|
||||
|
||||
l2-cache-controller@48242000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x48242000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
am43xx_control_module: control_module@4a002000 {
|
||||
compatible = "syscon";
|
||||
reg = <0x44e10000 0x7f4>;
|
||||
};
|
||||
|
||||
am43xx_pinmux: pinmux@44e10800 {
|
||||
compatible = "ti,am437-padconf", "pinctrl-single";
|
||||
reg = <0x44e10800 0x31c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0xffffffff>;
|
||||
};
|
||||
|
||||
ocp {
|
||||
compatible = "ti,am4372-l3-noc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "l3_main";
|
||||
reg = <0x44000000 0x400000
|
||||
0x44800000 0x400000>;
|
||||
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
prcm: prcm@44df0000 {
|
||||
compatible = "ti,am4-prcm";
|
||||
reg = <0x44df0000 0x11000>;
|
||||
|
||||
prcm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
prcm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
scrm: scrm@44e10000 {
|
||||
compatible = "ti,am4-scrm";
|
||||
reg = <0x44e10000 0x2000>;
|
||||
|
||||
scrm_clocks: clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
scrm_clockdomains: clockdomains {
|
||||
};
|
||||
};
|
||||
|
||||
edma: edma@49000000 {
|
||||
compatible = "ti,edma3";
|
||||
ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
|
||||
reg = <0x49000000 0x10000>,
|
||||
<0x44e10f90 0x10>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
uart0: serial@44e09000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x44e09000 0x2000>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart1";
|
||||
};
|
||||
|
||||
uart1: serial@48022000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x48022000 0x2000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@48024000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x48024000 0x2000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@481a6000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x481a6000 0x2000>;
|
||||
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@481a8000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x481a8000 0x2000>;
|
||||
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@481aa000 {
|
||||
compatible = "ti,am4372-uart","ti,omap2-uart";
|
||||
reg = <0x481aa000 0x2000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "uart6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mailbox: mailbox@480C8000 {
|
||||
compatible = "ti,omap4-mailbox";
|
||||
reg = <0x480C8000 0x200>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "mailbox";
|
||||
#mbox-cells = <1>;
|
||||
ti,mbox-num-users = <4>;
|
||||
ti,mbox-num-fifos = <8>;
|
||||
mbox_wkupm3: wkup_m3 {
|
||||
ti,mbox-tx = <0 0 0>;
|
||||
ti,mbox-rx = <0 0 3>;
|
||||
};
|
||||
};
|
||||
|
||||
timer1: timer@44e31000 {
|
||||
compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
|
||||
reg = <0x44e31000 0x400>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-alwon;
|
||||
ti,hwmods = "timer1";
|
||||
};
|
||||
|
||||
timer2: timer@48040000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48040000 0x400>;
|
||||
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer2";
|
||||
};
|
||||
|
||||
timer3: timer@48042000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48042000 0x400>;
|
||||
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer4: timer@48044000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48044000 0x400>;
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer5: timer@48046000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48046000 0x400>;
|
||||
interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer6: timer@48048000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48048000 0x400>;
|
||||
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer7: timer@4804a000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x4804a000 0x400>;
|
||||
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,timer-pwm;
|
||||
ti,hwmods = "timer7";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer8: timer@481c1000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x481c1000 0x400>;
|
||||
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer8";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer9: timer@4833d000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x4833d000 0x400>;
|
||||
interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer9";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer10: timer@4833f000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x4833f000 0x400>;
|
||||
interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer10";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer11: timer@48341000 {
|
||||
compatible = "ti,am4372-timer","ti,am335x-timer";
|
||||
reg = <0x48341000 0x400>;
|
||||
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "timer11";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
counter32k: counter@44e86000 {
|
||||
compatible = "ti,am4372-counter32k","ti,omap-counter32k";
|
||||
reg = <0x44e86000 0x40>;
|
||||
ti,hwmods = "counter_32k";
|
||||
};
|
||||
|
||||
rtc: rtc@44e3e000 {
|
||||
compatible = "ti,am4372-rtc","ti,da830-rtc";
|
||||
reg = <0x44e3e000 0x1000>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "rtc";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wdt: wdt@44e35000 {
|
||||
compatible = "ti,am4372-wdt","ti,omap3-wdt";
|
||||
reg = <0x44e35000 0x1000>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "wd_timer2";
|
||||
};
|
||||
|
||||
gpio0: gpio@44e07000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x44e07000 0x1000>;
|
||||
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@4804c000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x4804c000 0x1000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio2: gpio@481ac000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x481ac000 0x1000>;
|
||||
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio3";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio3: gpio@481ae000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x481ae000 0x1000>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio4";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio4: gpio@48320000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x48320000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio5";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio5: gpio@48322000 {
|
||||
compatible = "ti,am4372-gpio","ti,omap4-gpio";
|
||||
reg = <0x48322000 0x1000>;
|
||||
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
ti,hwmods = "gpio6";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hwspinlock: spinlock@480ca000 {
|
||||
compatible = "ti,omap4-hwspinlock";
|
||||
reg = <0x480ca000 0x1000>;
|
||||
ti,hwmods = "spinlock";
|
||||
#hwlock-cells = <1>;
|
||||
};
|
||||
|
||||
i2c0: i2c@44e0b000 {
|
||||
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
||||
reg = <0x44e0b000 0x1000>;
|
||||
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "i2c1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@4802a000 {
|
||||
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
||||
reg = <0x4802a000 0x1000>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "i2c2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c2: i2c@4819c000 {
|
||||
compatible = "ti,am4372-i2c","ti,omap4-i2c";
|
||||
reg = <0x4819c000 0x1000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "i2c3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@48030000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x48030000 0x400>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc1: mmc@48060000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x48060000 0x1000>;
|
||||
ti,hwmods = "mmc1";
|
||||
ti,dual-volt;
|
||||
ti,needs-special-reset;
|
||||
dmas = <&edma 24
|
||||
&edma 25>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc2: mmc@481d8000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x481d8000 0x1000>;
|
||||
ti,hwmods = "mmc2";
|
||||
ti,needs-special-reset;
|
||||
dmas = <&edma 2
|
||||
&edma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc3: mmc@47810000 {
|
||||
compatible = "ti,omap4-hsmmc";
|
||||
reg = <0x47810000 0x1000>;
|
||||
ti,hwmods = "mmc3";
|
||||
ti,needs-special-reset;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@481a0000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x481a0000 0x400>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi1";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi2: spi@481a2000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x481a2000 0x400>;
|
||||
interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi2";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi3: spi@481a4000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x481a4000 0x400>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi3";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi4: spi@48345000 {
|
||||
compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
|
||||
reg = <0x48345000 0x400>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "spi4";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mac: ethernet@4a100000 {
|
||||
compatible = "ti,am4372-cpsw","ti,cpsw";
|
||||
reg = <0x4a100000 0x800
|
||||
0x4a101200 0x100>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ti,hwmods = "cpgmac0";
|
||||
clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
|
||||
clock-names = "fck", "cpts";
|
||||
status = "disabled";
|
||||
cpdma_channels = <8>;
|
||||
ale_entries = <1024>;
|
||||
bd_ram_size = <0x2000>;
|
||||
no_bd_ram = <0>;
|
||||
rx_descs = <64>;
|
||||
mac_control = <0x20>;
|
||||
slaves = <2>;
|
||||
active_slave = <0>;
|
||||
cpts_clock_mult = <0x80000000>;
|
||||
cpts_clock_shift = <29>;
|
||||
ranges;
|
||||
|
||||
davinci_mdio: mdio@4a101000 {
|
||||
compatible = "ti,am4372-mdio","ti,davinci_mdio";
|
||||
reg = <0x4a101000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "davinci_mdio";
|
||||
bus_freq = <1000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
cpsw_emac0: slave@4a100200 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
cpsw_emac1: slave@4a100300 {
|
||||
/* Filled in by U-Boot */
|
||||
mac-address = [ 00 00 00 00 00 00 ];
|
||||
};
|
||||
|
||||
phy_sel: cpsw-phy-sel@44e10650 {
|
||||
compatible = "ti,am43xx-cpsw-phy-sel";
|
||||
reg= <0x44e10650 0x4>;
|
||||
reg-names = "gmii-sel";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss0: epwmss@48300000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48300000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss0";
|
||||
status = "disabled";
|
||||
|
||||
ecap0: ecap@48300100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300100 0x80>;
|
||||
ti,hwmods = "ecap0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm0: ehrpwm@48300200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48300200 0x80>;
|
||||
ti,hwmods = "ehrpwm0";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss1: epwmss@48302000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48302000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss1";
|
||||
status = "disabled";
|
||||
|
||||
ecap1: ecap@48302100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302100 0x80>;
|
||||
ti,hwmods = "ecap1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm1: ehrpwm@48302200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48302200 0x80>;
|
||||
ti,hwmods = "ehrpwm1";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss2: epwmss@48304000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48304000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss2";
|
||||
status = "disabled";
|
||||
|
||||
ecap2: ecap@48304100 {
|
||||
compatible = "ti,am4372-ecap","ti,am33xx-ecap";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304100 0x80>;
|
||||
ti,hwmods = "ecap2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ehrpwm2: ehrpwm@48304200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48304200 0x80>;
|
||||
ti,hwmods = "ehrpwm2";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss3: epwmss@48306000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48306000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss3";
|
||||
status = "disabled";
|
||||
|
||||
ehrpwm3: ehrpwm@48306200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48306200 0x80>;
|
||||
ti,hwmods = "ehrpwm3";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss4: epwmss@48308000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x48308000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss4";
|
||||
status = "disabled";
|
||||
|
||||
ehrpwm4: ehrpwm@48308200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x48308200 0x80>;
|
||||
ti,hwmods = "ehrpwm4";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
epwmss5: epwmss@4830a000 {
|
||||
compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
|
||||
reg = <0x4830a000 0x10>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "epwmss5";
|
||||
status = "disabled";
|
||||
|
||||
ehrpwm5: ehrpwm@4830a200 {
|
||||
compatible = "ti,am4372-ehrpwm","ti,am33xx-ehrpwm";
|
||||
#pwm-cells = <3>;
|
||||
reg = <0x4830a200 0x80>;
|
||||
ti,hwmods = "ehrpwm5";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
tscadc: tscadc@44e0d000 {
|
||||
compatible = "ti,am3359-tscadc";
|
||||
reg = <0x44e0d000 0x1000>;
|
||||
ti,hwmods = "adc_tsc";
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&adc_tsc_fck>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
|
||||
tsc {
|
||||
compatible = "ti,am3359-tsc";
|
||||
};
|
||||
|
||||
adc {
|
||||
#io-channel-cells = <1>;
|
||||
compatible = "ti,am3359-adc";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
sham: sham@53100000 {
|
||||
compatible = "ti,omap5-sham";
|
||||
ti,hwmods = "sham";
|
||||
reg = <0x53100000 0x300>;
|
||||
dmas = <&edma 36>;
|
||||
dma-names = "rx";
|
||||
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
aes: aes@53501000 {
|
||||
compatible = "ti,omap4-aes";
|
||||
ti,hwmods = "aes";
|
||||
reg = <0x53501000 0xa0>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma 6
|
||||
&edma 5>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
des: des@53701000 {
|
||||
compatible = "ti,omap4-des";
|
||||
ti,hwmods = "des";
|
||||
reg = <0x53701000 0xa0>;
|
||||
interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&edma 34
|
||||
&edma 33>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mcasp0: mcasp@48038000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp0";
|
||||
reg = <0x48038000 0x2000>,
|
||||
<0x46000000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <80>, <81>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 8>,
|
||||
<&edma 9>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
mcasp1: mcasp@4803C000 {
|
||||
compatible = "ti,am33xx-mcasp-audio";
|
||||
ti,hwmods = "mcasp1";
|
||||
reg = <0x4803C000 0x2000>,
|
||||
<0x46400000 0x400000>;
|
||||
reg-names = "mpu", "dat";
|
||||
interrupts = <82>, <83>;
|
||||
interrupt-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
dmas = <&edma 10>,
|
||||
<&edma 11>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
|
||||
elm: elm@48080000 {
|
||||
compatible = "ti,am3352-elm";
|
||||
reg = <0x48080000 0x2000>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "elm";
|
||||
clocks = <&l4ls_gclk>;
|
||||
clock-names = "fck";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpmc: gpmc@50000000 {
|
||||
compatible = "ti,am3352-gpmc";
|
||||
ti,hwmods = "gpmc";
|
||||
clocks = <&l3s_gclk>;
|
||||
clock-names = "fck";
|
||||
reg = <0x50000000 0x2000>;
|
||||
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpmc,num-cs = <7>;
|
||||
gpmc,num-waitpins = <2>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
am43xx_control_usb2phy1: control-phy@44e10620 {
|
||||
compatible = "ti,control-phy-usb2-am437";
|
||||
reg = <0x44e10620 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
am43xx_control_usb2phy2: control-phy@0x44e10628 {
|
||||
compatible = "ti,control-phy-usb2-am437";
|
||||
reg = <0x44e10628 0x4>;
|
||||
reg-names = "power";
|
||||
};
|
||||
|
||||
ocp2scp0: ocp2scp@483a8000 {
|
||||
compatible = "ti,omap-ocp2scp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "ocp2scp0";
|
||||
|
||||
usb2_phy1: phy@483a8000 {
|
||||
compatible = "ti,am437x-usb2";
|
||||
reg = <0x483a8000 0x8000>;
|
||||
ctrl-module = <&am43xx_control_usb2phy1>;
|
||||
clocks = <&usb_phy0_always_on_clk32k>,
|
||||
<&usb_otg_ss0_refclk960m>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ocp2scp1: ocp2scp@483e8000 {
|
||||
compatible = "ti,omap-ocp2scp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
ti,hwmods = "ocp2scp1";
|
||||
|
||||
usb2_phy2: phy@483e8000 {
|
||||
compatible = "ti,am437x-usb2";
|
||||
reg = <0x483e8000 0x8000>;
|
||||
ctrl-module = <&am43xx_control_usb2phy2>;
|
||||
clocks = <&usb_phy1_always_on_clk32k>,
|
||||
<&usb_otg_ss1_refclk960m>;
|
||||
clock-names = "wkupclk", "refclk";
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dwc3_1: omap_dwc3@48380000 {
|
||||
compatible = "ti,am437x-dwc3";
|
||||
ti,hwmods = "usb_otg_ss0";
|
||||
reg = <0x48380000 0x10000>;
|
||||
interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
utmi-mode = <1>;
|
||||
ranges;
|
||||
|
||||
usb1: usb@48390000 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x48390000 0x10000>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_phy1>;
|
||||
phy-names = "usb2-phy";
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
dwc3_2: omap_dwc3@483c0000 {
|
||||
compatible = "ti,am437x-dwc3";
|
||||
ti,hwmods = "usb_otg_ss1";
|
||||
reg = <0x483c0000 0x10000>;
|
||||
interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
utmi-mode = <1>;
|
||||
ranges;
|
||||
|
||||
usb2: usb@483d0000 {
|
||||
compatible = "synopsys,dwc3";
|
||||
reg = <0x483d0000 0x10000>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
phys = <&usb2_phy2>;
|
||||
phy-names = "usb2-phy";
|
||||
maximum-speed = "high-speed";
|
||||
dr_mode = "otg";
|
||||
status = "disabled";
|
||||
snps,dis_u3_susphy_quirk;
|
||||
snps,dis_u2_susphy_quirk;
|
||||
};
|
||||
};
|
||||
|
||||
qspi: qspi@47900000 {
|
||||
compatible = "ti,am4372-qspi";
|
||||
reg = <0x47900000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
ti,hwmods = "qspi";
|
||||
interrupts = <0 138 0x4>;
|
||||
num-cs = <4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
hdq: hdq@48347000 {
|
||||
compatible = "ti,am43xx-hdq";
|
||||
reg = <0x48347000 0x1000>;
|
||||
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&func_12m_clk>;
|
||||
clock-names = "fck";
|
||||
ti,hwmods = "hdq1w";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dss: dss@4832a000 {
|
||||
compatible = "ti,omap3-dss";
|
||||
reg = <0x4832a000 0x200>;
|
||||
status = "disabled";
|
||||
ti,hwmods = "dss_core";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
dispc: dispc@4832a400 {
|
||||
compatible = "ti,omap3-dispc";
|
||||
reg = <0x4832a400 0x400>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "dss_dispc";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
|
||||
rfbi: rfbi@4832a800 {
|
||||
compatible = "ti,omap3-rfbi";
|
||||
reg = <0x4832a800 0x100>;
|
||||
ti,hwmods = "dss_rfbi";
|
||||
clocks = <&disp_clk>;
|
||||
clock-names = "fck";
|
||||
};
|
||||
};
|
||||
|
||||
ocmcram: ocmcram@40300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x40300000 0x40000>; /* 256k */
|
||||
};
|
||||
|
||||
dcan0: can@481cc000 {
|
||||
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can0";
|
||||
clocks = <&dcan0_fck>;
|
||||
clock-names = "fck";
|
||||
reg = <0x481cc000 0x2000>;
|
||||
syscon-raminit = <&am43xx_control_module 0x644 0>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dcan1: can@481d0000 {
|
||||
compatible = "ti,am4372-d_can", "ti,am3352-d_can";
|
||||
ti,hwmods = "d_can1";
|
||||
clocks = <&dcan1_fck>;
|
||||
clock-names = "fck";
|
||||
reg = <0x481d0000 0x2000>;
|
||||
syscon-raminit = <&am43xx_control_module 0x644 1>;
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpfe0: vpfe@48326000 {
|
||||
compatible = "ti,am437x-vpfe";
|
||||
reg = <0x48326000 0x2000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "vpfe0";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
vpfe1: vpfe@48328000 {
|
||||
compatible = "ti,am437x-vpfe";
|
||||
reg = <0x48328000 0x2000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
ti,hwmods = "vpfe1";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "am43xx-clocks.dtsi"
|
||||
653
sys/gnu/dts/arm/am437x-gp-evm.dts
Normal file
653
sys/gnu/dts/arm/am437x-gp-evm.dts
Normal file
@ -0,0 +1,653 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* AM437x GP EVM */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
#include <dt-bindings/pinctrl/am43xx.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM437x GP EVM";
|
||||
compatible = "ti,am437x-gp-evm","ti,am4372","ti,am43";
|
||||
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator-vtt {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt_fixed";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH /* Bank3, pin21 */
|
||||
&gpio4 3 GPIO_ACTIVE_HIGH /* Bank4, pin3 */
|
||||
&gpio4 2 GPIO_ACTIVE_HIGH>; /* Bank4, pin2 */
|
||||
|
||||
col-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH /* Bank3, pin19 */
|
||||
&gpio3 20 GPIO_ACTIVE_HIGH>; /* Bank3, pin20 */
|
||||
|
||||
linux,keymap = <0x00000201 /* P1 */
|
||||
0x00010202 /* P2 */
|
||||
0x01000067 /* UP */
|
||||
0x0101006a /* RIGHT */
|
||||
0x02000069 /* LEFT */
|
||||
0x0201006c>; /* DOWN */
|
||||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins>;
|
||||
|
||||
/*
|
||||
* SelLCDorHDMI, LOW to select HDMI. This is not really the
|
||||
* panel's enable GPIO, but we don't have HDMI driver support nor
|
||||
* support to switch between two displays, so using this gpio as
|
||||
* panel's enable should be safe.
|
||||
*/
|
||||
enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <33000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <210>;
|
||||
hback-porch = <16>;
|
||||
hsync-len = <30>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <22>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
i2c0_pins: i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
0x158 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
pixcir_ts_pins: pixcir_ts_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x264 (PIN_INPUT_PULLUP | MUX_MODE7) /* spi2_d0.gpio3_22 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_txen */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rxctl */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd3 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd2 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_txd0 */
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd3 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd2 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rxd0 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
nand_flash_x8: nand_flash_x8 {
|
||||
pinctrl-single,pins = <
|
||||
0x26c(PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* spi2_cs0.gpio/eMMCorNANDsel */
|
||||
0x0 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_pins: dss_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
|
||||
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x02c (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x03c (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
|
||||
0x0a0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
|
||||
0x0a4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0a8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0ac (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0b0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0b4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0b8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0bc (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0c0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0c4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0c8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0cc (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0d0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0d4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0d8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0dc (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
|
||||
0x0e0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
|
||||
0x0e4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
|
||||
0x0e8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
|
||||
0x0ec (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins: lcd_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* GPIO 5_8 to select LCD / HDMI */
|
||||
0x238 (PIN_OUTPUT_PULLUP | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
dcan0_default: dcan0_default_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x178 (PIN_OUTPUT | MUX_MODE2) /* uart1_ctsn.d_can0_tx */
|
||||
0x17c (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_rtsn.d_can0_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
dcan1_default: dcan1_default_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x180 (PIN_OUTPUT | MUX_MODE2) /* uart1_rxd.d_can1_tx */
|
||||
0x184 (PIN_INPUT_PULLUP | MUX_MODE2) /* uart1_txd.d_can1_rx */
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_default: vpfe0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1B0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
|
||||
0x1B4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
|
||||
0x1C0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
|
||||
0x1C4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
|
||||
0x1C8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
|
||||
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
|
||||
0x20C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
|
||||
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
|
||||
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
|
||||
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
|
||||
0x21C (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
|
||||
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
|
||||
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_sleep: vpfe0_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1B0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_hd mode 0*/
|
||||
0x1B4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_vd mode 0*/
|
||||
0x1C0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_pclk mode 0*/
|
||||
0x1C4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data8 mode 0*/
|
||||
0x1C8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data9 mode 0*/
|
||||
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data0 mode 0*/
|
||||
0x20C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data1 mode 0*/
|
||||
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data2 mode 0*/
|
||||
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data3 mode 0*/
|
||||
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data4 mode 0*/
|
||||
0x21C (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data5 mode 0*/
|
||||
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data6 mode 0*/
|
||||
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam0_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe1_pins_default: vpfe1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1CC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0*/
|
||||
0x1D0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0*/
|
||||
0x1D4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0*/
|
||||
0x1D8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0*/
|
||||
0x1DC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0*/
|
||||
0x1E8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0*/
|
||||
0x1EC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0*/
|
||||
0x1F0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0*/
|
||||
0x1F4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0*/
|
||||
0x1F8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0*/
|
||||
0x1FC (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0*/
|
||||
0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0*/
|
||||
0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe1_pins_sleep: vpfe1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1CC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data9 mode 0*/
|
||||
0x1D0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data8 mode 0*/
|
||||
0x1D4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_hd mode 0*/
|
||||
0x1D8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_vd mode 0*/
|
||||
0x1DC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_pclk mode 0*/
|
||||
0x1E8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data0 mode 0*/
|
||||
0x1EC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data1 mode 0*/
|
||||
0x1F0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data2 mode 0*/
|
||||
0x1F4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data3 mode 0*/
|
||||
0x1F8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data4 mode 0*/
|
||||
0x1FC (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data5 mode 0*/
|
||||
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data6 mode 0*/
|
||||
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) /* cam1_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <100000>;
|
||||
|
||||
tps65218: tps65218@24 {
|
||||
reg = <0x24>;
|
||||
compatible = "ti,tps65218";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
dcdc1: regulator-dcdc1 {
|
||||
compatible = "ti,tps65218-dcdc1";
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2: regulator-dcdc2 {
|
||||
compatible = "ti,tps65218-dcdc2";
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1378000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3: regulator-dcdc3 {
|
||||
compatible = "ti,tps65218-dcdc3";
|
||||
regulator-name = "vdcdc3";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
dcdc5: regulator-dcdc5 {
|
||||
compatible = "ti,tps65218-dcdc5";
|
||||
regulator-name = "v1_0bat";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
dcdc6: regulator-dcdc6 {
|
||||
compatible = "ti,tps65218-dcdc6";
|
||||
regulator-name = "v1_8bat";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo1: regulator-ldo1 {
|
||||
compatible = "ti,tps65218-ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pixcir_ts@5c {
|
||||
compatible = "pixcir,pixcir_tangoc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pixcir_ts_pins>;
|
||||
reg = <0x5c>;
|
||||
interrupt-parent = <&gpio3>;
|
||||
interrupts = <22 0>;
|
||||
|
||||
attb-gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
touchscreen-size-x = <1024>;
|
||||
touchscreen-size-y = <600>;
|
||||
};
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
status = "okay";
|
||||
ti,no-reset-on-init;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mac {
|
||||
slaves = <1>;
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x8>;
|
||||
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* device IO registers */
|
||||
ti,nand-ecc-opt = "bch16";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <40>;
|
||||
gpmc,cs-wr-off-ns = <40>;
|
||||
gpmc,adv-on-ns = <0>;
|
||||
gpmc,adv-rd-off-ns = <25>;
|
||||
gpmc,adv-wr-off-ns = <25>;
|
||||
gpmc,we-on-ns = <0>;
|
||||
gpmc,we-off-ns = <20>;
|
||||
gpmc,oe-on-ns = <3>;
|
||||
gpmc,oe-off-ns = <30>;
|
||||
gpmc,access-ns = <30>;
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x000c0000 0x00040000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot-spl-os";
|
||||
reg = <0x00100000 0x00080000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x00180000 0x00100000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x00280000 0x00040000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.u-boot-env.backup1";
|
||||
reg = <0x002c0000 0x00040000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x00300000 0x00700000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a00000 0x1f600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&dcan0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan0_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&dcan1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dcan1_default>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpfe0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe0_pins_default>;
|
||||
pinctrl-1 = <&vpfe0_pins_sleep>;
|
||||
|
||||
port {
|
||||
vpfe0_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vpfe1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe1_pins_default>;
|
||||
pinctrl-1 = <&vpfe1_pins_sleep>;
|
||||
|
||||
port {
|
||||
vpfe1_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
405
sys/gnu/dts/arm/am437x-idk-evm.dts
Normal file
405
sys/gnu/dts/arm/am437x-idk-evm.dts
Normal file
@ -0,0 +1,405 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
#include <dt-bindings/pinctrl/am43xx.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM437x Industrial Development Kit";
|
||||
compatible = "ti,am437x-idk-evm","ti,am4372","ti,am43";
|
||||
|
||||
v24_0d: fixed-regulator-v24_0d {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V24_0D";
|
||||
regulator-min-microvolt = <24000000>;
|
||||
regulator-max-microvolt = <24000000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
v3_3d: fixed-regulator-v3_3d {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V3_3D";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&v24_0d>;
|
||||
};
|
||||
|
||||
vdd_corereg: fixed-regulator-vdd_corereg {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_COREREG";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&v24_0d>;
|
||||
};
|
||||
|
||||
vdd_core: fixed-regulator-vdd_core {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VDD_CORE";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&vdd_corereg>;
|
||||
};
|
||||
|
||||
v1_8dreg: fixed-regulator-v1_8dreg{
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V1_8DREG";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&v24_0d>;
|
||||
};
|
||||
|
||||
v1_8d: fixed-regulator-v1_8d{
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V1_8D";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&v1_8dreg>;
|
||||
};
|
||||
|
||||
v1_5dreg: fixed-regulator-v1_5dreg{
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V1_5DREG";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&v24_0d>;
|
||||
};
|
||||
|
||||
v1_5d: fixed-regulator-v1_5d{
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "V1_5D";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
vin-supply = <&v1_5dreg>;
|
||||
};
|
||||
|
||||
gpio_keys: gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&gpio_keys_pins_default>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@0 {
|
||||
label = "power-button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
gpio_keys_pins_default: gpio_keys_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1b8 (PIN_INPUT | MUX_MODE7) /* cam0_field.gpio4_2 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins_default: i2c0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins_sleep: i2c0_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x18c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins_default: i2c1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins_sleep: i2c1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
|
||||
0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins_default: pinmux_mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
0x1f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
0x1f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
0x1f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
0x1fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins_sleep: pinmux_mmc1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x100 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x104 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x1f0 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x1f4 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x1f8 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x1fc (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x160 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins_default: backlight_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x164 (PIN_OUTPUT | MUX_MODE0) /* ecap0_in_pwm0_out.ecap0_in_pwm0_out */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
|
||||
0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
qspi_pins_default: qspi_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x7c (PIN_OUTPUT_PULLUP | MUX_MODE3) /* gpmc_csn0.qspi_csn */
|
||||
0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
|
||||
0x90 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
|
||||
0x94 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
|
||||
0x98 (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_wen.qspi_d2 */
|
||||
0x9c (PIN_INPUT_PULLUP | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
|
||||
>;
|
||||
};
|
||||
|
||||
qspi_pins_sleep: qspi_pins_sleep{
|
||||
pinctrl-single,pins = <
|
||||
0x7c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x88 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x98 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c0_pins_default>;
|
||||
pinctrl-1 = <&i2c0_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c256";
|
||||
pagesize = <64>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&i2c1_pins_default>;
|
||||
pinctrl-1 = <&i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps: tps62362@60 {
|
||||
compatible = "ti,tps62362";
|
||||
regulator-name = "VDD_MPU";
|
||||
regulator-min-microvolt = <950000>;
|
||||
regulator-max-microvolt = <1330000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
ti,vsel0-state-high;
|
||||
ti,vsel1-state-high;
|
||||
vin-supply = <&v3_3d>;
|
||||
};
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins_default>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio4 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
pinctrl-1 = <&mmc1_pins_sleep>;
|
||||
vmmc-supply = <&v3_3d>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&qspi_pins_default>;
|
||||
pinctrl-1 = <&qspi_pins_sleep>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/*
|
||||
* MTD partition table. The ROM checks the first 512KiB for a
|
||||
* valid file to boot(XIP).
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.U-BOOT-SPL_OS";
|
||||
reg = <0x00100000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.U_BOOT_ENV";
|
||||
reg = <0x00110000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.U-BOOT-ENV.backup";
|
||||
reg = <0x00120000 0x00010000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.KERNEL";
|
||||
reg = <0x00130000 0x0800000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.FILESYSTEM";
|
||||
reg = <0x00930000 0x36D0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <0>;
|
||||
phy-mode = "rgmii";
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu {
|
||||
cpu0-supply = <&tps>;
|
||||
};
|
||||
701
sys/gnu/dts/arm/am437x-sk-evm.dts
Normal file
701
sys/gnu/dts/arm/am437x-sk-evm.dts
Normal file
@ -0,0 +1,701 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* AM437x SK EVM */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
#include <dt-bindings/pinctrl/am43xx.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM437x SK EVM";
|
||||
compatible = "ti,am437x-sk-evm","ti,am4372","ti,am43";
|
||||
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "ti,da830-evm-audio";
|
||||
ti,model = "AM437x-SK-EVM";
|
||||
ti,audio-codec = <&tlv320aic3106>;
|
||||
ti,mcasp-controller = <&mcasp1>;
|
||||
ti,codec-clock-rate = <24000000>;
|
||||
ti,audio-routing =
|
||||
"Headphone Jack", "HPLOUT",
|
||||
"Headphone Jack", "HPROUT";
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&matrix_keypad_pins>;
|
||||
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <1500>;
|
||||
|
||||
row-gpios = <&gpio5 5 GPIO_ACTIVE_HIGH /* Bank5, pin5 */
|
||||
&gpio5 6 GPIO_ACTIVE_HIGH>; /* Bank5, pin6 */
|
||||
|
||||
col-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH /* Bank5, pin13 */
|
||||
&gpio5 4 GPIO_ACTIVE_HIGH>; /* Bank5, pin4 */
|
||||
|
||||
linux,keymap = <
|
||||
MATRIX_KEY(0, 0, KEY_DOWN)
|
||||
MATRIX_KEY(0, 1, KEY_RIGHT)
|
||||
MATRIX_KEY(1, 0, KEY_LEFT)
|
||||
MATRIX_KEY(1, 1, KEY_UP)
|
||||
>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins>;
|
||||
|
||||
led@0 {
|
||||
label = "am437x-sk:red:heartbeat";
|
||||
gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 0 */
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "am437x-sk:green:mmc1";
|
||||
gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 1 */
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "am437x-sk:blue:cpu0";
|
||||
gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 2 */
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "am437x-sk:blue:usr3";
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; /* Bank 5, pin 3 */
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "newhaven,nhd-4.3-480272ef-atxl", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins>;
|
||||
|
||||
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <9000000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <2>;
|
||||
hback-porch = <2>;
|
||||
hsync-len = <41>;
|
||||
vfront-porch = <2>;
|
||||
vback-porch = <2>;
|
||||
vsync-len = <10>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&am43xx_pinmux {
|
||||
matrix_keypad_pins: matrix_keypad_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x24c (PIN_OUTPUT | MUX_MODE7) /* gpio5_13.gpio5_13 */
|
||||
0x250 (PIN_OUTPUT | MUX_MODE7) /* spi4_sclk.gpio5_4 */
|
||||
0x254 (PIN_INPUT | MUX_MODE7) /* spi4_d0.gpio5_5 */
|
||||
0x258 (PIN_INPUT | MUX_MODE7) /* spi4_d1.gpio5_5 */
|
||||
>;
|
||||
};
|
||||
|
||||
leds_pins: leds_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x228 (PIN_OUTPUT | MUX_MODE7) /* uart3_rxd.gpio5_2 */
|
||||
0x22c (PIN_OUTPUT | MUX_MODE7) /* uart3_txd.gpio5_3 */
|
||||
0x230 (PIN_OUTPUT | MUX_MODE7) /* uart3_ctsn.gpio5_0 */
|
||||
0x234 (PIN_OUTPUT | MUX_MODE7) /* uart3_rtsn.gpio5_1 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
|
||||
0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x0f0 (PIN_INPUT | MUX_MODE0) /* mmc0_dat3.mmc0_dat3 */
|
||||
0x0f4 (PIN_INPUT | MUX_MODE0) /* mmc0_dat2.mmc0_dat2 */
|
||||
0x0f8 (PIN_INPUT | MUX_MODE0) /* mmc0_dat1.mmc0_dat1 */
|
||||
0x0fc (PIN_INPUT | MUX_MODE0) /* mmc0_dat0.mmc0_dat0 */
|
||||
0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
|
||||
0x104 (PIN_INPUT | MUX_MODE0) /* mmc0_cmd.mmc0_cmd */
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 (PIN_OUTPUT | MUX_MODE0) /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out */
|
||||
>;
|
||||
};
|
||||
|
||||
edt_ft5306_ts_pins: edt_ft5306_ts_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x74 (PIN_INPUT | MUX_MODE7) /* gpmc_wpn.gpio0_31 */
|
||||
0x78 (PIN_OUTPUT | MUX_MODE7) /* gpmc_be1n.gpio1_28 */
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_default: vpfe0_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_hd mode 0*/
|
||||
0x1b4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_vd mode 0*/
|
||||
0x1b8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_field mode 0*/
|
||||
0x1bc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_wen mode 0*/
|
||||
0x1c0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_pclk mode 0*/
|
||||
0x1c4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data8 mode 0*/
|
||||
0x1c8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data9 mode 0*/
|
||||
0x208 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data0 mode 0*/
|
||||
0x20c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data1 mode 0*/
|
||||
0x210 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data2 mode 0*/
|
||||
0x214 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data3 mode 0*/
|
||||
0x218 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data4 mode 0*/
|
||||
0x21c (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data5 mode 0*/
|
||||
0x220 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data6 mode 0*/
|
||||
0x224 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam0_data7 mode 0*/
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe0_pins_sleep: vpfe0_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1b0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1b4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1b8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1bc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1c0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1c4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1c8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x208 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x20c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x210 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x214 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x218 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x21c (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x220 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x224 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x12c (PIN_OUTPUT | MUX_MODE2) /* mii1_txclk.rmii1_tclk */
|
||||
0x114 (PIN_OUTPUT | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
|
||||
0x128 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
|
||||
0x124 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
|
||||
0x120 (PIN_OUTPUT | MUX_MODE2) /* mii1_txd0.rgmii1_td2 */
|
||||
0x11c (PIN_OUTPUT | MUX_MODE2) /* mii1_txd1.rgmii1_td3 */
|
||||
0x130 (PIN_INPUT | MUX_MODE2) /* mii1_rxclk.rmii1_rclk */
|
||||
0x118 (PIN_INPUT | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
|
||||
0x140 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
|
||||
0x13c (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
|
||||
0x138 (PIN_INPUT | MUX_MODE2) /* mii1_rxd0.rgmii1_rd2 */
|
||||
0x134 (PIN_INPUT | MUX_MODE2) /* mii1_rxd1.rgmii1_rd3 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x58 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
|
||||
0x40 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
|
||||
0x54 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
|
||||
0x50 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
|
||||
0x4c (PIN_OUTPUT | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
|
||||
0x48 (PIN_OUTPUT | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
|
||||
0x5c (PIN_INPUT | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
|
||||
0x44 (PIN_INPUT | MUX_MODE2) /* gpmc_a1.rgmii2_rtcl */
|
||||
0x6c (PIN_INPUT | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
|
||||
0x68 (PIN_INPUT | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
|
||||
0x64 (PIN_INPUT | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
|
||||
0x60 (PIN_INPUT | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
|
||||
/* Slave 2 reset value */
|
||||
0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
dss_pins: dss_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x020 (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 8 -> DSS DATA 23 */
|
||||
0x024 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x028 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x02c (PIN_OUTPUT | MUX_MODE1)
|
||||
0x030 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x034 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x038 (PIN_OUTPUT | MUX_MODE1)
|
||||
0x03c (PIN_OUTPUT | MUX_MODE1) /* gpmc ad 15 -> DSS DATA 16 */
|
||||
0x0a0 (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 0 */
|
||||
0x0a4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0a8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0ac (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0b0 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0b4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0b8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0bc (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0c0 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0c4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0c8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0cc (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0d0 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0d4 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0d8 (PIN_OUTPUT | MUX_MODE0)
|
||||
0x0dc (PIN_OUTPUT | MUX_MODE0) /* DSS DATA 15 */
|
||||
0x0e0 (PIN_OUTPUT | MUX_MODE0) /* DSS VSYNC */
|
||||
0x0e4 (PIN_OUTPUT | MUX_MODE0) /* DSS HSYNC */
|
||||
0x0e8 (PIN_OUTPUT | MUX_MODE0) /* DSS PCLK */
|
||||
0x0ec (PIN_OUTPUT | MUX_MODE0) /* DSS AC BIAS EN */
|
||||
|
||||
>;
|
||||
};
|
||||
|
||||
qspi_pins: qspi_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x7c (PIN_OUTPUT | MUX_MODE3) /* gpmc_csn0.qspi_csn */
|
||||
0x88 (PIN_OUTPUT | MUX_MODE2) /* gpmc_csn3.qspi_clk */
|
||||
0x90 (PIN_INPUT | MUX_MODE3) /* gpmc_advn_ale.qspi_d0 */
|
||||
0x94 (PIN_INPUT | MUX_MODE3) /* gpmc_oen_ren.qspi_d1 */
|
||||
0x98 (PIN_INPUT | MUX_MODE3) /* gpmc_wen.qspi_d2 */
|
||||
0x9c (PIN_INPUT | MUX_MODE3) /* gpmc_be0n_cle.qspi_d3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcasp1_pins: mcasp1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */
|
||||
0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins: lcd_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpcm_ad7.gpio1_7 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x2c0 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
usb2_pins: usb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x2c4 (PIN_OUTPUT | MUX_MODE0) /* usb0_drvvbus.usb0_drvvbus */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps@24 {
|
||||
compatible = "ti,tps65218";
|
||||
reg = <0x24>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
dcdc1: regulator-dcdc1 {
|
||||
compatible = "ti,tps65218-dcdc1";
|
||||
/* VDD_CORE limits min of OPP50 and max of OPP100 */
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2: regulator-dcdc2 {
|
||||
compatible = "ti,tps65218-dcdc2";
|
||||
/* VDD_MPU limits min of OPP50 and max of OPP_NITRO */
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1378000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3: regulator-dcdc3 {
|
||||
compatible = "ti,tps65218-dcdc3";
|
||||
regulator-name = "vdds_ddr";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc4: regulator-dcdc4 {
|
||||
compatible = "ti,tps65218-dcdc4";
|
||||
regulator-name = "v3_3d";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
ldo1: regulator-ldo1 {
|
||||
compatible = "ti,tps65218-ldo1";
|
||||
regulator-name = "v1_8d";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
power-button {
|
||||
compatible = "ti,tps65218-pwrbutton";
|
||||
status = "okay";
|
||||
interrupts = <3 IRQ_TYPE_EDGE_BOTH>;
|
||||
};
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c256";
|
||||
pagesize = <64>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
edt-ft5306@38 {
|
||||
status = "okay";
|
||||
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&edt_ft5306_ts_pins>;
|
||||
|
||||
reg = <0x38>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <31 0>;
|
||||
|
||||
wake-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
touchscreen-size-x = <480>;
|
||||
touchscreen-size-y = <272>;
|
||||
};
|
||||
|
||||
tlv320aic3106: tlv320aic3106@1b {
|
||||
compatible = "ti,tlv320aic3106";
|
||||
reg = <0x1b>;
|
||||
status = "okay";
|
||||
|
||||
/* Regulators */
|
||||
AVDD-supply = <&dcdc4>;
|
||||
IOVDD-supply = <&dcdc4>;
|
||||
DRVDD-supply = <&dcdc4>;
|
||||
DVDD-supply = <&ldo1>;
|
||||
};
|
||||
|
||||
lis331dlh@18 {
|
||||
compatible = "st,lis331dlh";
|
||||
reg = <0x18>;
|
||||
status = "okay";
|
||||
|
||||
Vdd-supply = <&dcdc4>;
|
||||
Vdd_IO-supply = <&dcdc4>;
|
||||
interrupts-extended = <&gpio1 6 0>, <&gpio2 1 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio5 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
|
||||
vmmc-supply = <&dcdc4>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb2_pins>;
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* MTD partition table.
|
||||
* The ROM checks the first 512KiB
|
||||
* for a valid file to boot(XIP).
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.U-BOOT-SPL_OS";
|
||||
reg = <0x00100000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.U_BOOT_ENV";
|
||||
reg = <0x00110000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.U-BOOT-ENV.backup";
|
||||
reg = <0x00120000 0x00010000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.KERNEL";
|
||||
reg = <0x00130000 0x0800000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.FILESYSTEM";
|
||||
reg = <0x00930000 0x36D0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
dual_emac = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <4>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <5>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mcasp1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcasp1_pins>;
|
||||
|
||||
status = "okay";
|
||||
|
||||
op-mode = <0>;
|
||||
tdm-slots = <2>;
|
||||
serial-dir = <
|
||||
0 0 1 2
|
||||
>;
|
||||
|
||||
tx-num-evt = <1>;
|
||||
rx-num-evt = <1>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&rtc {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdt {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpu {
|
||||
cpu0-supply = <&dcdc2>;
|
||||
};
|
||||
|
||||
&vpfe0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe0_pins_default>;
|
||||
pinctrl-1 = <&vpfe0_pins_sleep>;
|
||||
|
||||
/* Camera port */
|
||||
port {
|
||||
vpfe0_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
689
sys/gnu/dts/arm/am43x-epos-evm.dts
Normal file
689
sys/gnu/dts/arm/am43x-epos-evm.dts
Normal file
@ -0,0 +1,689 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/* AM43x EPOS EVM */
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "am4372.dtsi"
|
||||
#include <dt-bindings/pinctrl/am43xx.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/pwm/pwm.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM43x EPOS EVM";
|
||||
compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43";
|
||||
|
||||
aliases {
|
||||
display0 = &lcd0;
|
||||
};
|
||||
|
||||
vmmcsd_fixed: fixedregulator-sd {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmcsd_fixed";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
lcd0: display {
|
||||
compatible = "osddisplays,osd057T0559-34ts", "panel-dpi";
|
||||
label = "lcd";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_pins>;
|
||||
|
||||
/*
|
||||
* SelLCDorHDMI, LOW to select HDMI. This is not really the
|
||||
* panel's enable GPIO, but we don't have HDMI driver support nor
|
||||
* support to switch between two displays, so using this gpio as
|
||||
* panel's enable should be safe.
|
||||
*/
|
||||
enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
panel-timing {
|
||||
clock-frequency = <33000000>;
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
hfront-porch = <210>;
|
||||
hback-porch = <16>;
|
||||
hsync-len = <30>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <22>;
|
||||
vsync-len = <13>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
|
||||
port {
|
||||
lcd_in: endpoint {
|
||||
remote-endpoint = <&dpi_out>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
am43xx_pinmux: pinmux@44e10800 {
|
||||
cpsw_default: cpsw_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
|
||||
0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */
|
||||
0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
|
||||
0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_sleep: cpsw_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 reset value */
|
||||
0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_default: davinci_mdio_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
|
||||
0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_sleep: davinci_mdio_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO reset value */
|
||||
0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
i2c0_pins: pinmux_i2c0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */
|
||||
0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
nand_flash_x8: nand_flash_x8 {
|
||||
pinctrl-single,pins = <
|
||||
0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
|
||||
0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
|
||||
0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
|
||||
0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
|
||||
0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
|
||||
0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
|
||||
0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
|
||||
0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
|
||||
0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
|
||||
0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
|
||||
0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
|
||||
0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
|
||||
0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
|
||||
0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
|
||||
0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
|
||||
0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
|
||||
>;
|
||||
};
|
||||
|
||||
ecap0_pins: backlight_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c2_pins: pinmux_i2c2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */
|
||||
0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
spi0_pins: pinmux_spi0_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */
|
||||
0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */
|
||||
0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */
|
||||
0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
spi1_pins: pinmux_spi1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */
|
||||
0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */
|
||||
0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */
|
||||
0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins: pinmux_mmc1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */
|
||||
>;
|
||||
};
|
||||
|
||||
qspi1_default: qspi1_default {
|
||||
pinctrl-single,pins = <
|
||||
0x7c (PIN_INPUT_PULLUP | MUX_MODE3)
|
||||
0x88 (PIN_INPUT_PULLUP | MUX_MODE2)
|
||||
0x90 (PIN_INPUT_PULLUP | MUX_MODE3)
|
||||
0x94 (PIN_INPUT_PULLUP | MUX_MODE3)
|
||||
0x98 (PIN_INPUT_PULLUP | MUX_MODE3)
|
||||
0x9c (PIN_INPUT_PULLUP | MUX_MODE3)
|
||||
>;
|
||||
};
|
||||
|
||||
pixcir_ts_pins: pixcir_ts_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */
|
||||
>;
|
||||
};
|
||||
|
||||
hdq_pins: pinmux_hdq_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */
|
||||
>;
|
||||
};
|
||||
|
||||
dss_pins: dss_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */
|
||||
0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1)
|
||||
0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */
|
||||
0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */
|
||||
0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0)
|
||||
0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */
|
||||
0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */
|
||||
0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */
|
||||
0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */
|
||||
0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */
|
||||
>;
|
||||
};
|
||||
|
||||
lcd_pins: lcd_pins {
|
||||
pinctrl-single,pins = <
|
||||
/* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */
|
||||
0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe1_pins_default: vpfe1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */
|
||||
0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */
|
||||
0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */
|
||||
0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */
|
||||
0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */
|
||||
0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */
|
||||
0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */
|
||||
0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */
|
||||
0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */
|
||||
0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */
|
||||
0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */
|
||||
0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */
|
||||
0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */
|
||||
>;
|
||||
};
|
||||
|
||||
vpfe1_pins_sleep: vpfe1_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
matrix_keypad: matrix_keypad@0 {
|
||||
compatible = "gpio-matrix-keypad";
|
||||
debounce-delay-ms = <5>;
|
||||
col-scan-delay-us = <2>;
|
||||
|
||||
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
|
||||
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
|
||||
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
|
||||
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
|
||||
|
||||
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
|
||||
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
|
||||
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
|
||||
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
|
||||
|
||||
linux,keymap = <0x00000201 /* P1 */
|
||||
0x01000204 /* P4 */
|
||||
0x02000207 /* P7 */
|
||||
0x0300020a /* NUMERIC_STAR */
|
||||
0x00010202 /* P2 */
|
||||
0x01010205 /* P5 */
|
||||
0x02010208 /* P8 */
|
||||
0x03010200 /* P0 */
|
||||
0x00020203 /* P3 */
|
||||
0x01020206 /* P6 */
|
||||
0x02020209 /* P9 */
|
||||
0x0302020b /* NUMERIC_POUND */
|
||||
0x00030067 /* UP */
|
||||
0x0103006a /* RIGHT */
|
||||
0x0203006c /* DOWN */
|
||||
0x03030069>; /* LEFT */
|
||||
};
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
|
||||
brightness-levels = <0 51 53 56 62 75 101 152 255>;
|
||||
default-brightness-level = <8>;
|
||||
};
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
vmmc-supply = <&vmmcsd_fixed>;
|
||||
bus-width = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins>;
|
||||
cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_default>;
|
||||
pinctrl-1 = <&cpsw_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_default>;
|
||||
pinctrl-1 = <&davinci_mdio_sleep>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <16>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rmii";
|
||||
};
|
||||
|
||||
&phy_sel {
|
||||
rmii-clock-ext;
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps65218: tps65218@24 {
|
||||
reg = <0x24>;
|
||||
compatible = "ti,tps65218";
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */
|
||||
interrupt-parent = <&gic>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
dcdc1: regulator-dcdc1 {
|
||||
compatible = "ti,tps65218-dcdc1";
|
||||
regulator-name = "vdd_core";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1144000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc2: regulator-dcdc2 {
|
||||
compatible = "ti,tps65218-dcdc2";
|
||||
regulator-name = "vdd_mpu";
|
||||
regulator-min-microvolt = <912000>;
|
||||
regulator-max-microvolt = <1378000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc3: regulator-dcdc3 {
|
||||
compatible = "ti,tps65218-dcdc3";
|
||||
regulator-name = "vdcdc3";
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
dcdc5: regulator-dcdc5 {
|
||||
compatible = "ti,tps65218-dcdc5";
|
||||
regulator-name = "v1_0bat";
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <1000000>;
|
||||
};
|
||||
|
||||
dcdc6: regulator-dcdc6 {
|
||||
compatible = "ti,tps65218-dcdc6";
|
||||
regulator-name = "v1_8bat";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
};
|
||||
|
||||
ldo1: regulator-ldo1 {
|
||||
compatible = "ti,tps65218-ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
|
||||
at24@50 {
|
||||
compatible = "at24,24c256";
|
||||
pagesize = <64>;
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
pixcir_ts@5c {
|
||||
compatible = "pixcir,pixcir_tangoc";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pixcir_ts_pins>;
|
||||
reg = <0x5c>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <17 0>;
|
||||
|
||||
attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>;
|
||||
|
||||
touchscreen-size-x = <1024>;
|
||||
touchscreen-size-y = <600>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c2_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&elm {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpmc {
|
||||
status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&nand_flash_x8>;
|
||||
ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */
|
||||
nand@0,0 {
|
||||
reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
|
||||
ti,nand-ecc-opt = "bch16";
|
||||
ti,elm-id = <&elm>;
|
||||
nand-bus-width = <8>;
|
||||
gpmc,device-width = <1>;
|
||||
gpmc,sync-clk-ps = <0>;
|
||||
gpmc,cs-on-ns = <0>;
|
||||
gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
|
||||
gpmc,cs-wr-off-ns = <40>;
|
||||
gpmc,adv-on-ns = <0>; /* cs-on-ns */
|
||||
gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
|
||||
gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
|
||||
gpmc,we-on-ns = <0>; /* cs-on-ns */
|
||||
gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
|
||||
gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
|
||||
gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
|
||||
gpmc,access-ns = <30>; /* tCEA + 4*/
|
||||
gpmc,rd-cycle-ns = <40>;
|
||||
gpmc,wr-cycle-ns = <40>;
|
||||
gpmc,wait-pin = <0>;
|
||||
gpmc,bus-turnaround-ns = <0>;
|
||||
gpmc,cycle2cycle-delay-ns = <0>;
|
||||
gpmc,clk-activation-ns = <0>;
|
||||
gpmc,wait-monitoring-ns = <0>;
|
||||
gpmc,wr-access-ns = <40>;
|
||||
gpmc,wr-data-mux-bus-ns = <0>;
|
||||
/* MTD partition table */
|
||||
/* All SPL-* partitions are sized to minimal length
|
||||
* which can be independently programmable. For
|
||||
* NAND flash this is equal to size of erase-block */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "NAND.SPL";
|
||||
reg = <0x00000000 0x00040000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "NAND.SPL.backup1";
|
||||
reg = <0x00040000 0x00040000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "NAND.SPL.backup2";
|
||||
reg = <0x00080000 0x00040000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "NAND.SPL.backup3";
|
||||
reg = <0x000C0000 0x00040000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "NAND.u-boot-spl-os";
|
||||
reg = <0x00100000 0x00080000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "NAND.u-boot";
|
||||
reg = <0x00180000 0x00100000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "NAND.u-boot-env";
|
||||
reg = <0x00280000 0x00040000>;
|
||||
};
|
||||
partition@7 {
|
||||
label = "NAND.u-boot-env.backup1";
|
||||
reg = <0x002C0000 0x00040000>;
|
||||
};
|
||||
partition@8 {
|
||||
label = "NAND.kernel";
|
||||
reg = <0x00300000 0x00700000>;
|
||||
};
|
||||
partition@9 {
|
||||
label = "NAND.file-system";
|
||||
reg = <0x00a00000 0x1f600000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&epwmss0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tscadc {
|
||||
status = "okay";
|
||||
|
||||
adc {
|
||||
ti,adc-channels = <0 1 2 3 4 5 6 7>;
|
||||
};
|
||||
};
|
||||
|
||||
&ecap0 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ecap0_pins>;
|
||||
};
|
||||
|
||||
&spi0 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&spi1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "peripheral";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "host";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&qspi1_default>;
|
||||
|
||||
spi-max-frequency = <48000000>;
|
||||
m25p80@0 {
|
||||
compatible = "mx66l51235l";
|
||||
spi-max-frequency = <48000000>;
|
||||
reg = <0>;
|
||||
spi-cpol;
|
||||
spi-cpha;
|
||||
spi-tx-bus-width = <1>;
|
||||
spi-rx-bus-width = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* MTD partition table.
|
||||
* The ROM checks the first 512KiB
|
||||
* for a valid file to boot(XIP).
|
||||
*/
|
||||
partition@0 {
|
||||
label = "QSPI.U_BOOT";
|
||||
reg = <0x00000000 0x000080000>;
|
||||
};
|
||||
partition@1 {
|
||||
label = "QSPI.U_BOOT.backup";
|
||||
reg = <0x00080000 0x00080000>;
|
||||
};
|
||||
partition@2 {
|
||||
label = "QSPI.U-BOOT-SPL_OS";
|
||||
reg = <0x00100000 0x00010000>;
|
||||
};
|
||||
partition@3 {
|
||||
label = "QSPI.U_BOOT_ENV";
|
||||
reg = <0x00110000 0x00010000>;
|
||||
};
|
||||
partition@4 {
|
||||
label = "QSPI.U-BOOT-ENV.backup";
|
||||
reg = <0x00120000 0x00010000>;
|
||||
};
|
||||
partition@5 {
|
||||
label = "QSPI.KERNEL";
|
||||
reg = <0x00130000 0x0800000>;
|
||||
};
|
||||
partition@6 {
|
||||
label = "QSPI.FILESYSTEM";
|
||||
reg = <0x00930000 0x36D0000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&hdq {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&hdq_pins>;
|
||||
};
|
||||
|
||||
&dss {
|
||||
status = "ok";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&dss_pins>;
|
||||
|
||||
port {
|
||||
dpi_out: endpoint@0 {
|
||||
remote-endpoint = <&lcd_in>;
|
||||
data-lines = <24>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vpfe1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&vpfe1_pins_default>;
|
||||
pinctrl-1 = <&vpfe1_pins_sleep>;
|
||||
|
||||
port {
|
||||
vpfe1_ep: endpoint {
|
||||
/* remote-endpoint = <&sensor>; add once we have it */
|
||||
ti,am437x-vpfe-interface = <0>;
|
||||
bus-width = <8>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
757
sys/gnu/dts/arm/am43xx-clocks.dtsi
Normal file
757
sys/gnu/dts/arm/am43xx-clocks.dtsi
Normal file
@ -0,0 +1,757 @@
|
||||
/*
|
||||
* Device Tree Source for AM43xx clock data
|
||||
*
|
||||
* Copyright (C) 2013 Texas Instruments, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
&scrm_clocks {
|
||||
sys_clkin_ck: sys_clkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysboot_freq_sel_ck>, <&crystal_freq_sel_ck>;
|
||||
ti,bit-shift = <31>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
crystal_freq_sel_ck: crystal_freq_sel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <29>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
sysboot_freq_sel_ck: sysboot_freq_sel_ck@44e10040 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>;
|
||||
ti,bit-shift = <22>;
|
||||
reg = <0x0040>;
|
||||
};
|
||||
|
||||
adc_tsc_fck: adc_tsc_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan0_fck: dcan0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dcan1_fck: dcan1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp0_fck: mcasp0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
mcasp1_fck: mcasp1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex0_fck: smartreflex0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
smartreflex1_fck: smartreflex1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
sha0_fck: sha0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
aes0_fck: aes0_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
ehrpwm0_tbclk: ehrpwm0_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <0>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm1_tbclk: ehrpwm1_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm2_tbclk: ehrpwm2_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <2>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm3_tbclk: ehrpwm3_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <4>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm4_tbclk: ehrpwm4_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <5>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
|
||||
ehrpwm5_tbclk: ehrpwm5_tbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <6>;
|
||||
reg = <0x0664>;
|
||||
};
|
||||
};
|
||||
&prcm_clocks {
|
||||
clk_32768_ck: clk_32768_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
clk_rc32k_ck: clk_rc32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
virt_19200000_ck: virt_19200000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
virt_24000000_ck: virt_24000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
virt_25000000_ck: virt_25000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
virt_26000000_ck: virt_26000000_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
tclkin_ck: tclkin_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
dpll_core_ck: dpll_core_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-core-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2d20>, <0x2d24>, <0x2d2c>;
|
||||
};
|
||||
|
||||
dpll_core_x2_ck: dpll_core_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_core_ck>;
|
||||
};
|
||||
|
||||
dpll_core_m4_ck: dpll_core_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d38>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_m5_ck: dpll_core_m5_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d3c>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_core_m6_ck: dpll_core_m6_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_core_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d40>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_mpu_ck: dpll_mpu_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2d60>, <0x2d64>, <0x2d6c>;
|
||||
};
|
||||
|
||||
dpll_mpu_m2_ck: dpll_mpu_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_mpu_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2d70>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_ddr_ck: dpll_ddr_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2da0>, <0x2da4>, <0x2dac>;
|
||||
};
|
||||
|
||||
dpll_ddr_m2_ck: dpll_ddr_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2db0>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_disp_ck: dpll_disp_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2e20>, <0x2e24>, <0x2e2c>;
|
||||
};
|
||||
|
||||
dpll_disp_m2_ck: dpll_disp_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_disp_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e30>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_per_ck: dpll_per_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-j-type-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2de0>, <0x2de4>, <0x2dec>;
|
||||
};
|
||||
|
||||
dpll_per_m2_ck: dpll_per_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,max-div = <127>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2df0>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
dpll_per_m2_div4_ck: dpll_per_m2_div4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <4>;
|
||||
};
|
||||
|
||||
clk_24mhz: clk_24mhz {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
clkdiv32k_ck: clkdiv32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&clk_24mhz>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <732>;
|
||||
};
|
||||
|
||||
clkdiv32k_ick: clkdiv32k_ick {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a38>;
|
||||
};
|
||||
|
||||
sysclk_div: sysclk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
pruss_ocp_gclk: pruss_ocp_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x4248>;
|
||||
};
|
||||
|
||||
clk_32k_tpm_ck: clk_32k_tpm_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
timer1_fck: timer1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4200>;
|
||||
};
|
||||
|
||||
timer2_fck: timer2_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4204>;
|
||||
};
|
||||
|
||||
timer3_fck: timer3_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4208>;
|
||||
};
|
||||
|
||||
timer4_fck: timer4_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x420c>;
|
||||
};
|
||||
|
||||
timer5_fck: timer5_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4210>;
|
||||
};
|
||||
|
||||
timer6_fck: timer6_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4214>;
|
||||
};
|
||||
|
||||
timer7_fck: timer7_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4218>;
|
||||
};
|
||||
|
||||
wdt1_fck: wdt1_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x422c>;
|
||||
};
|
||||
|
||||
l3_gclk: l3_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
dpll_core_m4_div2_ck: dpll_core_m4_div2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sysclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
l4hs_gclk: l4hs_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l3s_gclk: l3s_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
l4ls_gclk: l4ls_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m4_div2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_125mhz_gclk: cpsw_125mhz_gclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
cpsw_cpts_rft_clk: cpsw_cpts_rft_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_core_m5_ck>, <&dpll_disp_m2_ck>;
|
||||
reg = <0x4238>;
|
||||
};
|
||||
|
||||
clk_32k_mosc_ck: clk_32k_mosc_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>, <&clk_32k_mosc_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4240>;
|
||||
};
|
||||
|
||||
gpio0_dbclk: gpio0_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&gpio0_dbclk_mux_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2b68>;
|
||||
};
|
||||
|
||||
gpio1_dbclk: gpio1_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c78>;
|
||||
};
|
||||
|
||||
gpio2_dbclk: gpio2_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c80>;
|
||||
};
|
||||
|
||||
gpio3_dbclk: gpio3_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c88>;
|
||||
};
|
||||
|
||||
gpio4_dbclk: gpio4_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c90>;
|
||||
};
|
||||
|
||||
gpio5_dbclk: gpio5_dbclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&clkdiv32k_ick>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8c98>;
|
||||
};
|
||||
|
||||
mmc_clk: mmc_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
gfx_fclk_clksel_ck: gfx_fclk_clksel_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&sysclk_div>, <&dpll_per_m2_ck>;
|
||||
ti,bit-shift = <1>;
|
||||
reg = <0x423c>;
|
||||
};
|
||||
|
||||
gfx_fck_div_ck: gfx_fck_div_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&gfx_fclk_clksel_ck>;
|
||||
reg = <0x423c>;
|
||||
ti,max-div = <2>;
|
||||
};
|
||||
|
||||
disp_clk: disp_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>;
|
||||
reg = <0x4244>;
|
||||
ti,set-rate-parent;
|
||||
};
|
||||
|
||||
dpll_extdev_ck: dpll_extdev_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-clock";
|
||||
clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
|
||||
reg = <0x2e60>, <0x2e64>, <0x2e6c>;
|
||||
};
|
||||
|
||||
dpll_extdev_m2_ck: dpll_extdev_m2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_extdev_ck>;
|
||||
ti,max-div = <127>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e70>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
mux_synctimer32k_ck: mux_synctimer32k_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>, <&clkdiv32k_ick>;
|
||||
reg = <0x4230>;
|
||||
};
|
||||
|
||||
synctimer_32kclk: synctimer_32kclk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&mux_synctimer32k_ck>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a30>;
|
||||
};
|
||||
|
||||
timer8_fck: timer8_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x421c>;
|
||||
};
|
||||
|
||||
timer9_fck: timer9_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4220>;
|
||||
};
|
||||
|
||||
timer10_fck: timer10_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4224>;
|
||||
};
|
||||
|
||||
timer11_fck: timer11_fck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4228>;
|
||||
};
|
||||
|
||||
cpsw_50m_clkdiv: cpsw_50m_clkdiv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_core_m5_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <1>;
|
||||
};
|
||||
|
||||
cpsw_5m_clkdiv: cpsw_5m_clkdiv {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&cpsw_50m_clkdiv>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <10>;
|
||||
};
|
||||
|
||||
dpll_ddr_x2_ck: dpll_ddr_x2_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,am3-dpll-x2-clock";
|
||||
clocks = <&dpll_ddr_ck>;
|
||||
};
|
||||
|
||||
dpll_ddr_m4_ck: dpll_ddr_m4_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&dpll_ddr_x2_ck>;
|
||||
ti,max-div = <31>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2db8>;
|
||||
ti,index-starts-at-one;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dpll_per_clkdcoldo: dpll_per_clkdcoldo {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,fixed-factor-clock";
|
||||
clocks = <&dpll_per_ck>;
|
||||
ti,clock-mult = <1>;
|
||||
ti,clock-div = <1>;
|
||||
ti,autoidle-shift = <8>;
|
||||
reg = <0x2e14>;
|
||||
ti,invert-autoidle-bit;
|
||||
};
|
||||
|
||||
dll_aging_clk_div: dll_aging_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,divider-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
reg = <0x4250>;
|
||||
ti,dividers = <8>, <16>, <32>;
|
||||
};
|
||||
|
||||
div_core_25m_ck: div_core_25m_ck {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sysclk_div>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <8>;
|
||||
};
|
||||
|
||||
func_12m_clk: func_12m_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&dpll_per_m2_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <16>;
|
||||
};
|
||||
|
||||
vtp_clk_div: vtp_clk_div {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clocks = <&sys_clkin_ck>;
|
||||
clock-mult = <1>;
|
||||
clock-div = <2>;
|
||||
};
|
||||
|
||||
usbphy_32khz_clkmux: usbphy_32khz_clkmux {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,mux-clock";
|
||||
clocks = <&clk_32768_ck>, <&clk_32k_tpm_ck>;
|
||||
reg = <0x4260>;
|
||||
};
|
||||
|
||||
usb_phy0_always_on_clk32k: usb_phy0_always_on_clk32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&usbphy_32khz_clkmux>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a40>;
|
||||
};
|
||||
|
||||
usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&usbphy_32khz_clkmux>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x2a48>;
|
||||
};
|
||||
|
||||
usb_otg_ss0_refclk960m: usb_otg_ss0_refclk960m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_clkdcoldo>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8a60>;
|
||||
};
|
||||
|
||||
usb_otg_ss1_refclk960m: usb_otg_ss1_refclk960m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "ti,gate-clock";
|
||||
clocks = <&dpll_per_clkdcoldo>;
|
||||
ti,bit-shift = <8>;
|
||||
reg = <0x8a68>;
|
||||
};
|
||||
};
|
||||
562
sys/gnu/dts/arm/am57xx-beagle-x15.dts
Normal file
562
sys/gnu/dts/arm/am57xx-beagle-x15.dts
Normal file
@ -0,0 +1,562 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
/dts-v1/;
|
||||
|
||||
#include "dra74x.dtsi"
|
||||
#include <dt-bindings/clk/ti-dra7-atl.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
model = "TI AM5728 BeagleBoard-X15";
|
||||
compatible = "ti,am572x-beagle-x15", "ti,am5728", "ti,dra742", "ti,dra74", "ti,dra7";
|
||||
|
||||
aliases {
|
||||
rtc0 = &mcp_rtc;
|
||||
rtc1 = &tps659038_rtc;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x80000000 0x80000000>;
|
||||
};
|
||||
|
||||
vdd_3v3: fixedregulator-vdd_3v3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vdd_3v3";
|
||||
vin-supply = <®en1>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
vtt_fixed: fixedregulator-vtt {
|
||||
/* TPS51200 */
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vtt_fixed";
|
||||
vin-supply = <&smps3_reg>;
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
enable-active-high;
|
||||
gpio = <&gpio7 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&leds_pins_default>;
|
||||
|
||||
led@0 {
|
||||
label = "beagle-x15:usr0";
|
||||
gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@1 {
|
||||
label = "beagle-x15:usr1";
|
||||
gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@2 {
|
||||
label = "beagle-x15:usr2";
|
||||
gpios = <&gpio7 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
led@3 {
|
||||
label = "beagle-x15:usr3";
|
||||
gpios = <&gpio7 15 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "ide-disk";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_fan: gpio_fan {
|
||||
/* Based on 5v 500mA AFB02505HHB */
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&tps659038_gpio 1 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = <0 0>,
|
||||
<13000 1>;
|
||||
};
|
||||
|
||||
extcon_usb1: extcon_usb1 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 25 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb1_pins>;
|
||||
};
|
||||
|
||||
extcon_usb2: extcon_usb2 {
|
||||
compatible = "linux,extcon-usb-gpio";
|
||||
id-gpio = <&gpio7 24 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&extcon_usb2_pins>;
|
||||
};
|
||||
};
|
||||
|
||||
&dra7_pmx_core {
|
||||
leds_pins_default: leds_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3a8 (PIN_OUTPUT | MUX_MODE14) /* spi1_d1.gpio7_8 */
|
||||
0x3ac (PIN_OUTPUT | MUX_MODE14) /* spi1_d0.gpio7_9 */
|
||||
0x3c0 (PIN_OUTPUT | MUX_MODE14) /* spi2_sclk.gpio7_14 */
|
||||
0x3c4 (PIN_OUTPUT | MUX_MODE14) /* spi2_d1.gpio7_15 */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c1_pins_default: i2c1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x400 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_sda.sda */
|
||||
0x404 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c1_scl.scl */
|
||||
>;
|
||||
};
|
||||
|
||||
i2c3_pins_default: i2c3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x2a4 (PIN_INPUT| MUX_MODE10) /* mcasp1_aclkx.i2c3_sda */
|
||||
0x2a8 (PIN_INPUT| MUX_MODE10) /* mcasp1_fsx.i2c3_scl */
|
||||
>;
|
||||
};
|
||||
|
||||
uart3_pins_default: uart3_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd.rxd */
|
||||
0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd.txd */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc1_pins_default: mmc1_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x36c (PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
|
||||
0x354 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
|
||||
0x358 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
|
||||
0x35c (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
|
||||
0x360 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
|
||||
0x364 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
|
||||
0x368 (PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
|
||||
>;
|
||||
};
|
||||
|
||||
mmc2_pins_default: mmc2_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x9c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
|
||||
0xb0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
|
||||
0xa0 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
|
||||
0xa4 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
|
||||
0xa8 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
|
||||
0xac (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
|
||||
0x8c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
|
||||
0x90 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
|
||||
0x94 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
|
||||
0x98 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
|
||||
>;
|
||||
};
|
||||
|
||||
cpsw_pins_default: cpsw_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tclk */
|
||||
0x254 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_tctl */
|
||||
0x258 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td3 */
|
||||
0x25c (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td2 */
|
||||
0x260 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td1 */
|
||||
0x264 (PIN_OUTPUT | MUX_MODE0) /* rgmii1_td0 */
|
||||
0x268 (PIN_INPUT | MUX_MODE0) /* rgmii1_rclk */
|
||||
0x26c (PIN_INPUT | MUX_MODE0) /* rgmii1_rctl */
|
||||
0x270 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd3 */
|
||||
0x274 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd2 */
|
||||
0x278 (PIN_INPUT | MUX_MODE0) /* rgmii1_rd1 */
|
||||
0x27c (PIN_INPUT | MUX_MODE0) /* rgmii1_rd0 */
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tclk */
|
||||
0x19c (PIN_OUTPUT | MUX_MODE3) /* rgmii2_tctl */
|
||||
0x1a0 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td3 */
|
||||
0x1a4 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td2 */
|
||||
0x1a8 (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td1 */
|
||||
0x1ac (PIN_OUTPUT | MUX_MODE3) /* rgmii2_td0 */
|
||||
0x1b0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rclk */
|
||||
0x1b4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rctl */
|
||||
0x1b8 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd3 */
|
||||
0x1bc (PIN_INPUT | MUX_MODE3) /* rgmii2_rd2 */
|
||||
0x1c0 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd1 */
|
||||
0x1c4 (PIN_INPUT | MUX_MODE3) /* rgmii2_rd0 */
|
||||
>;
|
||||
|
||||
};
|
||||
|
||||
cpsw_pins_sleep: cpsw_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
/* Slave 1 */
|
||||
0x250 (PIN_INPUT | MUX_MODE15)
|
||||
0x254 (PIN_INPUT | MUX_MODE15)
|
||||
0x258 (PIN_INPUT | MUX_MODE15)
|
||||
0x25c (PIN_INPUT | MUX_MODE15)
|
||||
0x260 (PIN_INPUT | MUX_MODE15)
|
||||
0x264 (PIN_INPUT | MUX_MODE15)
|
||||
0x268 (PIN_INPUT | MUX_MODE15)
|
||||
0x26c (PIN_INPUT | MUX_MODE15)
|
||||
0x270 (PIN_INPUT | MUX_MODE15)
|
||||
0x274 (PIN_INPUT | MUX_MODE15)
|
||||
0x278 (PIN_INPUT | MUX_MODE15)
|
||||
0x27c (PIN_INPUT | MUX_MODE15)
|
||||
|
||||
/* Slave 2 */
|
||||
0x198 (PIN_INPUT | MUX_MODE15)
|
||||
0x19c (PIN_INPUT | MUX_MODE15)
|
||||
0x1a0 (PIN_INPUT | MUX_MODE15)
|
||||
0x1a4 (PIN_INPUT | MUX_MODE15)
|
||||
0x1a8 (PIN_INPUT | MUX_MODE15)
|
||||
0x1ac (PIN_INPUT | MUX_MODE15)
|
||||
0x1b0 (PIN_INPUT | MUX_MODE15)
|
||||
0x1b4 (PIN_INPUT | MUX_MODE15)
|
||||
0x1b8 (PIN_INPUT | MUX_MODE15)
|
||||
0x1bc (PIN_INPUT | MUX_MODE15)
|
||||
0x1c0 (PIN_INPUT | MUX_MODE15)
|
||||
0x1c4 (PIN_INPUT | MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_pins_default: davinci_mdio_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
/* MDIO */
|
||||
0x23c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_mclk */
|
||||
0x240 (PIN_INPUT_PULLUP | MUX_MODE0) /* mdio_d */
|
||||
>;
|
||||
};
|
||||
|
||||
davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
|
||||
pinctrl-single,pins = <
|
||||
0x23c (PIN_INPUT | MUX_MODE15)
|
||||
0x240 (PIN_INPUT | MUX_MODE15)
|
||||
>;
|
||||
};
|
||||
|
||||
tps659038_pins_default: tps659038_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x418 (PIN_INPUT_PULLUP | MUX_MODE14) /* wakeup0.gpio1_0 */
|
||||
>;
|
||||
};
|
||||
|
||||
tmp102_pins_default: tmp102_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x3C8 (PIN_INPUT_PULLUP | MUX_MODE14) /* spi2_d0.gpio7_16 */
|
||||
>;
|
||||
};
|
||||
|
||||
mcp79410_pins_default: mcp79410_pins_default {
|
||||
pinctrl-single,pins = <
|
||||
0x424 (PIN_INPUT_PULLUP | MUX_MODE1) /* wakeup3.sys_nirq1 */
|
||||
>;
|
||||
};
|
||||
|
||||
usb1_pins: pinmux_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x280 (PIN_INPUT_SLEW | MUX_MODE0) /* usb1_drvvbus */
|
||||
>;
|
||||
};
|
||||
|
||||
extcon_usb1_pins: extcon_usb1_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3ec (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_rtsn.gpio7_25 */
|
||||
>;
|
||||
};
|
||||
|
||||
extcon_usb2_pins: extcon_usb2_pins {
|
||||
pinctrl-single,pins = <
|
||||
0x3e8 (PIN_INPUT_PULLUP | MUX_MODE14) /* uart1_ctsn.gpio7_24 */
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c1_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
tps659038: tps659038@58 {
|
||||
compatible = "ti,tps659038";
|
||||
reg = <0x58>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tps659038_pins_default>;
|
||||
|
||||
#interrupt-cells = <2>;
|
||||
interrupt-controller;
|
||||
|
||||
ti,system-power-controller;
|
||||
|
||||
tps659038_pmic {
|
||||
compatible = "ti,tps659038-pmic";
|
||||
|
||||
regulators {
|
||||
smps12_reg: smps12 {
|
||||
/* VDD_MPU */
|
||||
regulator-name = "smps12";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1250000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps3_reg: smps3 {
|
||||
/* VDD_DDR */
|
||||
regulator-name = "smps3";
|
||||
regulator-min-microvolt = <1350000>;
|
||||
regulator-max-microvolt = <1350000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps45_reg: smps45 {
|
||||
/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
|
||||
regulator-name = "smps45";
|
||||
regulator-min-microvolt = < 850000>;
|
||||
regulator-max-microvolt = <1150000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
smps6_reg: smps6 {
|
||||
/* VDD_CORE */
|
||||
regulator-name = "smps6";
|
||||
regulator-min-microvolt = <850000>;
|
||||
regulator-max-microvolt = <1030000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* SMPS7 unused */
|
||||
|
||||
smps8_reg: smps8 {
|
||||
/* VDD_1V8 */
|
||||
regulator-name = "smps8";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
/* SMPS9 unused */
|
||||
|
||||
ldo1_reg: ldo1 {
|
||||
/* VDD_SD */
|
||||
regulator-name = "ldo1";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo2_reg: ldo2 {
|
||||
/* VDD_SHV5 */
|
||||
regulator-name = "ldo2";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo3_reg: ldo3 {
|
||||
/* VDDA_1V8_PHY */
|
||||
regulator-name = "ldo3";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldo9_reg: ldo9 {
|
||||
/* VDD_RTC */
|
||||
regulator-name = "ldo9";
|
||||
regulator-min-microvolt = <1050000>;
|
||||
regulator-max-microvolt = <1050000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldoln_reg: ldoln {
|
||||
/* VDDA_1V8_PLL */
|
||||
regulator-name = "ldoln";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
ldousb_reg: ldousb {
|
||||
/* VDDA_3V_USB: VDDA_USBHS33 */
|
||||
regulator-name = "ldousb";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
regen1: regen1 {
|
||||
/* VDD_3V3_ON */
|
||||
regulator-name = "regen1";
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
tps659038_rtc: tps659038_rtc {
|
||||
compatible = "ti,palmas-rtc";
|
||||
interrupt-parent = <&tps659038>;
|
||||
interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
tps659038_pwr_button: tps659038_pwr_button {
|
||||
compatible = "ti,palmas-pwrbutton";
|
||||
interrupt-parent = <&tps659038>;
|
||||
interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
|
||||
wakeup-source;
|
||||
ti,palmas-long-press-seconds = <12>;
|
||||
};
|
||||
|
||||
tps659038_gpio: tps659038_gpio {
|
||||
compatible = "ti,palmas-gpio";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
tmp102: tmp102@48 {
|
||||
compatible = "ti,tmp102";
|
||||
reg = <0x48>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&tmp102_pins_default>;
|
||||
interrupt-parent = <&gpio7>;
|
||||
interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c3_pins_default>;
|
||||
clock-frequency = <400000>;
|
||||
|
||||
mcp_rtc: rtc@6f {
|
||||
compatible = "microchip,mcp7941x";
|
||||
reg = <0x6f>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_LOW>; /* IRQ_SYS_1N */
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mcp79410_pins_default>;
|
||||
|
||||
vcc-supply = <&vdd_3v3>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
&gpio7 {
|
||||
ti,no-reset-on-init;
|
||||
ti,no-idle-on-init;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
cpu0-supply = <&smps12_reg>;
|
||||
voltage-tolerance = <1>;
|
||||
};
|
||||
|
||||
&uart3 {
|
||||
status = "okay";
|
||||
interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&dra7_pmx_core 0x248>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart3_pins_default>;
|
||||
};
|
||||
|
||||
&mac {
|
||||
status = "okay";
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&cpsw_pins_default>;
|
||||
pinctrl-1 = <&cpsw_pins_sleep>;
|
||||
dual_emac;
|
||||
};
|
||||
|
||||
&cpsw_emac0 {
|
||||
phy_id = <&davinci_mdio>, <1>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <1>;
|
||||
};
|
||||
|
||||
&cpsw_emac1 {
|
||||
phy_id = <&davinci_mdio>, <2>;
|
||||
phy-mode = "rgmii";
|
||||
dual_emac_res_vlan = <2>;
|
||||
};
|
||||
|
||||
&davinci_mdio {
|
||||
pinctrl-names = "default", "sleep";
|
||||
pinctrl-0 = <&davinci_mdio_pins_default>;
|
||||
pinctrl-1 = <&davinci_mdio_pins_sleep>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc1_pins_default>;
|
||||
|
||||
vmmc-supply = <&ldo1_reg>;
|
||||
vmmc_aux-supply = <&vdd_3v3>;
|
||||
pbias-supply = <&pbias_mmc_reg>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&gpio6 27 0>; /* gpio 219 */
|
||||
};
|
||||
|
||||
&mmc2 {
|
||||
status = "okay";
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mmc2_pins_default>;
|
||||
|
||||
vmmc-supply = <&vdd_3v3>;
|
||||
bus-width = <8>;
|
||||
ti,non-removable;
|
||||
cap-mmc-dual-data-rate;
|
||||
};
|
||||
|
||||
&sata {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb2_phy1 {
|
||||
phy-supply = <&ldousb_reg>;
|
||||
};
|
||||
|
||||
&usb1 {
|
||||
dr_mode = "host";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&usb1_pins>;
|
||||
};
|
||||
|
||||
&omap_dwc3_1 {
|
||||
extcon = <&extcon_usb1>;
|
||||
};
|
||||
|
||||
&omap_dwc3_2 {
|
||||
extcon = <&extcon_usb2>;
|
||||
};
|
||||
|
||||
&usb2 {
|
||||
dr_mode = "peripheral";
|
||||
};
|
||||
412
sys/gnu/dts/arm/arm-realview-pb1176.dts
Normal file
412
sys/gnu/dts/arm/arm-realview-pb1176.dts
Normal file
@ -0,0 +1,412 @@
|
||||
/*
|
||||
* Copyright 2014 Linaro Ltd
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "ARM RealView PB1176";
|
||||
compatible = "arm,realview-pb1176";
|
||||
|
||||
chosen { };
|
||||
|
||||
aliases {
|
||||
serial0 = &pb1176_serial0;
|
||||
serial1 = &pb1176_serial1;
|
||||
serial2 = &pb1176_serial2;
|
||||
serial3 = &pb1176_serial3;
|
||||
serial4 = &fpga_serial;
|
||||
};
|
||||
|
||||
memory {
|
||||
/* 128 MiB memory @ 0x0 */
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
/* The voltage to the MMC card is hardwired at 3.3V */
|
||||
vmmc: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vmmc";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
};
|
||||
|
||||
xtal24mhz: xtal24mhz@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
timclk: timclk@1M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <24>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
mclk: mclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
kmiclk: kmiclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
sspclk: sspclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
uartclk: uartclk@24M {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-factor-clock";
|
||||
clock-div = <1>;
|
||||
clock-mult = <1>;
|
||||
clocks = <&xtal24mhz>;
|
||||
};
|
||||
|
||||
/* FIXME: this actually hangs off the PLL clocks */
|
||||
pclk: pclk@0 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,realview-pb1176-soc", "simple-bus";
|
||||
regmap = <&syscon>;
|
||||
ranges;
|
||||
|
||||
syscon: syscon@10000000 {
|
||||
compatible = "arm,realview-pb1176-syscon", "syscon";
|
||||
reg = <0x10000000 0x1000>;
|
||||
|
||||
led@08.0 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x01>;
|
||||
label = "versatile:0";
|
||||
linux,default-trigger = "heartbeat";
|
||||
default-state = "on";
|
||||
};
|
||||
led@08.1 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x02>;
|
||||
label = "versatile:1";
|
||||
linux,default-trigger = "mmc0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.2 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x04>;
|
||||
label = "versatile:2";
|
||||
linux,default-trigger = "cpu0";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.3 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x08>;
|
||||
label = "versatile:3";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.4 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x10>;
|
||||
label = "versatile:4";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.5 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x20>;
|
||||
label = "versatile:5";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.6 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x40>;
|
||||
label = "versatile:6";
|
||||
default-state = "off";
|
||||
};
|
||||
led@08.7 {
|
||||
compatible = "register-bit-led";
|
||||
offset = <0x08>;
|
||||
mask = <0x80>;
|
||||
label = "versatile:7";
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
/* Primary DevChip GIC synthesized with the CPU */
|
||||
intc_dc1176: interrupt-controller@10120000 {
|
||||
compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x10121000 0x1000>,
|
||||
<0x10120000 0x100>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,l220-cache";
|
||||
reg = <0x10110000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
/*
|
||||
* Override default cache size, sets and
|
||||
* associativity as these may be erroneously set
|
||||
* up by boot loader(s).
|
||||
*/
|
||||
arm,override-auxreg;
|
||||
cache-size = <131072>; // 128kB
|
||||
cache-sets = <512>;
|
||||
cache-line-size = <32>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,arm1176-pmu";
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer01: timer@10104000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10104000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>, <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
timer23: timer@10105000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x10105000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
arm,sp804-has-irq = <1>;
|
||||
clocks = <&timclk>, <&timclk>, <&pclk>;
|
||||
clock-names = "timer1", "timer2", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_rtc: rtc@10108000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10108000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_gpio0: gpio@1010a000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x1010a000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_ssp: ssp@1010b000 {
|
||||
compatible = "arm,pl022", "arm,primecell";
|
||||
reg = <0x1010b000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sspclk>, <&pclk>;
|
||||
clock-names = "SSPCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial0: serial@1010c000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010c000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial1: serial@1010d000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010d000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial2: serial@1010e000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010e000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
pb1176_serial3: serial@1010f000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x1010f000 0x1000>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
/* These peripherals are inside the FPGA rather than the DevChip */
|
||||
fpga {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
|
||||
fpga_mci: mmcsd@10005000 {
|
||||
compatible = "arm,pl18x", "arm,primecell";
|
||||
reg = <0x10005000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 1 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<0 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
/* Due to frequent FIFO overruns, use just 500 kHz */
|
||||
max-frequency = <500000>;
|
||||
bus-width = <4>;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
clocks = <&mclk>, <&pclk>;
|
||||
clock-names = "mclk", "apb_pclk";
|
||||
vmmc-supply = <&vmmc>;
|
||||
cd-gpios = <&fpga_gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&fpga_gpio1 1 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
fpga_kmi0: kmi@10006000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10006000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_kmi1: kmi@10007000 {
|
||||
compatible = "arm,pl050", "arm,primecell";
|
||||
reg = <0x10007000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&kmiclk>, <&pclk>;
|
||||
clock-names = "KMIREFCLK", "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_charlcd: charlcd@10008000 {
|
||||
compatible = "arm,versatile-lcd";
|
||||
reg = <0x10008000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_serial: serial@10009000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x10009000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&uartclk>, <&pclk>;
|
||||
clock-names = "uartclk", "apb_pclk";
|
||||
};
|
||||
|
||||
/* This GIC on the board is cascaded off the DevChip GIC */
|
||||
intc_fpga1176: interrupt-controller@10040000 {
|
||||
compatible = "arm,arm1176jzf-devchip-gic", "arm,arm11mp-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <1>;
|
||||
interrupt-controller;
|
||||
reg = <0x10041000 0x1000>,
|
||||
<0x10040000 0x100>;
|
||||
interrupt-parent = <&intc_dc1176>;
|
||||
interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
fpga_gpio0: gpio@10014000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10014000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_gpio1: gpio@10015000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x10015000 0x1000>;
|
||||
gpio-controller;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
fpga_rtc: rtc@10017000 {
|
||||
compatible = "arm,pl031", "arm,primecell";
|
||||
reg = <0x10017000 0x1000>;
|
||||
interrupt-parent = <&intc_fpga1176>;
|
||||
interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&pclk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
|
||||
|
||||
};
|
||||
};
|
||||
239
sys/gnu/dts/arm/armada-370-db.dts
Normal file
239
sys/gnu/dts/arm/armada-370-db.dts
Normal file
@ -0,0 +1,239 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 370 evaluation board
|
||||
* (DB-88F6710-BP-DDR3)
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 Evaluation Board";
|
||||
compatible = "marvell,a370-db", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
audio_codec: audio-codec@4a {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "cirrus,cs42l51";
|
||||
reg = <0x4a>;
|
||||
};
|
||||
};
|
||||
|
||||
audio-controller@30000 {
|
||||
pinctrl-0 = <&i2s_pins2>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
pinctrl-0 = <&sdio_pins1>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* This device is disabled by default, because
|
||||
* using the SD card connector requires
|
||||
* changing the default CON40 connector
|
||||
* "DB-88F6710_MPP_2xRGMII_DEVICE_Jumper" to a
|
||||
* different connector
|
||||
* "DB-88F6710_MPP_RGMII_SD_Jumper".
|
||||
*/
|
||||
status = "disabled";
|
||||
/* No CD or WP GPIOs */
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
pinctrl-0 = <&spi0_pins2>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "mx25l25635e";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
* both standard PCIe slots and mini-PCIe
|
||||
* slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "simple-audio-card";
|
||||
simple-audio-card,name = "Armada 370 DB Audio";
|
||||
simple-audio-card,mclk-fs = <256>;
|
||||
simple-audio-card,widgets =
|
||||
"Headphone", "Out Jack",
|
||||
"Line", "In Jack";
|
||||
simple-audio-card,routing =
|
||||
"Out Jack", "HPL",
|
||||
"Out Jack", "HPR",
|
||||
"AIN1L", "In Jack",
|
||||
"AIN1L", "In Jack";
|
||||
status = "okay";
|
||||
|
||||
simple-audio-card,dai-link@0 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&audio_controller 0>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&audio_codec>;
|
||||
};
|
||||
};
|
||||
|
||||
simple-audio-card,dai-link@1 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&audio_controller 1>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&spdif_out>;
|
||||
};
|
||||
};
|
||||
|
||||
simple-audio-card,dai-link@2 {
|
||||
format = "i2s";
|
||||
cpu {
|
||||
sound-dai = <&audio_controller 1>;
|
||||
};
|
||||
|
||||
codec {
|
||||
sound-dai = <&spdif_in>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spdif_out: spdif-out {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "linux,spdif-dit";
|
||||
};
|
||||
|
||||
spdif_in: spdif-in {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "linux,spdif-dir";
|
||||
};
|
||||
};
|
||||
206
sys/gnu/dts/arm/armada-370-mirabox.dts
Normal file
206
sys/gnu/dts/arm/armada-370-mirabox.dts
Normal file
@ -0,0 +1,206 @@
|
||||
/*
|
||||
* Device Tree file for Globalscale Mirabox
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Globalscale Mirabox";
|
||||
compatible = "globalscale,mirabox", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected on the PCB to a USB 3.0 XHCI controller */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
timer@20300 {
|
||||
clock-frequency = <600000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpio_leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pwr_led_pin &stat_led_pins>;
|
||||
|
||||
green_pwr_led {
|
||||
label = "mirabox:green:pwr";
|
||||
gpios = <&gpio1 31 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
blue_stat_led {
|
||||
label = "mirabox:blue:stat";
|
||||
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
green_stat_led {
|
||||
label = "mirabox:green:stat";
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
pinctrl-0 = <&sdio_pins3>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
/*
|
||||
* No CD or WP GPIOs: SDIO interface used for
|
||||
* Wifi/Bluetooth chip
|
||||
*/
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
pca9505: pca9505@25 {
|
||||
compatible = "nxp,pca9505";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x25>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x400000>;
|
||||
};
|
||||
partition@400000 {
|
||||
label = "Linux";
|
||||
reg = <0x400000 0x400000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x800000 0x3f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pwr_led_pin: pwr-led-pin {
|
||||
marvell,pins = "mpp63";
|
||||
marvell,function = "gpo";
|
||||
};
|
||||
|
||||
stat_led_pins: stat-led-pins {
|
||||
marvell,pins = "mpp64", "mpp65";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
293
sys/gnu/dts/arm/armada-370-netgear-rn102.dts
Normal file
293
sys/gnu/dts/arm/armada-370-netgear-rn102.dts
Normal file
@ -0,0 +1,293 @@
|
||||
/*
|
||||
* Device Tree file for NETGEAR ReadyNAS 102
|
||||
*
|
||||
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NETGEAR ReadyNAS 102";
|
||||
compatible = "netgear,readynas-102", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Connected to Marvell 88SE9170 SATA controller */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected to FL1009 USB 3.0 controller */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* eSATA interface */
|
||||
sata@a0000 {
|
||||
nr-ports = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
isl12057: isl12057@68 {
|
||||
compatible = "isil,isl12057";
|
||||
reg = <0x68>;
|
||||
isil,irq2-can-wakeup-machine;
|
||||
};
|
||||
|
||||
g762: g762@3e {
|
||||
compatible = "gmt,g762";
|
||||
reg = <0x3e>;
|
||||
clocks = <&g762_clk>; /* input clock */
|
||||
fan_gear_mode = <0>;
|
||||
fan_startv = <1>;
|
||||
pwm_polarity = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
/* Use Hardware BCH ECC */
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0000000 0x180000>; /* 1.5MB */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x180000 0x20000>; /* 128KB */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "uImage";
|
||||
reg = <0x0200000 0x600000>; /* 6MB */
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "minirootfs";
|
||||
reg = <0x0800000 0x400000>; /* 4MB */
|
||||
};
|
||||
|
||||
/* Last MB is for the BBT, i.e. not writable */
|
||||
partition@c00000 {
|
||||
label = "ubifs";
|
||||
reg = <0x0c00000 0x7400000>; /* 116MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <8192>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&power_led_pin
|
||||
&sata1_led_pin
|
||||
&sata2_led_pin
|
||||
&backup_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
blue-power-led {
|
||||
label = "rn102:blue:pwr";
|
||||
gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
blue-sata1-led {
|
||||
label = "rn102:blue:sata1";
|
||||
gpios = <&gpio0 15 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
blue-sata2-led {
|
||||
label = "rn102:blue:sata2";
|
||||
gpios = <&gpio0 14 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
blue-backup-led {
|
||||
label = "rn102:blue:backup";
|
||||
gpios = <&gpio1 24 GPIO_ACTIVE_LOW>;
|
||||
default-state = "on";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&power_button_pin
|
||||
&reset_button_pin
|
||||
&backup_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-button {
|
||||
label = "Power Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reset-button {
|
||||
label = "Reset Button";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
backup-button {
|
||||
label = "Backup Button";
|
||||
linux,code = <KEY_COPY>;
|
||||
gpios = <&gpio1 26 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
pinctrl-0 = <&poweroff>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpio0 8 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
power_led_pin: power-led-pin {
|
||||
marvell,pins = "mpp57";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_led_pin: sata1-led-pin {
|
||||
marvell,pins = "mpp15";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_led_pin: sata2-led-pin {
|
||||
marvell,pins = "mpp14";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
backup_led_pin: backup-led-pin {
|
||||
marvell,pins = "mpp56";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
backup_button_pin: backup-button-pin {
|
||||
marvell,pins = "mpp58";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
power_button_pin: power-button-pin {
|
||||
marvell,pins = "mpp62";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
reset_button_pin: reset-button-pin {
|
||||
marvell,pins = "mpp6";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
poweroff: poweroff {
|
||||
marvell,pins = "mpp8";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
305
sys/gnu/dts/arm/armada-370-netgear-rn104.dts
Normal file
305
sys/gnu/dts/arm/armada-370-netgear-rn104.dts
Normal file
@ -0,0 +1,305 @@
|
||||
/*
|
||||
* Device Tree file for NETGEAR ReadyNAS 104
|
||||
*
|
||||
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NETGEAR ReadyNAS 104";
|
||||
compatible = "netgear,readynas-104", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Connected to FL1009 USB 3.0 controller */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected to Marvell 88SE9215 SATA controller */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
clock-frequency = <100000>;
|
||||
status = "okay";
|
||||
|
||||
isl12057: isl12057@68 {
|
||||
compatible = "isil,isl12057";
|
||||
reg = <0x68>;
|
||||
isil,irq2-can-wakeup-machine;
|
||||
};
|
||||
|
||||
g762: g762@3e {
|
||||
compatible = "gmt,g762";
|
||||
reg = <0x3e>;
|
||||
clocks = <&g762_clk>; /* input clock */
|
||||
fan_gear_mode = <0>;
|
||||
fan_startv = <1>;
|
||||
pwm_polarity = <0>;
|
||||
};
|
||||
|
||||
pca9554: pca9554@23 {
|
||||
compatible = "nxp,pca9554";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0x23>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
/* Use Hardware BCH ECC */
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0000000 0x180000>; /* 1.5MB */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x180000 0x20000>; /* 128KB */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "uImage";
|
||||
reg = <0x0200000 0x600000>; /* 6MB */
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "minirootfs";
|
||||
reg = <0x0800000 0x400000>; /* 4MB */
|
||||
};
|
||||
|
||||
/* Last MB is for the BBT, i.e. not writable */
|
||||
partition@c00000 {
|
||||
label = "ubifs";
|
||||
reg = <0x0c00000 0x7400000>; /* 116MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <8192>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&backup_led_pin &power_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
blue-backup-led {
|
||||
label = "rn104:blue:backup";
|
||||
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
blue-power-led {
|
||||
label = "rn104:blue:pwr";
|
||||
gpios = <&gpio2 0 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "keep";
|
||||
};
|
||||
|
||||
blue-sata1-led {
|
||||
label = "rn104:blue:sata1";
|
||||
gpios = <&pca9554 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
blue-sata2-led {
|
||||
label = "rn104:blue:sata2";
|
||||
gpios = <&pca9554 1 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
blue-sata3-led {
|
||||
label = "rn104:blue:sata3";
|
||||
gpios = <&pca9554 2 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
blue-sata4-led {
|
||||
label = "rn104:blue:sata4";
|
||||
gpios = <&pca9554 3 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&backup_button_pin
|
||||
&power_button_pin
|
||||
&reset_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
backup-button {
|
||||
label = "Backup Button";
|
||||
linux,code = <KEY_COPY>;
|
||||
gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
power-button {
|
||||
label = "Power Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reset-button {
|
||||
label = "Reset Button";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
pinctrl-0 = <&poweroff>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpio1 28 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
poweroff: poweroff {
|
||||
marvell,pins = "mpp60";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
backup_button_pin: backup-button-pin {
|
||||
marvell,pins = "mpp52";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
power_button_pin: power-button-pin {
|
||||
marvell,pins = "mpp62";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
backup_led_pin: backup-led-pin {
|
||||
marvell,pins = "mpp63";
|
||||
marvell,function = "gpo";
|
||||
};
|
||||
|
||||
power_led_pin: power-led-pin {
|
||||
marvell,pins = "mpp64";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
reset_button_pin: reset-button-pin {
|
||||
marvell,pins = "mpp65";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
249
sys/gnu/dts/arm/armada-370-rd.dts
Normal file
249
sys/gnu/dts/arm/armada-370-rd.dts
Normal file
@ -0,0 +1,249 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 370 Reference Design board
|
||||
* (RD-88F6710-A1)
|
||||
*
|
||||
* Copied from arch/arm/boot/dts/armada-370-db.dts
|
||||
*
|
||||
* Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the default
|
||||
* 0xd0000000). The 0xf1000000 is the default used by the recent,
|
||||
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
|
||||
* boards were delivered with an older version of the bootloader that
|
||||
* left internal registers mapped at 0xd0000000. If you are in this
|
||||
* situation, you should either update your bootloader (preferred
|
||||
* solution) or the below Device Tree should be adjusted.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 Reference Design";
|
||||
compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy-mode = "rgmii-id";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
pinctrl-0 = <&sdio_pins1>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
/* No CD or WP GPIOs */
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
button@1 {
|
||||
label = "Software Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = <0 0 3000 1>;
|
||||
pinctrl-0 = <&fan_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
gpio_leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
|
||||
sw_led {
|
||||
label = "370rd:green:sw";
|
||||
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x800000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Linux";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
dsa@0 {
|
||||
compatible = "marvell,dsa";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <0>;
|
||||
|
||||
dsa,ethernet = <ð1>;
|
||||
dsa,mii-bus = <&mdio>;
|
||||
|
||||
switch@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "cpu";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
fan_pins: fan-pins {
|
||||
marvell,pins = "mpp8";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
led_pins: led-pins {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
349
sys/gnu/dts/arm/armada-370-synology-ds213j.dts
Normal file
349
sys/gnu/dts/arm/armada-370-synology-ds213j.dts
Normal file
@ -0,0 +1,349 @@
|
||||
/*
|
||||
* Device Tree file for Synology DS213j
|
||||
*
|
||||
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
|
||||
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
|
||||
* bootloaders provided by Marvell. It is used in recent versions of
|
||||
* DSM software provided by Synology. Nonetheless, some earlier boards
|
||||
* were delivered with an older version of u-boot that left internal
|
||||
* registers mapped at 0xd0000000. If you have such a device you will
|
||||
* not be able to directly boot a kernel based on this Device Tree. In
|
||||
* that case, the preferred solution is to update your bootloader (e.g.
|
||||
* by upgrading to latest version of DSM, or building a new one and
|
||||
* installing it from u-boot prompt) or adjust the Devive Tree
|
||||
* (s/0xf1000000/0xd0000000/ in 'ranges' below).
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-370.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Synology DS213j";
|
||||
compatible = "synology,ds213j", "marvell,armada370",
|
||||
"marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x20000000>; /* 512 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
|
||||
/* RTC provided by Seiko S-35390A I2C RTC chip below */
|
||||
rtc@10300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
|
||||
/*
|
||||
* Warning!
|
||||
*
|
||||
* Synology u-boot uses its compiled-in environment
|
||||
* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
|
||||
* modified environment at a sensible location. So,
|
||||
* if you do a 'saveenv' under u-boot, your modified
|
||||
* environment will be saved at 1MB after the start
|
||||
* of the flash, i.e. in the middle of the uImage.
|
||||
* For that reason, it is strongly advised not to
|
||||
* change the default environment, unless you know
|
||||
* what you are doing.
|
||||
*/
|
||||
partition@00000000 { /* u-boot */
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x000c0000>; /* 768KB */
|
||||
};
|
||||
|
||||
partition@000c0000 { /* uImage */
|
||||
label = "zImage";
|
||||
reg = <0x000c0000 0x002d0000>; /* 2880KB */
|
||||
};
|
||||
|
||||
partition@00390000 { /* uInitramfs */
|
||||
label = "rd.gz";
|
||||
reg = <0x00390000 0x00440000>; /* 4250KB */
|
||||
};
|
||||
|
||||
partition@007d0000 { /* MAC address and serial number */
|
||||
label = "vendor";
|
||||
reg = <0x007d0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007e0000 {
|
||||
label = "RedBoot config";
|
||||
reg = <0x007e0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007f0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x007f0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
/* Main device RTC chip */
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "sii,s35390a";
|
||||
reg = <0x30>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Connected to a header on device's PCB */
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected to a TI MSP430F2111 for power control */
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
poweroff@12100 {
|
||||
compatible = "synology,power-off";
|
||||
reg = <0x12100 0x100>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
/* rear USB port, near reset button */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* rear USB port, near RJ45 port */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-fan-32-38 {
|
||||
status = "okay";
|
||||
compatible = "gpio-fan";
|
||||
pinctrl-0 = <&fan_ctrl_low_pin &fan_ctrl_mid_pin
|
||||
&fan_ctrl_high_pin &fan_alarm_pin>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpio1 31 GPIO_ACTIVE_HIGH
|
||||
&gpio2 0 GPIO_ACTIVE_HIGH
|
||||
&gpio2 1 GPIO_ACTIVE_HIGH>;
|
||||
alarm-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
1000 1
|
||||
1150 2
|
||||
1350 4
|
||||
1500 3
|
||||
1650 5
|
||||
1750 6
|
||||
1900 7 >;
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&disk1_led_pin
|
||||
&disk2_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
disk1-led-amber {
|
||||
label = "synology:amber:disk1";
|
||||
gpios = <&gpio0 31 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
|
||||
disk2-led-amber {
|
||||
label = "synology:amber:disk2";
|
||||
gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
sata1_regulator: sata1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "SATA1 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <2000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata2_regulator: sata2-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "SATA2 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <4000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 30 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
disk1_led_pin: disk1-led-pin {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
disk2_led_pin: disk2-led-pin {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_pwr_pin: sata1-pwr-pin {
|
||||
marvell,pins = "mpp37";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_pwr_pin: sata2-pwr-pin {
|
||||
marvell,pins = "mpp62";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_pres_pin: sata1-pres-pin {
|
||||
marvell,pins = "mpp60";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_pres_pin: sata2-pres-pin {
|
||||
marvell,pins = "mpp48";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit0_pin: syno-id-bit0-pin {
|
||||
marvell,pins = "mpp55";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit1_pin: syno-id-bit1-pin {
|
||||
marvell,pins = "mpp56";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit2_pin: syno-id-bit2-pin {
|
||||
marvell,pins = "mpp57";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit3_pin: syno-id-bit3-pin {
|
||||
marvell,pins = "mpp58";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
fan_ctrl_low_pin: fan-ctrl-low-pin {
|
||||
marvell,pins = "mpp65";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
fan_ctrl_mid_pin: fan-ctrl-mid-pin {
|
||||
marvell,pins = "mpp64";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
fan_ctrl_high_pin: fan-ctrl-high-pin {
|
||||
marvell,pins = "mpp63";
|
||||
marvell,function = "gpo";
|
||||
};
|
||||
|
||||
fan_alarm_pin: fan-alarm-pin {
|
||||
marvell,pins = "mpp38";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
332
sys/gnu/dts/arm/armada-370-xp.dtsi
Normal file
332
sys/gnu/dts/arm/armada-370-xp.dtsi
Normal file
@ -0,0 +1,332 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 370 and Armada XP SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* This file contains the definitions that are common to the Armada
|
||||
* 370 and Armada XP SoC.
|
||||
*/
|
||||
|
||||
/include/ "skeleton64.dtsi"
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 and XP SoC";
|
||||
compatible = "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
eth0 = ð0;
|
||||
eth1 = ð1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu@0 {
|
||||
compatible = "marvell,sheeva-v7";
|
||||
device_type = "cpu";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&mpic>;
|
||||
pcie-mem-aperture = <0xf8000000 0x7e00000>;
|
||||
pcie-io-aperture = <0xffe00000 0x100000>;
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
rtc@10300 {
|
||||
compatible = "marvell,orion-rtc";
|
||||
reg = <0x10300 0x20>;
|
||||
interrupts = <50>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
|
||||
reg = <0x10600 0x28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <30>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
|
||||
reg = <0x10680 0x28>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <92>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <31>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <32>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <41>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <42>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pin-ctrl@18000 {
|
||||
reg = <0x18000 0x38>;
|
||||
};
|
||||
|
||||
coredivclk: corediv-clock@18740 {
|
||||
compatible = "marvell,armada-370-corediv-clock";
|
||||
reg = <0x18740 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>,
|
||||
<0x20250 0x8>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20000 {
|
||||
compatible = "marvell,mpic";
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
};
|
||||
|
||||
coherency-fabric@20200 {
|
||||
compatible = "marvell,coherency-fabric";
|
||||
reg = <0x20200 0xb0>, <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts = <37>, <38>, <39>, <40>, <5>, <6>;
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-370-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x500>;
|
||||
interrupts = <45>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x51000 0x500>;
|
||||
interrupts = <46>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio: mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
eth1: ethernet@74000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x74000 0x4000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
compatible = "marvell,armada-370-sata";
|
||||
reg = <0xa0000 0x5000>;
|
||||
interrupts = <55>;
|
||||
clocks = <&gateclk 15>, <&gateclk 30>;
|
||||
clock-names = "0", "1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <113>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
compatible = "marvell,orion-sdio";
|
||||
reg = <0xd4000 0x200>;
|
||||
interrupts = <54>;
|
||||
clocks = <&gateclk 17>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
399
sys/gnu/dts/arm/armada-370.dtsi
Normal file
399
sys/gnu/dts/arm/armada-370.dtsi
Normal file
@ -0,0 +1,399 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 370 family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada 370 SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-370-xp.dtsi"
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 370 family SoC";
|
||||
compatible = "marvell,armada370", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada370-mbus", "simple-bus";
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0xe0) 0 0x100000>;
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,aurora-outer-cache";
|
||||
reg = <0x08000 0x1000>;
|
||||
cache-id-part = <0x100>;
|
||||
cache-unified;
|
||||
wt-override;
|
||||
};
|
||||
|
||||
/*
|
||||
* Default SPI pinctrl setting, can be overwritten on
|
||||
* board level if a different configuration is used.
|
||||
*/
|
||||
spi0: spi@10600 {
|
||||
pinctrl-0 = <&spi0_pins1>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
reg = <0x11000 0x20>;
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
reg = <0x11100 0x20>;
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <2>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
/*
|
||||
* Default UART pinctrl setting without RTS/CTS, can
|
||||
* be overwritten on board level if a different
|
||||
* configuration is used.
|
||||
*/
|
||||
uart0: serial@12000 {
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
uart1: serial@12100 {
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-370-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18230 {
|
||||
compatible = "marvell,armada-370-core-clock";
|
||||
reg = <0x18230 0x08>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
thermal@18300 {
|
||||
compatible = "marvell,armada370-thermal";
|
||||
reg = <0x18300 0x4
|
||||
0x18304 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sscg@18330 {
|
||||
reg = <0x18330 0x4>;
|
||||
};
|
||||
|
||||
interrupt-controller@20000 {
|
||||
reg = <0x20a00 0x1d0>, <0x21870 0x58>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-370-timer";
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-370-wdt";
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x8>;
|
||||
};
|
||||
|
||||
audio_controller: audio-controller@30000 {
|
||||
#sound-dai-cells = <1>;
|
||||
compatible = "marvell,armada370-audio";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts = <93>;
|
||||
clocks = <&gateclk 0>;
|
||||
clock-names = "internal";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60A00 0x100>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <51>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <52>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <94>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <95>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv88f6710-pinctrl";
|
||||
|
||||
spi0_pins1: spi0-pins1 {
|
||||
marvell,pins = "mpp33", "mpp34",
|
||||
"mpp35", "mpp36";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi0_pins2: spi0_pins2 {
|
||||
marvell,pins = "mpp32", "mpp63",
|
||||
"mpp64", "mpp65";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi1-pins {
|
||||
marvell,pins = "mpp49", "mpp50",
|
||||
"mpp51", "mpp52";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart0_pins: uart0-pins {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "uart0";
|
||||
};
|
||||
|
||||
uart1_pins: uart1-pins {
|
||||
marvell,pins = "mpp41", "mpp42";
|
||||
marvell,function = "uart1";
|
||||
};
|
||||
|
||||
sdio_pins1: sdio-pins1 {
|
||||
marvell,pins = "mpp9", "mpp11", "mpp12",
|
||||
"mpp13", "mpp14", "mpp15";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sdio_pins2: sdio-pins2 {
|
||||
marvell,pins = "mpp47", "mpp48", "mpp49",
|
||||
"mpp50", "mpp51", "mpp52";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sdio_pins3: sdio-pins3 {
|
||||
marvell,pins = "mpp48", "mpp49", "mpp50",
|
||||
"mpp51", "mpp52", "mpp53";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
i2s_pins1: i2s-pins1 {
|
||||
marvell,pins = "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10",
|
||||
"mpp12", "mpp13";
|
||||
marvell,function = "audio";
|
||||
};
|
||||
|
||||
i2s_pins2: i2s-pins2 {
|
||||
marvell,pins = "mpp49", "mpp47", "mpp50",
|
||||
"mpp59", "mpp57", "mpp61",
|
||||
"mpp62", "mpp60", "mpp58";
|
||||
marvell,function = "audio";
|
||||
};
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
marvell,pins = "mpp17", "mpp18";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
ge0_rgmii_pins: ge0-rgmii-pins {
|
||||
marvell,pins = "mpp5", "mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11", "mpp12",
|
||||
"mpp13", "mpp14", "mpp15", "mpp16";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge1-rgmii-pins {
|
||||
marvell,pins = "mpp19", "mpp20", "mpp21", "mpp22",
|
||||
"mpp23", "mpp24", "mpp25", "mpp26",
|
||||
"mpp27", "mpp28", "mpp29", "mpp30";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
};
|
||||
204
sys/gnu/dts/arm/armada-375-db.dts
Normal file
204
sys/gnu/dts/arm/armada-375-db.dts
Normal file
@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 375 evaluation board
|
||||
* (DB-88F6720)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-375.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 375 Development Board";
|
||||
compatible = "marvell,a375-db", "marvell,armada375";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* SPI conflicts with NAND, so we disable it
|
||||
* here, and select NAND as the enabled device
|
||||
* by default.
|
||||
*/
|
||||
status = "disabled";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
i2c@11100 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-0 = <&i2c1_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
sdio_st_pins: sdio-st-pins {
|
||||
marvell,pins = "mpp44", "mpp45";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
status = "okay";
|
||||
nr-ports = <2>;
|
||||
};
|
||||
|
||||
nand: nand@d0000 {
|
||||
pinctrl-0 = <&nand_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x800000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Linux";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@54000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@58000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
pinctrl-0 = <&sdio_pins &sdio_st_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
cd-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@f0000 {
|
||||
status = "okay";
|
||||
|
||||
eth0@c4000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
eth1@c5000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "gmii";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
612
sys/gnu/dts/arm/armada-375.dtsi
Normal file
612
sys/gnu/dts/arm/armada-375.dtsi
Normal file
@ -0,0 +1,612 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 375 family SoC
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 375 family SoC";
|
||||
compatible = "marvell,armada375";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-375-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada375-mbus", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&gic>;
|
||||
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
L2: cache-controller@8000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x8000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu@c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xc000 0x58>;
|
||||
};
|
||||
|
||||
timer@c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xc600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0xd000 0x1000>,
|
||||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0xc0054 0x4>;
|
||||
clocks = <&gateclk 19>;
|
||||
};
|
||||
|
||||
/* Network controller */
|
||||
ethernet@f0000 {
|
||||
compatible = "marvell,armada-375-pp2";
|
||||
reg = <0xf0000 0xa000>, /* Packet Processor regs */
|
||||
<0xc0000 0x3060>, /* LMS regs */
|
||||
<0xc4000 0x100>, /* eth0 regs */
|
||||
<0xc5000 0x100>; /* eth1 regs */
|
||||
clocks = <&gateclk 3>, <&gateclk 19>;
|
||||
clock-names = "pp_clk", "gop_clk";
|
||||
status = "disabled";
|
||||
|
||||
eth0: eth0@c4000 {
|
||||
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
||||
port-id = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth1: eth1@c5000 {
|
||||
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
|
||||
port-id = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
rtc@10300 {
|
||||
compatible = "marvell,orion-rtc";
|
||||
reg = <0x10300 0x20>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl {
|
||||
compatible = "marvell,mv88f6720-pinctrl";
|
||||
reg = <0x18000 0x24>;
|
||||
|
||||
i2c0_pins: i2c0-pins {
|
||||
marvell,pins = "mpp14", "mpp15";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
i2c1_pins: i2c1-pins {
|
||||
marvell,pins = "mpp61", "mpp62";
|
||||
marvell,function = "i2c1";
|
||||
};
|
||||
|
||||
nand_pins: nand-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp2",
|
||||
"mpp3", "mpp4", "mpp5",
|
||||
"mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13";
|
||||
marvell,function = "nand";
|
||||
};
|
||||
|
||||
sdio_pins: sdio-pins {
|
||||
marvell,pins = "mpp24", "mpp25", "mpp26",
|
||||
"mpp27", "mpp28", "mpp29";
|
||||
marvell,function = "sd";
|
||||
};
|
||||
|
||||
spi0_pins: spi0-pins {
|
||||
marvell,pins = "mpp0", "mpp1", "mpp4",
|
||||
"mpp5", "mpp8", "mpp9";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-375-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-375-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
usbcluster: usb-cluster@18400 {
|
||||
compatible = "marvell,armada-375-usb-cluster";
|
||||
reg = <0x18400 0x4>;
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20000 {
|
||||
compatible = "marvell,mpic";
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&mpic 5>,
|
||||
<&mpic 6>;
|
||||
clocks = <&coreclk 0>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-375-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
|
||||
clocks = <&coreclk 0>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-375-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x50000 0x500>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 18>;
|
||||
phys = <&usbcluster PHY_TYPE_USB2>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@54000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x54000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@58000 {
|
||||
compatible = "marvell,armada-375-xhci";
|
||||
reg = <0x58000 0x20000>,<0x5b880 0x80>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 16>;
|
||||
phys = <&usbcluster PHY_TYPE_USB3>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60A00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 23>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
compatible = "marvell,orion-sata";
|
||||
reg = <0xa0000 0x5000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 14>, <&gateclk 20>;
|
||||
clock-names = "0", "1";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
compatible = "marvell,orion-sdio";
|
||||
reg = <0xd4000 0x200>;
|
||||
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 17>;
|
||||
bus-width = <4>;
|
||||
cap-sdio-irq;
|
||||
cap-sd-highspeed;
|
||||
cap-mmc-highspeed;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada375-thermal";
|
||||
reg = <0xe8078 0x4>, <0xe807c 0x8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@e8204 {
|
||||
compatible = "marvell,armada-375-core-clock";
|
||||
reg = <0xe8204 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coredivclk: corediv-clock@e8250 {
|
||||
compatible = "marvell,armada-375-corediv-clock";
|
||||
reg = <0xe8250 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
152
sys/gnu/dts/arm/armada-380.dtsi
Normal file
152
sys/gnu/dts/arm/armada-380.dtsi
Normal file
@ -0,0 +1,152 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 380 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 380 family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6810-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>;
|
||||
|
||||
/* x1 port */
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
178
sys/gnu/dts/arm/armada-385-db-ap.dts
Normal file
178
sys/gnu/dts/arm/armada-385-db-ap.dts
Normal file
@ -0,0 +1,178 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 385 Access Point Development board
|
||||
* (DB-88F6820-AP)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Nadav Haklai <nadavh@marvell.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-385.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 Access Point Development Board";
|
||||
compatible = "marvell,a385-db-ap", "marvell,armada385", "marvell,armada38x";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi1: spi@10680 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <54000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* This bus is wired to two EEPROM
|
||||
* sockets, one of which holding the
|
||||
* board ID used by the bootloader.
|
||||
* Erasing this EEPROM's content will
|
||||
* brick the board.
|
||||
* Use this bus with caution.
|
||||
*/
|
||||
};
|
||||
|
||||
mdio@72004 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@4 {
|
||||
reg = <4>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@6 {
|
||||
reg = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
/* UART0 is exposed through the JP8 connector */
|
||||
uart0: serial@12000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* UART1 is exposed through a FTDI chip
|
||||
* wired to the mini-USB connector
|
||||
*/
|
||||
uart1: serial@12100 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
|
||||
/*
|
||||
* The Reference Clock 0 is used to
|
||||
* provide a clock to the PHY
|
||||
*/
|
||||
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The three PCIe units are accessible through
|
||||
* standard mini-PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
184
sys/gnu/dts/arm/armada-385.dtsi
Normal file
184
sys/gnu/dts/arm/armada-385.dtsi
Normal file
@ -0,0 +1,184 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 385 SoC.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "armada-38x.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 family SoC";
|
||||
compatible = "marvell,armada385", "marvell,armada380";
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-380-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6820-pinctrl";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-370-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
|
||||
0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
|
||||
0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
|
||||
|
||||
/*
|
||||
* This port can be either x4 or x1. When
|
||||
* configured in x4 by the bootloader, then
|
||||
* pcie@4,0 is not available.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* x1 port */
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/*
|
||||
* x1 port only available when pcie@1,0 is
|
||||
* configured as a x1 port
|
||||
*/
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
186
sys/gnu/dts/arm/armada-388-db.dts
Normal file
186
sys/gnu/dts/arm/armada-388-db.dts
Normal file
@ -0,0 +1,186 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 388 evaluation board
|
||||
* (DB-88F6820)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 Development Board";
|
||||
compatible = "marvell,a385-db", "marvell,armada388",
|
||||
"marvell,armada385", "marvell,armada380";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "w25q32";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
i2c@11100 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "ok";
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
mdio@72004 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partition@0 {
|
||||
label = "U-Boot";
|
||||
reg = <0 0x800000>;
|
||||
};
|
||||
partition@800000 {
|
||||
label = "Linux";
|
||||
reg = <0x800000 0x800000>;
|
||||
};
|
||||
partition@1000000 {
|
||||
label = "Filesystem";
|
||||
reg = <0x1000000 0x3f000000>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
broken-cd;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
no-1-8-v;
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* The two PCIe units are accessible through
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
414
sys/gnu/dts/arm/armada-388-gp.dts
Normal file
414
sys/gnu/dts/arm/armada-388-gp.dts
Normal file
@ -0,0 +1,414 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 385 development board
|
||||
* (RD-88F6820-GP)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 GP";
|
||||
compatible = "marvell,a385-gp", "marvell,armada388", "marvell,armada380";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <50000000>;
|
||||
m25p,fast-read;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins>;
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
/*
|
||||
* The EEPROM located at adresse 54 is needed
|
||||
* for the boot - DO NOT ERASE IT -
|
||||
*/
|
||||
|
||||
expander0: pca9555@20 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pca0_pins>;
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x20>;
|
||||
};
|
||||
|
||||
expander1: pca9555@21 {
|
||||
compatible = "nxp,pca9555";
|
||||
pinctrl-names = "default";
|
||||
interrupt-parent = <&gpio0>;
|
||||
interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x21>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
/*
|
||||
* Exported on the micro USB connector CON16
|
||||
* through an FTDI
|
||||
*/
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart0_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE1 CON15 */
|
||||
ethernet@30000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* CON4 */
|
||||
usb@50000 {
|
||||
vcc-supply = <®_usb2_0_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* GE0 CON1 */
|
||||
ethernet@70000 {
|
||||
pinctrl-names = "default";
|
||||
/*
|
||||
* The Reference Clock 0 is used to provide a
|
||||
* clock to the PHY
|
||||
*/
|
||||
pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
|
||||
mdio@72004 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&mdio_pins>;
|
||||
|
||||
phy0: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata0: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata0>;
|
||||
};
|
||||
|
||||
sata1: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata1>;
|
||||
};
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
|
||||
status = "okay";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
sata2: sata-port@0 {
|
||||
reg = <0>;
|
||||
target-supply = <®_5v_sata2>;
|
||||
};
|
||||
|
||||
sata3: sata-port@1 {
|
||||
reg = <1>;
|
||||
target-supply = <®_5v_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&sdhci_pins>;
|
||||
cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;
|
||||
no-1-8-v;
|
||||
wp-inverted;
|
||||
bus-width = <8>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON5 */
|
||||
usb3@f0000 {
|
||||
vcc-supply = <®_usb2_1_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* CON7 */
|
||||
usb3@f8000 {
|
||||
vcc-supply = <®_usb3_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* One PCIe units is accessible through
|
||||
* standard PCIe slot on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* The two other PCIe units are accessible
|
||||
* through mini PCIe slot on the board.
|
||||
*/
|
||||
pcie@2,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-fan {
|
||||
compatible = "gpio-fan";
|
||||
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
|
||||
gpio-fan,speed-map = < 0 0
|
||||
3000 1>;
|
||||
};
|
||||
};
|
||||
|
||||
reg_usb3_vbus: usb3-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb3-vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_0_vbus: v5-vbus0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_usb2_1_vbus: v5-vbus1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-vbus1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_sata0: pwr-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata0";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
|
||||
};
|
||||
|
||||
reg_5v_sata0: v5-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata0";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_12v_sata0: v12-sata0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata0";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata0>;
|
||||
};
|
||||
|
||||
reg_sata1: pwr-sata1 {
|
||||
regulator-name = "pwr_en_sata1";
|
||||
compatible = "regulator-fixed";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata1: v5-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata1";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_12v_sata1: v12-sata1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata1";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata1>;
|
||||
};
|
||||
|
||||
reg_sata2: pwr-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata2";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata2: v5-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata2";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_12v_sata2: v12-sata2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata2";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata2>;
|
||||
};
|
||||
|
||||
reg_sata3: pwr-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "pwr_en_sata3";
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reg_5v_sata3: v5-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v5.0-sata3";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
|
||||
reg_12v_sata3: v12-sata3 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "v12.0-sata3";
|
||||
regulator-min-microvolt = <12000000>;
|
||||
regulator-max-microvolt = <12000000>;
|
||||
regulator-always-on;
|
||||
vin-supply = <®_sata3>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pca0_pins: pca0_pins {
|
||||
marvell,pins = "mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
132
sys/gnu/dts/arm/armada-388-rd.dts
Normal file
132
sys/gnu/dts/arm/armada-388-rd.dts
Normal file
@ -0,0 +1,132 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada 388 Reference Design board
|
||||
* (RD-88F6820-AP)
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-388.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 385 Reference Design";
|
||||
compatible = "marvell,a385-rd", "marvell,armada388",
|
||||
"marvell,armada385","marvell,armada380";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x10000000>; /* 256 MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "st,m25p128";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
|
||||
mdio@72004 {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/*
|
||||
* One PCIe units is accessible through
|
||||
* standard PCIe slot on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
70
sys/gnu/dts/arm/armada-388.dtsi
Normal file
70
sys/gnu/dts/arm/armada-388.dtsi
Normal file
@ -0,0 +1,70 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 388 SoC.
|
||||
*
|
||||
* Copyright (C) 2015 Marvell
|
||||
*
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without
|
||||
* any warranty of any kind, whether express or implied.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
*
|
||||
* The main difference with the Armada 385 is that the 388 can handle two more
|
||||
* SATA ports. So we can reuse the dtsi of the Armada 385, override the pinctrl
|
||||
* property and the name of the SoC, and add the second SATA host which control
|
||||
* the 2 other ports.
|
||||
*/
|
||||
|
||||
#include "armada-385.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 388 family SoC";
|
||||
compatible = "marvell,armada388", "marvell,armada385",
|
||||
"marvell,armada380";
|
||||
|
||||
soc {
|
||||
internal-regs {
|
||||
pinctrl@18000 {
|
||||
compatible = "marvell,mv88f6828-pinctrl";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
};
|
||||
591
sys/gnu/dts/arm/armada-38x.dtsi
Normal file
591
sys/gnu/dts/arm/armada-38x.dtsi
Normal file
@ -0,0 +1,591 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada 38x family of SoCs.
|
||||
*
|
||||
* Copyright (C) 2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada 38x family SoC";
|
||||
compatible = "marvell,armada380";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
ethernet0 = ð0;
|
||||
ethernet1 = ð1;
|
||||
ethernet2 = ð2;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armada380-mbus", "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
controller = <&mbusc>;
|
||||
interrupt-parent = <&gic>;
|
||||
pcie-mem-aperture = <0xe0000000 0x8000000>;
|
||||
pcie-io-aperture = <0xe8000000 0x100000>;
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
|
||||
};
|
||||
|
||||
devbus-bootcs {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs0 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs1 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs2 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
devbus-cs3 {
|
||||
compatible = "marvell,mvebu-devbus";
|
||||
reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
|
||||
ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
|
||||
|
||||
L2: cache-controller@8000 {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x8000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
scu@c000 {
|
||||
compatible = "arm,cortex-a9-scu";
|
||||
reg = <0xc000 0x58>;
|
||||
};
|
||||
|
||||
timer@c600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xc600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
|
||||
clocks = <&coreclk 2>;
|
||||
};
|
||||
|
||||
gic: interrupt-controller@d000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#size-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0xd000 0x1000>,
|
||||
<0xc100 0x100>;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
compatible = "marvell,orion-spi";
|
||||
reg = <0x10600 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <0>;
|
||||
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@10680 {
|
||||
compatible = "marvell,orion-spi";
|
||||
reg = <0x10680 0x50>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cell-index = <1>;
|
||||
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x20>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
|
||||
timeout-ms = <1000>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@12000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12000 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial@12100 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x12100 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl: pinctrl@18000 {
|
||||
reg = <0x18000 0x20>;
|
||||
|
||||
ge0_rgmii_pins: ge-rgmii-pins-0 {
|
||||
marvell,pins = "mpp6", "mpp7", "mpp8",
|
||||
"mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14",
|
||||
"mpp15", "mpp16", "mpp17";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge-rgmii-pins-1 {
|
||||
marvell,pins = "mpp21", "mpp27", "mpp28",
|
||||
"mpp29", "mpp30", "mpp31",
|
||||
"mpp32", "mpp37", "mpp38",
|
||||
"mpp39", "mpp40", "mpp41";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
i2c0_pins: i2c-pins-0 {
|
||||
marvell,pins = "mpp2", "mpp3";
|
||||
marvell,function = "i2c0";
|
||||
};
|
||||
|
||||
mdio_pins: mdio-pins {
|
||||
marvell,pins = "mpp4", "mpp5";
|
||||
marvell,function = "ge";
|
||||
};
|
||||
|
||||
ref_clk0_pins: ref-clk-pins-0 {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
ref_clk1_pins: ref-clk-pins-1 {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "ref";
|
||||
};
|
||||
|
||||
spi0_pins: spi-pins-0 {
|
||||
marvell,pins = "mpp22", "mpp23", "mpp24",
|
||||
"mpp25";
|
||||
marvell,function = "spi0";
|
||||
};
|
||||
|
||||
spi1_pins: spi-pins-1 {
|
||||
marvell,pins = "mpp56", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "spi1";
|
||||
};
|
||||
|
||||
uart0_pins: uart-pins-0 {
|
||||
marvell,pins = "mpp0", "mpp1";
|
||||
marvell,function = "ua0";
|
||||
};
|
||||
|
||||
uart1_pins: uart-pins-1 {
|
||||
marvell,pins = "mpp19", "mpp20";
|
||||
marvell,function = "ua1";
|
||||
};
|
||||
|
||||
sdhci_pins: sdhci-pins {
|
||||
marvell,pins = "mpp48", "mpp49", "mpp50",
|
||||
"mpp52", "mpp53", "mpp54",
|
||||
"mpp55", "mpp57", "mpp58",
|
||||
"mpp59";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
sata0_pins: sata-pins-0 {
|
||||
marvell,pins = "mpp20";
|
||||
marvell,function = "sata0";
|
||||
};
|
||||
|
||||
sata1_pins: sata-pins-1 {
|
||||
marvell,pins = "mpp19";
|
||||
marvell,function = "sata1";
|
||||
};
|
||||
|
||||
sata2_pins: sata-pins-2 {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "sata2";
|
||||
};
|
||||
|
||||
sata3_pins: sata-pins-3 {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "sata3";
|
||||
};
|
||||
};
|
||||
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <28>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-380-system-controller",
|
||||
"marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x100>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-380-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18600 {
|
||||
compatible = "marvell,armada-380-core-clock";
|
||||
reg = <0x18600 0x04>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
mbusc: mbus-controller@20000 {
|
||||
compatible = "marvell,mbus-controller";
|
||||
reg = <0x20000 0x100>, <0x20180 0x20>;
|
||||
};
|
||||
|
||||
mpic: interrupt-controller@20000 {
|
||||
compatible = "marvell,mpic";
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-controller;
|
||||
msi-controller;
|
||||
interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-380-timer",
|
||||
"marvell,armada-xp-timer";
|
||||
reg = <0x20300 0x30>, <0x21040 0x30>;
|
||||
interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<&mpic 5>,
|
||||
<&mpic 6>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-380-wdt";
|
||||
reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x10>;
|
||||
};
|
||||
|
||||
mpcore-soc-ctrl@20d20 {
|
||||
compatible = "marvell,armada-380-mpcore-soc-ctrl";
|
||||
reg = <0x20d20 0x6c>;
|
||||
};
|
||||
|
||||
coherency-fabric@21010 {
|
||||
compatible = "marvell,armada-380-coherency-fabric";
|
||||
reg = <0x21010 0x1c>;
|
||||
};
|
||||
|
||||
pmsu@22000 {
|
||||
compatible = "marvell,armada-380-pmsu";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
|
||||
eth1: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts-extended = <&mpic 10>;
|
||||
clocks = <&gateclk 3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
eth2: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts-extended = <&mpic 12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x58000 0x500>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60800 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60800 0x100
|
||||
0x60a00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
eth0: ethernet@70000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x70000 0x4000>;
|
||||
interrupts-extended = <&mpic 8>;
|
||||
clocks = <&gateclk 4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mdio@72004 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "marvell,orion-mdio";
|
||||
reg = <0x72004 0x4>;
|
||||
clocks = <&gateclk 4>;
|
||||
};
|
||||
|
||||
rtc@a3800 {
|
||||
compatible = "marvell,armada-380-rtc";
|
||||
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
|
||||
reg-names = "rtc", "rtc-soc";
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sata@a8000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xa8000 0x2000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 15>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sata@e0000 {
|
||||
compatible = "marvell,armada-380-ahci";
|
||||
reg = <0xe0000 0x2000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 30>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
coredivclk: clock@e4250 {
|
||||
compatible = "marvell,armada-380-corediv-clock";
|
||||
reg = <0xe4250 0xc>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&mainpll>;
|
||||
clock-output-names = "nand";
|
||||
};
|
||||
|
||||
thermal@e8078 {
|
||||
compatible = "marvell,armada380-thermal";
|
||||
reg = <0xe4078 0x4>, <0xe4074 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
flash@d0000 {
|
||||
compatible = "marvell,armada370-nand";
|
||||
reg = <0xd0000 0x54>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&coredivclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci@d8000 {
|
||||
compatible = "marvell,armada-380-sdhci";
|
||||
reg = <0xd8000 0x1000>, <0xdc000 0x100>;
|
||||
interrupts = <0 25 0x4>;
|
||||
clocks = <&gateclk 17>;
|
||||
mrvl,clk-delay-cycles = <0x1F>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f0000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
|
||||
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb3@f8000 {
|
||||
compatible = "marvell,armada-380-xhci";
|
||||
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 2 GHz fixed main PLL */
|
||||
mainpll: mainpll {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <2000000000>;
|
||||
};
|
||||
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
179
sys/gnu/dts/arm/armada-xp-axpwifiap.dts
Normal file
179
sys/gnu/dts/arm/armada-xp-axpwifiap.dts
Normal file
@ -0,0 +1,179 @@
|
||||
/*
|
||||
* Device Tree file for Marvell RD-AXPWiFiAP.
|
||||
*
|
||||
* Note: this board is shipped with a new generation boot loader that
|
||||
* remaps internal registers at 0xf1000000. Therefore, if earlyprintk
|
||||
* is used, the CONFIG_DEBUG_MVEBU_UART0_ALTERNATE option or the
|
||||
* CONFIG_DEBUG_MVEBU_UART1_ALTERNATE option should be used.
|
||||
*
|
||||
* Copyright (C) 2013 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "armada-xp-mv78230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell RD-AXPWiFiAP";
|
||||
compatible = "marvell,rd-axpwifiap", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* First mini-PCIe port */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Second mini-PCIe port */
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Renesas uPD720202 USB 3.0 controller */
|
||||
pcie@3,0 {
|
||||
/* Port 0, Lane 3 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
/* UART0 */
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* UART1 */
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
nr-ports = <1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&keys_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
button@1 {
|
||||
label = "Factory Reset Button";
|
||||
linux,code = <KEY_SETUP>;
|
||||
gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
pinctrl-0 = <&phy_int_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
keys_pin: keys-pin {
|
||||
marvell,pins = "mpp33";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
phy_int_pin: phy-int-pin {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
232
sys/gnu/dts/arm/armada-xp-db.dts
Normal file
232
sys/gnu/dts/arm/armada-xp-db.dts
Normal file
@ -0,0 +1,232 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada XP evaluation board
|
||||
* (DB-78460-BP)
|
||||
*
|
||||
* Copyright (C) 2012-2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the default
|
||||
* 0xd0000000). The 0xf1000000 is the default used by the recent,
|
||||
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
|
||||
* boards were delivered with an older version of the bootloader that
|
||||
* left internal registers mapped at 0xd0000000. If you are in this
|
||||
* situation, you should either update your bootloader (preferred
|
||||
* solution) or the below Device Tree should be adjusted.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Evaluation Board";
|
||||
compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0 0x80000000>; /* 2 GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <16>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* All 6 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@3,0 {
|
||||
/* Port 0, Lane 2 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@4,0 {
|
||||
/* Port 0, Lane 3 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12200 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <25>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <27>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@74000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
|
||||
mvsdio@d4000 {
|
||||
pinctrl-0 = <&sdio_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
/* No CD or WP GPIOs */
|
||||
broken-cd;
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@52000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "m25p64";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
245
sys/gnu/dts/arm/armada-xp-gp.dts
Normal file
245
sys/gnu/dts/arm/armada-xp-gp.dts
Normal file
@ -0,0 +1,245 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada XP development board
|
||||
* (DB-MV784MP-GP)
|
||||
*
|
||||
* Copyright (C) 2013-2014 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the default
|
||||
* 0xd0000000). The 0xf1000000 is the default used by the recent,
|
||||
* DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
|
||||
* boards were delivered with an older version of the bootloader that
|
||||
* left internal registers mapped at 0xd0000000. If you are in this
|
||||
* situation, you should either update your bootloader (preferred
|
||||
* solution) or the below Device Tree should be adjusted.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Development Board DB-MV784MP-GP";
|
||||
compatible = "marvell,axp-gp", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/*
|
||||
* 8 GB of plug-in RAM modules by default.The amount
|
||||
* of memory available can be changed by the
|
||||
* bootloader according the size of the module
|
||||
* actually plugged. However, memory between
|
||||
* 0xF0000000 to 0xFFFFFFFF cannot be used, as it is
|
||||
* the address range used for I/O (internal registers,
|
||||
* MBus windows).
|
||||
*/
|
||||
reg = <0x00000000 0x00000000 0x00000000 0xf0000000>,
|
||||
<0x00000001 0x00000000 0x00000001 0x00000000>;
|
||||
};
|
||||
|
||||
cpus {
|
||||
pm_pic {
|
||||
ctrl-gpios = <&gpio0 16 GPIO_ACTIVE_LOW>,
|
||||
<&gpio0 17 GPIO_ACTIVE_LOW>,
|
||||
<&gpio0 18 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <16>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 16 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x1000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* The 3 slots are physically present as
|
||||
* standard PCIe slots on the board.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@9,0 {
|
||||
/* Port 2, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
pcie@10,0 {
|
||||
/* Port 3, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12200 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12300 {
|
||||
status = "okay";
|
||||
};
|
||||
pinctrl {
|
||||
pinctrl-0 = <&pic_pins>;
|
||||
pinctrl-names = "default";
|
||||
pic_pins: pic-pins-0 {
|
||||
marvell,pins = "mpp16", "mpp17",
|
||||
"mpp18";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <16>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <18>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <19>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@74000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "qsgmii";
|
||||
};
|
||||
|
||||
/* Front-side USB slot */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Back-side USB slot */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "n25q128a13";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <108000000>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
326
sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts
Normal file
326
sys/gnu/dts/arm/armada-xp-lenovo-ix4-300d.dts
Normal file
@ -0,0 +1,326 @@
|
||||
/*
|
||||
* Device Tree file for Lenovo Iomega ix4-300d
|
||||
*
|
||||
* Copyright (C) 2014, Benoit Masson <yahoo@perenite.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-xp-mv78230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Lenovo Iomega ix4-300d";
|
||||
compatible = "lenovo,ix4-300d", "marvell,armadaxp-mv78230",
|
||||
"marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0 0x20000000>; /* 512MB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Quad port sata: Marvell 88SX7042 */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* USB 3.0 xHCI controller: NEC D720200F1 */
|
||||
pcie@5,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
adt7473@2e {
|
||||
compatible = "adi,adt7473";
|
||||
reg = <0x2e>;
|
||||
};
|
||||
|
||||
eeprom@50 {
|
||||
compatible = "atmel,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
|
||||
pcf8563@51 {
|
||||
compatible = "nxp,pcf8563";
|
||||
reg = <0x51>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0000000 0xe0000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@e0000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0xe0000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
label = "u-boot-env2";
|
||||
reg = <0x100000 0x20000>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@120000 {
|
||||
label = "zImage";
|
||||
reg = <0x120000 0x400000>;
|
||||
};
|
||||
|
||||
partition@520000 {
|
||||
label = "initrd";
|
||||
reg = <0x520000 0x400000>;
|
||||
};
|
||||
|
||||
partition@xE00000 {
|
||||
label = "boot";
|
||||
reg = <0xE00000 0x3F200000>;
|
||||
};
|
||||
|
||||
partition@flash {
|
||||
label = "flash";
|
||||
reg = <0x0 0x40000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&power_button_pin &reset_button_pin
|
||||
&select_button_pin &scroll_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-button {
|
||||
label = "Power Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reset-button {
|
||||
label = "Reset Button";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
select-button {
|
||||
label = "Select Button";
|
||||
linux,code = <BTN_SELECT>;
|
||||
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
scroll-button {
|
||||
label = "Scroll Button";
|
||||
linux,code = <KEY_SCROLLDOWN>;
|
||||
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
spi3 {
|
||||
compatible = "spi-gpio";
|
||||
status = "okay";
|
||||
gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>;
|
||||
gpio-mosi = <&gpio1 15 GPIO_ACTIVE_LOW>; /*gpio 47*/
|
||||
cs-gpios = <&gpio0 27 GPIO_ACTIVE_LOW>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio_spi: gpio_spi@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0>;
|
||||
registers-number = <1>;
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&hdd_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
hdd-led {
|
||||
label = "ix4-300d:hdd:blue";
|
||||
gpios = <&gpio0 26 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
power-led {
|
||||
label = "ix4-300d:power:white";
|
||||
gpios = <&gpio_spi 1 GPIO_ACTIVE_LOW>;
|
||||
/* init blinking while booting */
|
||||
linux,default-trigger = "timer";
|
||||
default-state = "on";
|
||||
};
|
||||
|
||||
sysfail-led {
|
||||
label = "ix4-300d:sysfail:red";
|
||||
gpios = <&gpio_spi 2 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
sys-led {
|
||||
label = "ix4-300d:sys:blue";
|
||||
gpios = <&gpio_spi 3 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
hddfail-led {
|
||||
label = "ix4-300d:hddfail:red";
|
||||
gpios = <&gpio_spi 4 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/*
|
||||
* Warning: you need both eth1 & 0 PHY initialized (i.e having
|
||||
* them up does the tweak) for poweroff to shutdown otherwise it
|
||||
* reboots
|
||||
*/
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
pinctrl-0 = <&poweroff_pin>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpio0 24 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
poweroff_pin: poweroff-pin {
|
||||
marvell,pins = "mpp24";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
power_button_pin: power-button-pin {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
reset_button_pin: reset-button-pin {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
select_button_pin: select-button-pin {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
scroll_button_pin: scroll-button-pin {
|
||||
marvell,pins = "mpp42";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
hdd_led_pin: hdd-led-pin {
|
||||
marvell,pins = "mpp26";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
114
sys/gnu/dts/arm/armada-xp-matrix.dts
Normal file
114
sys/gnu/dts/arm/armada-xp-matrix.dts
Normal file
@ -0,0 +1,114 @@
|
||||
/*
|
||||
* Device Tree file for Marvell Armada XP Matrix board
|
||||
*
|
||||
* Copyright (C) 2013 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include "armada-xp-mv78460.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP Matrix Board";
|
||||
compatible = "marvell,axp-matrix", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
/*
|
||||
* This board has 4 GB of RAM, but the last 256 MB of
|
||||
* RAM are not usable due to the overlap with the MBus
|
||||
* Window address range
|
||||
*/
|
||||
reg = <0 0x00000000 0 0xf0000000>;
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12200 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy-mode = "sgmii";
|
||||
fixed-link {
|
||||
speed = <1000>;
|
||||
full-duplex;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
231
sys/gnu/dts/arm/armada-xp-mv78230.dtsi
Normal file
231
sys/gnu/dts/arm/armada-xp-mv78230.dtsi
Normal file
@ -0,0 +1,231 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78230 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78230 SoC";
|
||||
compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78230 has 2 PCIe units Gen2.0: One unit can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x1 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <17>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78230-pinctrl";
|
||||
};
|
||||
334
sys/gnu/dts/arm/armada-xp-mv78260.dtsi
Normal file
334
sys/gnu/dts/arm/armada-xp-mv78260.dtsi
Normal file
@ -0,0 +1,334 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78260 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78260 SoC";
|
||||
compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
eth3 = ð3;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78260 has 3 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. One unit is
|
||||
* x4 only.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78260-pinctrl";
|
||||
};
|
||||
372
sys/gnu/dts/arm/armada-xp-mv78460.dtsi
Normal file
372
sys/gnu/dts/arm/armada-xp-mv78460.dtsi
Normal file
@ -0,0 +1,372 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP MV78460 SoC that are not
|
||||
* common to all Armada XP SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP MV78460 SoC";
|
||||
compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
gpio0 = &gpio0;
|
||||
gpio1 = &gpio1;
|
||||
gpio2 = &gpio2;
|
||||
eth3 = ð3;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "marvell,armada-xp-smp";
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <0>;
|
||||
clocks = <&cpuclk 0>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <1>;
|
||||
clocks = <&cpuclk 1>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <2>;
|
||||
clocks = <&cpuclk 2>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
|
||||
cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "marvell,sheeva-v7";
|
||||
reg = <3>;
|
||||
clocks = <&cpuclk 3>;
|
||||
clock-latency = <1000000>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
/*
|
||||
* MV78460 has 4 PCIe units Gen2.0: Two units can be
|
||||
* configured as x4 or quad x1 lanes. Two units are
|
||||
* x4/x1.
|
||||
*/
|
||||
pcie-controller {
|
||||
compatible = "marvell,armada-xp-pcie";
|
||||
status = "disabled";
|
||||
device_type = "pci";
|
||||
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
|
||||
msi-parent = <&mpic>;
|
||||
bus-range = <0x00 0xff>;
|
||||
|
||||
ranges =
|
||||
<0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
|
||||
0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
|
||||
0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
|
||||
0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
|
||||
0x82000000 0 0x4c000 MBUS_ID(0xf0, 0x01) 0x4c000 0 0x00002000 /* Port 0.3 registers */
|
||||
0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 /* Port 1.0 registers */
|
||||
0x82000000 0 0x82000 MBUS_ID(0xf0, 0x01) 0x82000 0 0x00002000 /* Port 3.0 registers */
|
||||
0x82000000 0 0x84000 MBUS_ID(0xf0, 0x01) 0x84000 0 0x00002000 /* Port 1.1 registers */
|
||||
0x82000000 0 0x88000 MBUS_ID(0xf0, 0x01) 0x88000 0 0x00002000 /* Port 1.2 registers */
|
||||
0x82000000 0 0x8c000 MBUS_ID(0xf0, 0x01) 0x8c000 0 0x00002000 /* Port 1.3 registers */
|
||||
0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */
|
||||
0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */
|
||||
0x82000000 0x2 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 0.1 MEM */
|
||||
0x81000000 0x2 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 0.1 IO */
|
||||
0x82000000 0x3 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 0.2 MEM */
|
||||
0x81000000 0x3 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 0.2 IO */
|
||||
0x82000000 0x4 0 MBUS_ID(0x04, 0x78) 0 1 0 /* Port 0.3 MEM */
|
||||
0x81000000 0x4 0 MBUS_ID(0x04, 0x70) 0 1 0 /* Port 0.3 IO */
|
||||
|
||||
0x82000000 0x5 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 1.0 MEM */
|
||||
0x81000000 0x5 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 1.0 IO */
|
||||
0x82000000 0x6 0 MBUS_ID(0x08, 0xd8) 0 1 0 /* Port 1.1 MEM */
|
||||
0x81000000 0x6 0 MBUS_ID(0x08, 0xd0) 0 1 0 /* Port 1.1 IO */
|
||||
0x82000000 0x7 0 MBUS_ID(0x08, 0xb8) 0 1 0 /* Port 1.2 MEM */
|
||||
0x81000000 0x7 0 MBUS_ID(0x08, 0xb0) 0 1 0 /* Port 1.2 IO */
|
||||
0x82000000 0x8 0 MBUS_ID(0x08, 0x78) 0 1 0 /* Port 1.3 MEM */
|
||||
0x81000000 0x8 0 MBUS_ID(0x08, 0x70) 0 1 0 /* Port 1.3 IO */
|
||||
|
||||
0x82000000 0x9 0 MBUS_ID(0x04, 0xf8) 0 1 0 /* Port 2.0 MEM */
|
||||
0x81000000 0x9 0 MBUS_ID(0x04, 0xf0) 0 1 0 /* Port 2.0 IO */
|
||||
|
||||
0x82000000 0xa 0 MBUS_ID(0x08, 0xf8) 0 1 0 /* Port 3.0 MEM */
|
||||
0x81000000 0xa 0 MBUS_ID(0x08, 0xf0) 0 1 0 /* Port 3.0 IO */>;
|
||||
|
||||
pcie@1,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
||||
reg = <0x0800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 58>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 5>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@2,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001000 0 0x44000 0 0x2000>;
|
||||
reg = <0x1000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 59>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 6>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@3,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82001800 0 0x48000 0 0x2000>;
|
||||
reg = <0x1800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 60>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@4,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002000 0 0x4c000 0 0x2000>;
|
||||
reg = <0x2000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 61>;
|
||||
marvell,pcie-port = <0>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 8>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@5,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82002800 0 0x80000 0 0x2000>;
|
||||
reg = <0x2800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x5 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 62>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 9>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@6,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003000 0 0x84000 0 0x2000>;
|
||||
reg = <0x3000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x6 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 63>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <1>;
|
||||
clocks = <&gateclk 10>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@7,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82003800 0 0x88000 0 0x2000>;
|
||||
reg = <0x3800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x7 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 64>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <2>;
|
||||
clocks = <&gateclk 11>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@8,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004000 0 0x8c000 0 0x2000>;
|
||||
reg = <0x4000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x8 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 65>;
|
||||
marvell,pcie-port = <1>;
|
||||
marvell,pcie-lane = <3>;
|
||||
clocks = <&gateclk 12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@9,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82004800 0 0x42000 0 0x2000>;
|
||||
reg = <0x4800 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
|
||||
0x81000000 0 0 0x81000000 0x9 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 99>;
|
||||
marvell,pcie-port = <2>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie@10,0 {
|
||||
device_type = "pci";
|
||||
assigned-addresses = <0x82005000 0 0x82000 0 0x2000>;
|
||||
reg = <0x5000 0 0 0 0>;
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
|
||||
0x81000000 0 0 0x81000000 0xa 0 1 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &mpic 103>;
|
||||
marvell,pcie-port = <3>;
|
||||
marvell,pcie-lane = <0>;
|
||||
clocks = <&gateclk 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
gpio0: gpio@18100 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18100 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <82>, <83>, <84>, <85>;
|
||||
};
|
||||
|
||||
gpio1: gpio@18140 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18140 0x40>;
|
||||
ngpios = <32>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <87>, <88>, <89>, <90>;
|
||||
};
|
||||
|
||||
gpio2: gpio@18180 {
|
||||
compatible = "marvell,orion-gpio";
|
||||
reg = <0x18180 0x40>;
|
||||
ngpios = <3>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <91>;
|
||||
};
|
||||
|
||||
eth3: ethernet@34000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x34000 0x4000>;
|
||||
interrupts = <14>;
|
||||
clocks = <&gateclk 1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
compatible = "marvell,mv78460-pinctrl";
|
||||
};
|
||||
370
sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts
Normal file
370
sys/gnu/dts/arm/armada-xp-netgear-rn2120.dts
Normal file
@ -0,0 +1,370 @@
|
||||
/*
|
||||
* Device Tree file for NETGEAR ReadyNAS 2120
|
||||
*
|
||||
* Copyright (C) 2013, Arnaud EBALARD <arno@natisbad.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-xp-mv78230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "NETGEAR ReadyNAS 2120";
|
||||
compatible = "netgear,readynas-2120", "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0 0x80000000>; /* 2GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/* Connected to first Marvell 88SE9170 SATA controller */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected to second Marvell 88SE9170 SATA controller */
|
||||
pcie@2,0 {
|
||||
/* Port 0, Lane 1 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected to Fresco Logic FL1009 USB 3.0 controller */
|
||||
pcie@5,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
/* Two rear eSATA ports */
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1318 */
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1318 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
/* Front USB 2.0 port */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
compatible = "marvell,mv64xxx-i2c";
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
isl12057: isl12057@68 {
|
||||
compatible = "isil,isl12057";
|
||||
reg = <0x68>;
|
||||
isil,irq2-can-wakeup-machine;
|
||||
};
|
||||
|
||||
/* Controller for rear fan #1 of 3 (Protechnic
|
||||
* MGT4012XB-O20, 8000RPM) near eSATA port */
|
||||
g762_fan1: g762@3e {
|
||||
compatible = "gmt,g762";
|
||||
reg = <0x3e>;
|
||||
clocks = <&g762_clk>; /* input clock */
|
||||
fan_gear_mode = <0>;
|
||||
fan_startv = <1>;
|
||||
pwm_polarity = <0>;
|
||||
};
|
||||
|
||||
/* Controller for rear (center) fan #2 of 3 */
|
||||
g762_fan2: g762@48 {
|
||||
compatible = "gmt,g762";
|
||||
reg = <0x48>;
|
||||
clocks = <&g762_clk>; /* input clock */
|
||||
fan_gear_mode = <0>;
|
||||
fan_startv = <1>;
|
||||
pwm_polarity = <0>;
|
||||
};
|
||||
|
||||
/* Controller for rear fan #3 of 3 */
|
||||
g762_fan3: g762@49 {
|
||||
compatible = "gmt,g762";
|
||||
reg = <0x49>;
|
||||
clocks = <&g762_clk>; /* input clock */
|
||||
fan_gear_mode = <0>;
|
||||
fan_startv = <1>;
|
||||
pwm_polarity = <0>;
|
||||
};
|
||||
|
||||
/* Temperature sensor */
|
||||
g751: g751@4c {
|
||||
compatible = "gmt,g751";
|
||||
reg = <0x4c>;
|
||||
};
|
||||
};
|
||||
|
||||
nand@d0000 {
|
||||
status = "okay";
|
||||
num-cs = <1>;
|
||||
marvell,nand-keep-config;
|
||||
marvell,nand-enable-arbiter;
|
||||
nand-on-flash-bbt;
|
||||
|
||||
/* Use Hardware BCH ECC */
|
||||
nand-ecc-strength = <4>;
|
||||
nand-ecc-step-size = <512>;
|
||||
|
||||
partition@0 {
|
||||
label = "u-boot";
|
||||
reg = <0x0000000 0x180000>; /* 1.5MB */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@180000 {
|
||||
label = "u-boot-env";
|
||||
reg = <0x180000 0x20000>; /* 128KB */
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
label = "uImage";
|
||||
reg = <0x0200000 0x600000>; /* 6MB */
|
||||
};
|
||||
|
||||
partition@800000 {
|
||||
label = "minirootfs";
|
||||
reg = <0x0800000 0x400000>; /* 4MB */
|
||||
};
|
||||
|
||||
/* Last MB is for the BBT, i.e. not writable */
|
||||
partition@c00000 {
|
||||
label = "ubifs";
|
||||
reg = <0x0c00000 0x7400000>; /* 116MB */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
g762_clk: g762-oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-0 = <&sata1_led_pin &sata2_led_pin &err_led_pin
|
||||
&sata3_led_pin &sata4_led_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
red-sata1-led {
|
||||
label = "rn2120:red:sata1";
|
||||
gpios = <&gpio0 31 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
red-sata2-led {
|
||||
label = "rn2120:red:sata2";
|
||||
gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
red-sata3-led {
|
||||
label = "rn2120:red:sata3";
|
||||
gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
red-sata4-led {
|
||||
label = "rn2120:red:sata4";
|
||||
gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
red-err-led {
|
||||
label = "rn2120:red:err";
|
||||
gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
pinctrl-0 = <&power_button_pin &reset_button_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
power-button {
|
||||
label = "Power Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio0 27 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
reset-button {
|
||||
label = "Reset Button";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
gpio-poweroff {
|
||||
compatible = "gpio-poweroff";
|
||||
pinctrl-0 = <&poweroff>;
|
||||
pinctrl-names = "default";
|
||||
gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
poweroff: poweroff {
|
||||
marvell,pins = "mpp42";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
power_button_pin: power-button-pin {
|
||||
marvell,pins = "mpp27";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
reset_button_pin: reset-button-pin {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_led_pin: sata1-led-pin {
|
||||
marvell,pins = "mpp31";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_led_pin: sata2-led-pin {
|
||||
marvell,pins = "mpp40";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata3_led_pin: sata3-led-pin {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata4_led_pin: sata4-led-pin {
|
||||
marvell,pins = "mpp47";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_power_pin: sata1-power-pin {
|
||||
marvell,pins = "mpp24";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_power_pin: sata2-power-pin {
|
||||
marvell,pins = "mpp25";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata3_power_pin: sata3-power-pin {
|
||||
marvell,pins = "mpp26";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata4_power_pin: sata4-power-pin {
|
||||
marvell,pins = "mpp28";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_pres_pin: sata1-pres-pin {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_pres_pin: sata2-pres-pin {
|
||||
marvell,pins = "mpp33";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata3_pres_pin: sata3-pres-pin {
|
||||
marvell,pins = "mpp34";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata4_pres_pin: sata4-pres-pin {
|
||||
marvell,pins = "mpp35";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
err_led_pin: err-led-pin {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
225
sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts
Normal file
225
sys/gnu/dts/arm/armada-xp-openblocks-ax3-4.dts
Normal file
@ -0,0 +1,225 @@
|
||||
/*
|
||||
* Device Tree file for OpenBlocks AX3-4 board
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include "armada-xp-mv78260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "PlatHome OpenBlocks AX3-4 board";
|
||||
compatible = "plathome,openblocks-ax3-4", "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0 0x40000000>; /* 1 GB soldered on */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xd0000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000
|
||||
MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x8000000>;
|
||||
|
||||
devbus-bootcs {
|
||||
status = "okay";
|
||||
|
||||
/* Device Bus parameters are required */
|
||||
|
||||
/* Read parameters */
|
||||
devbus,bus-width = <16>;
|
||||
devbus,turn-off-ps = <60000>;
|
||||
devbus,badr-skew-ps = <0>;
|
||||
devbus,acc-first-ps = <124000>;
|
||||
devbus,acc-next-ps = <248000>;
|
||||
devbus,rd-setup-ps = <0>;
|
||||
devbus,rd-hold-ps = <0>;
|
||||
|
||||
/* Write parameters */
|
||||
devbus,sync-enable = <0>;
|
||||
devbus,wr-high-ps = <60000>;
|
||||
devbus,wr-low-ps = <60000>;
|
||||
devbus,ale-wr-ps = <60000>;
|
||||
|
||||
/* NOR 128 MiB */
|
||||
nor@0 {
|
||||
compatible = "cfi-flash";
|
||||
reg = <0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
/* Internal mini-PCIe connector */
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&led_pins>;
|
||||
|
||||
red_led {
|
||||
label = "red_led";
|
||||
gpios = <&gpio1 17 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
yellow_led {
|
||||
label = "yellow_led";
|
||||
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
default-state = "off";
|
||||
};
|
||||
|
||||
green_led {
|
||||
label = "green_led";
|
||||
gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
|
||||
default-state = "keep";
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
button@1 {
|
||||
label = "Init Button";
|
||||
linux,code = <KEY_POWER>;
|
||||
gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 {
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 {
|
||||
reg = <1>;
|
||||
};
|
||||
|
||||
phy2: ethernet-phy@2 {
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
phy3: ethernet-phy@3 {
|
||||
reg = <3>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
ethernet@74000 {
|
||||
status = "okay";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
ethernet@30000 {
|
||||
status = "okay";
|
||||
phy = <&phy2>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
ethernet@34000 {
|
||||
status = "okay";
|
||||
phy = <&phy3>;
|
||||
phy-mode = "sgmii";
|
||||
};
|
||||
i2c@11000 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
i2c@11100 {
|
||||
status = "okay";
|
||||
clock-frequency = <400000>;
|
||||
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "s35390a";
|
||||
reg = <0x30>;
|
||||
};
|
||||
};
|
||||
sata@a0000 {
|
||||
nr-ports = <2>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Front side USB 0 */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Front side USB 1 */
|
||||
usb@51000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
led_pins: led-pins-0 {
|
||||
marvell,pins = "mpp49", "mpp51", "mpp53";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
363
sys/gnu/dts/arm/armada-xp-synology-ds414.dts
Normal file
363
sys/gnu/dts/arm/armada-xp-synology-ds414.dts
Normal file
@ -0,0 +1,363 @@
|
||||
/*
|
||||
* Device Tree file for Synology DS414
|
||||
*
|
||||
* Copyright (C) 2014, Arnaud EBALARD <arno@natisbad.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Note: this Device Tree assumes that the bootloader has remapped the
|
||||
* internal registers to 0xf1000000 (instead of the old 0xd0000000).
|
||||
* The 0xf1000000 is the default used by the recent, DT-capable, U-Boot
|
||||
* bootloaders provided by Marvell. It is used in recent versions of
|
||||
* DSM software provided by Synology. Nonetheless, some earlier boards
|
||||
* were delivered with an older version of u-boot that left internal
|
||||
* registers mapped at 0xd0000000. If you have such a device you will
|
||||
* not be able to directly boot a kernel based on this Device Tree. In
|
||||
* that case, the preferred solution is to update your bootloader (e.g.
|
||||
* by upgrading to latest version of DSM, or building a new one and
|
||||
* installing it from u-boot prompt) or adjust the Devive Tree
|
||||
* (s/0xf1000000/0xd0000000/ in 'ranges' below).
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include "armada-xp-mv78230.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Synology DS414";
|
||||
compatible = "synology,ds414", "marvell,armadaxp-mv78230",
|
||||
"marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 earlyprintk";
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0 0x40000000>; /* 1GB */
|
||||
};
|
||||
|
||||
soc {
|
||||
ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000
|
||||
MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000>;
|
||||
|
||||
pcie-controller {
|
||||
status = "okay";
|
||||
|
||||
/*
|
||||
* Connected to Marvell 88SX7042 SATA-II controller
|
||||
* handling the four disks.
|
||||
*/
|
||||
pcie@1,0 {
|
||||
/* Port 0, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/*
|
||||
* Connected to EtronTech EJ168A XHCI controller
|
||||
* providing the two rear USB 3.0 ports.
|
||||
*/
|
||||
pcie@5,0 {
|
||||
/* Port 1, Lane 0 */
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
|
||||
/* RTC is provided by Seiko S-35390A below */
|
||||
rtc@10300 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
status = "okay";
|
||||
|
||||
spi-flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "micron,n25q064";
|
||||
reg = <0>; /* Chip select 0 */
|
||||
spi-max-frequency = <20000000>;
|
||||
|
||||
/*
|
||||
* Warning!
|
||||
*
|
||||
* Synology u-boot uses its compiled-in environment
|
||||
* and it seems Synology did not care to change u-boot
|
||||
* default configuration in order to allow saving a
|
||||
* modified environment at a sensible location. So,
|
||||
* if you do a 'saveenv' under u-boot, your modified
|
||||
* environment will be saved at 1MB after the start
|
||||
* of the flash, i.e. in the middle of the uImage.
|
||||
* For that reason, it is strongly advised not to
|
||||
* change the default environment, unless you know
|
||||
* what you are doing.
|
||||
*/
|
||||
partition@00000000 { /* u-boot */
|
||||
label = "RedBoot";
|
||||
reg = <0x00000000 0x000d0000>; /* 832KB */
|
||||
};
|
||||
|
||||
partition@000c0000 { /* uImage */
|
||||
label = "zImage";
|
||||
reg = <0x000d0000 0x002d0000>; /* 2880KB */
|
||||
};
|
||||
|
||||
partition@003a0000 { /* uInitramfs */
|
||||
label = "rd.gz";
|
||||
reg = <0x003a0000 0x00430000>; /* 4250KB */
|
||||
};
|
||||
|
||||
partition@007d0000 { /* MAC address and serial number */
|
||||
label = "vendor";
|
||||
reg = <0x007d0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007e0000 {
|
||||
label = "RedBoot config";
|
||||
reg = <0x007e0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
|
||||
partition@007f0000 {
|
||||
label = "FIS directory";
|
||||
reg = <0x007f0000 0x00010000>; /* 64KB */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
i2c@11000 {
|
||||
clock-frequency = <400000>;
|
||||
status = "okay";
|
||||
|
||||
s35390a: s35390a@30 {
|
||||
compatible = "sii,s35390a";
|
||||
reg = <0x30>;
|
||||
};
|
||||
};
|
||||
|
||||
/* Connected to a header on device's PCB. This
|
||||
* provides the main console for the device.
|
||||
*
|
||||
* Warning: the device may not boot with a 3.3V
|
||||
* USB-serial converter connected when the power
|
||||
* button is pressed. The converter needs to be
|
||||
* connected a few seconds after pressing the
|
||||
* power button. This is possibly due to UART0_TXD
|
||||
* pin being sampled at reset (bit 0 of SAR).
|
||||
*/
|
||||
serial@12000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* Connected to a Microchip PIC16F883 for power control */
|
||||
serial@12100 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
poweroff@12100 {
|
||||
compatible = "synology,power-off";
|
||||
reg = <0x12100 0x100>;
|
||||
clocks = <&coreclk 0>;
|
||||
};
|
||||
|
||||
/* Front USB 2.0 port */
|
||||
usb@50000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mdio {
|
||||
phy0: ethernet-phy@0 { /* Marvell 88E1512 */
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
phy1: ethernet-phy@1 { /* Marvell 88E1512 */
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethernet@70000 {
|
||||
status = "okay";
|
||||
pinctrl-0 = <&ge0_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
phy = <&phy1>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
|
||||
ethernet@74000 {
|
||||
pinctrl-0 = <&ge1_rgmii_pins>;
|
||||
pinctrl-names = "default";
|
||||
status = "okay";
|
||||
phy = <&phy0>;
|
||||
phy-mode = "rgmii-id";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-0 = <&sata1_pwr_pin &sata2_pwr_pin
|
||||
&sata3_pwr_pin &sata4_pwr_pin>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
sata1_regulator: sata1-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <1>;
|
||||
regulator-name = "SATA1 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <2000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata2_regulator: sata2-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <2>;
|
||||
regulator-name = "SATA2 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <4000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata3_regulator: sata3-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <3>;
|
||||
regulator-name = "SATA3 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <6000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
sata4_regulator: sata4-regulator {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <4>;
|
||||
regulator-name = "SATA4 Power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
startup-delay-us = <8000000>;
|
||||
enable-active-high;
|
||||
regulator-always-on;
|
||||
regulator-boot-on;
|
||||
gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
sata1_pwr_pin: sata1-pwr-pin {
|
||||
marvell,pins = "mpp42";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_pwr_pin: sata2-pwr-pin {
|
||||
marvell,pins = "mpp44";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata3_pwr_pin: sata3-pwr-pin {
|
||||
marvell,pins = "mpp45";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata4_pwr_pin: sata4-pwr-pin {
|
||||
marvell,pins = "mpp46";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata1_pres_pin: sata1-pres-pin {
|
||||
marvell,pins = "mpp34";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata2_pres_pin: sata2-pres-pin {
|
||||
marvell,pins = "mpp35";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata3_pres_pin: sata3-pres-pin {
|
||||
marvell,pins = "mpp40";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
sata4_pres_pin: sata4-pres-pin {
|
||||
marvell,pins = "mpp41";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit0_pin: syno-id-bit0-pin {
|
||||
marvell,pins = "mpp26";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit1_pin: syno-id-bit1-pin {
|
||||
marvell,pins = "mpp28";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
syno_id_bit2_pin: syno-id-bit2-pin {
|
||||
marvell,pins = "mpp29";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
fan1_alarm_pin: fan1-alarm-pin {
|
||||
marvell,pins = "mpp33";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
|
||||
fan2_alarm_pin: fan2-alarm-pin {
|
||||
marvell,pins = "mpp32";
|
||||
marvell,function = "gpio";
|
||||
};
|
||||
};
|
||||
302
sys/gnu/dts/arm/armada-xp.dtsi
Normal file
302
sys/gnu/dts/arm/armada-xp.dtsi
Normal file
@ -0,0 +1,302 @@
|
||||
/*
|
||||
* Device Tree Include file for Marvell Armada XP family SoC
|
||||
*
|
||||
* Copyright (C) 2012 Marvell
|
||||
*
|
||||
* Lior Amsalem <alior@marvell.com>
|
||||
* Gregory CLEMENT <gregory.clement@free-electrons.com>
|
||||
* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
|
||||
* Ben Dooks <ben.dooks@codethink.co.uk>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*
|
||||
* Contains definitions specific to the Armada XP SoC that are not
|
||||
* common to all Armada SoCs.
|
||||
*/
|
||||
|
||||
#include "armada-370-xp.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Marvell Armada XP family SoC";
|
||||
compatible = "marvell,armadaxp", "marvell,armada-370-xp";
|
||||
|
||||
aliases {
|
||||
eth2 = ð2;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "marvell,armadaxp-mbus", "simple-bus";
|
||||
|
||||
bootrom {
|
||||
compatible = "marvell,bootrom";
|
||||
reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
|
||||
};
|
||||
|
||||
internal-regs {
|
||||
sdramc@1400 {
|
||||
compatible = "marvell,armada-xp-sdram-controller";
|
||||
reg = <0x1400 0x500>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "marvell,aurora-system-cache";
|
||||
reg = <0x08000 0x1000>;
|
||||
cache-id-part = <0x100>;
|
||||
cache-unified;
|
||||
wt-override;
|
||||
};
|
||||
|
||||
spi0: spi@10600 {
|
||||
pinctrl-0 = <&spi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
};
|
||||
|
||||
i2c0: i2c@11000 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11000 0x100>;
|
||||
};
|
||||
|
||||
i2c1: i2c@11100 {
|
||||
compatible = "marvell,mv78230-i2c", "marvell,mv64xxx-i2c";
|
||||
reg = <0x11100 0x100>;
|
||||
};
|
||||
|
||||
uart2: serial@12200 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x12200 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <43>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@12300 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
pinctrl-0 = <&uart3_pins>;
|
||||
pinctrl-names = "default";
|
||||
reg = <0x12300 0x100>;
|
||||
reg-shift = <2>;
|
||||
interrupts = <44>;
|
||||
reg-io-width = <1>;
|
||||
clocks = <&coreclk 0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
system-controller@18200 {
|
||||
compatible = "marvell,armada-370-xp-system-controller";
|
||||
reg = <0x18200 0x500>;
|
||||
};
|
||||
|
||||
gateclk: clock-gating-control@18220 {
|
||||
compatible = "marvell,armada-xp-gating-clock";
|
||||
reg = <0x18220 0x4>;
|
||||
clocks = <&coreclk 0>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
coreclk: mvebu-sar@18230 {
|
||||
compatible = "marvell,armada-xp-core-clock";
|
||||
reg = <0x18230 0x08>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
thermal@182b0 {
|
||||
compatible = "marvell,armadaxp-thermal";
|
||||
reg = <0x182b0 0x4
|
||||
0x184d0 0x4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
cpuclk: clock-complex@18700 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "marvell,armada-xp-cpu-clock";
|
||||
reg = <0x18700 0xA0>, <0x1c054 0x10>;
|
||||
clocks = <&coreclk 1>;
|
||||
};
|
||||
|
||||
interrupt-controller@20000 {
|
||||
reg = <0x20a00 0x2d0>, <0x21070 0x58>;
|
||||
};
|
||||
|
||||
timer@20300 {
|
||||
compatible = "marvell,armada-xp-timer";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
watchdog@20300 {
|
||||
compatible = "marvell,armada-xp-wdt";
|
||||
clocks = <&coreclk 2>, <&refclk>;
|
||||
clock-names = "nbclk", "fixed";
|
||||
};
|
||||
|
||||
cpurst@20800 {
|
||||
compatible = "marvell,armada-370-cpu-reset";
|
||||
reg = <0x20800 0x20>;
|
||||
};
|
||||
|
||||
eth2: ethernet@30000 {
|
||||
compatible = "marvell,armada-370-neta";
|
||||
reg = <0x30000 0x4000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&gateclk 2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@50000 {
|
||||
clocks = <&gateclk 18>;
|
||||
};
|
||||
|
||||
usb@51000 {
|
||||
clocks = <&gateclk 19>;
|
||||
};
|
||||
|
||||
usb@52000 {
|
||||
compatible = "marvell,orion-ehci";
|
||||
reg = <0x52000 0x500>;
|
||||
interrupts = <47>;
|
||||
clocks = <&gateclk 20>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
xor@60900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0x60900 0x100
|
||||
0x60b00 0x100>;
|
||||
clocks = <&gateclk 22>;
|
||||
status = "okay";
|
||||
|
||||
xor10 {
|
||||
interrupts = <51>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor11 {
|
||||
interrupts = <52>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
|
||||
xor@f0900 {
|
||||
compatible = "marvell,orion-xor";
|
||||
reg = <0xF0900 0x100
|
||||
0xF0B00 0x100>;
|
||||
clocks = <&gateclk 28>;
|
||||
status = "okay";
|
||||
|
||||
xor00 {
|
||||
interrupts = <94>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
};
|
||||
xor01 {
|
||||
interrupts = <95>;
|
||||
dmacap,memcpy;
|
||||
dmacap,xor;
|
||||
dmacap,memset;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
/* 25 MHz reference crystal */
|
||||
refclk: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pinctrl {
|
||||
ge0_gmii_pins: ge0-gmii-pins {
|
||||
marvell,pins =
|
||||
"mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11",
|
||||
"mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge0_rgmii_pins: ge0-rgmii-pins {
|
||||
marvell,pins =
|
||||
"mpp0", "mpp1", "mpp2", "mpp3",
|
||||
"mpp4", "mpp5", "mpp6", "mpp7",
|
||||
"mpp8", "mpp9", "mpp10", "mpp11";
|
||||
marvell,function = "ge0";
|
||||
};
|
||||
|
||||
ge1_rgmii_pins: ge1-rgmii-pins {
|
||||
marvell,pins =
|
||||
"mpp12", "mpp13", "mpp14", "mpp15",
|
||||
"mpp16", "mpp17", "mpp18", "mpp19",
|
||||
"mpp20", "mpp21", "mpp22", "mpp23";
|
||||
marvell,function = "ge1";
|
||||
};
|
||||
|
||||
sdio_pins: sdio-pins {
|
||||
marvell,pins = "mpp30", "mpp31", "mpp32",
|
||||
"mpp33", "mpp34", "mpp35";
|
||||
marvell,function = "sd0";
|
||||
};
|
||||
|
||||
spi0_pins: spi0-pins {
|
||||
marvell,pins = "mpp36", "mpp37",
|
||||
"mpp38", "mpp39";
|
||||
marvell,function = "spi";
|
||||
};
|
||||
|
||||
uart2_pins: uart2-pins {
|
||||
marvell,pins = "mpp42", "mpp43";
|
||||
marvell,function = "uart2";
|
||||
};
|
||||
|
||||
uart3_pins: uart3-pins {
|
||||
marvell,pins = "mpp44", "mpp45";
|
||||
marvell,function = "uart3";
|
||||
};
|
||||
};
|
||||
18
sys/gnu/dts/arm/armv7-m.dtsi
Normal file
18
sys/gnu/dts/arm/armv7-m.dtsi
Normal file
@ -0,0 +1,18 @@
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
nvic: nv-interrupt-controller {
|
||||
compatible = "arm,armv7m-nvic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
reg = <0xe000e100 0xc00>;
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&nvic>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
260
sys/gnu/dts/arm/at91-sama5d4ek.dts
Normal file
260
sys/gnu/dts/arm/at91-sama5d4ek.dts
Normal file
@ -0,0 +1,260 @@
|
||||
/*
|
||||
* at91-sama5d4ek.dts - Device Tree file for SAMA5D4 Evaluation Kit
|
||||
*
|
||||
* Copyright (C) 2014 Atmel,
|
||||
* 2014 Nicolas Ferre <nicolas.ferre@atmel.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
/dts-v1/;
|
||||
#include "sama5d4.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel SAMA5D4-EK";
|
||||
compatible = "atmel,sama5d4ek", "atmel,sama5d4", "atmel,sama5";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200 ignore_loglevel earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x20000000 0x20000000>;
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
main_clock: clock@0 {
|
||||
compatible = "atmel,osc", "fixed-clock";
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
slow_xtal {
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
main_xtal {
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
lcd_bus@f0000000 {
|
||||
status = "okay";
|
||||
|
||||
lcd@f0000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
lcdovl1@f0000140 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
lcdovl2@f0000240 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
lcdheo1@f0000340 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
adc0: adc@fc034000 {
|
||||
/* The vref depends on JP22 of EK. If connect 1-2 then use 3.3V. connect 2-3 use 3.0V */
|
||||
atmel,adc-vref = <3300>;
|
||||
/*atmel,adc-ts-wires = <4>;*/ /* Set up ADC touch screen */
|
||||
status = "okay"; /* Enable ADC IIO support */
|
||||
};
|
||||
|
||||
mmc0: mmc@f8000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_cd>;
|
||||
slot@1 {
|
||||
reg = <1>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioE 5 0>;
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f8010000 {
|
||||
cs-gpios = <&pioC 3 0>, <0>, <0>, <0>;
|
||||
status = "okay";
|
||||
m25p80@0 {
|
||||
compatible = "atmel,at25df321a";
|
||||
spi-max-frequency = <50000000>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@f8014000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
macb0: ethernet@f8020000 {
|
||||
phy-mode = "rmii";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc1: mmc@fc000000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3 &pinctrl_mmc1_cd>;
|
||||
status = "okay";
|
||||
slot@0 {
|
||||
reg = <0>;
|
||||
bus-width = <4>;
|
||||
cd-gpios = <&pioE 6 0>;
|
||||
};
|
||||
};
|
||||
|
||||
usart2: serial@fc008000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart3: serial@fc00c000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usart4: serial@fc010000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fc068640 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pinctrl@fc06a000 {
|
||||
board {
|
||||
pinctrl_mmc0_cd: mmc0_cd {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
pinctrl_mmc1_cd: mmc1_cd {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 6 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
|
||||
};
|
||||
pinctrl_usba_vbus: usba_vbus {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 31 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
|
||||
};
|
||||
pinctrl_key_gpio: key_gpio_0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOE 13 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PE13 gpio */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
usb0: gadget@00400000 {
|
||||
atmel,vbus-gpio = <&pioE 31 GPIO_ACTIVE_HIGH>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usba_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: ohci@00500000 {
|
||||
num-ports = <3>;
|
||||
atmel,vbus-gpio = <0 /* &pioE 10 GPIO_ACTIVE_LOW */
|
||||
&pioE 11 GPIO_ACTIVE_LOW
|
||||
&pioE 12 GPIO_ACTIVE_LOW
|
||||
>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb2: ehci@00600000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
nand0: nand@80000000 {
|
||||
nand-bus-width = <8>;
|
||||
nand-ecc-mode = "hw";
|
||||
nand-on-flash-bbt;
|
||||
atmel,has-pmecc;
|
||||
status = "okay";
|
||||
|
||||
at91bootstrap@0 {
|
||||
label = "at91bootstrap";
|
||||
reg = <0x0 0x40000>;
|
||||
};
|
||||
|
||||
bootloader@40000 {
|
||||
label = "bootloader";
|
||||
reg = <0x40000 0x80000>;
|
||||
};
|
||||
|
||||
bootloaderenv@c0000 {
|
||||
label = "bootloader env";
|
||||
reg = <0xc0000 0xc0000>;
|
||||
};
|
||||
|
||||
dtb@180000 {
|
||||
label = "device tree";
|
||||
reg = <0x180000 0x80000>;
|
||||
};
|
||||
|
||||
kernel@200000 {
|
||||
label = "kernel";
|
||||
reg = <0x200000 0x600000>;
|
||||
};
|
||||
|
||||
rootfs@800000 {
|
||||
label = "rootfs";
|
||||
reg = <0x800000 0x0f800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
gpio_keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_key_gpio>;
|
||||
|
||||
pb_user1 {
|
||||
label = "pb_user1";
|
||||
gpios = <&pioE 13 GPIO_ACTIVE_HIGH>;
|
||||
linux,code = <0x100>;
|
||||
gpio-key,wakeup;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -66,6 +66,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@00200000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00200000 0x4000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -149,7 +154,7 @@
|
||||
usb: usbck {
|
||||
compatible = "atmel,at91rm9200-clk-usb";
|
||||
#clock-cells = <0>;
|
||||
atmel,clk-divisors = <1 2>;
|
||||
atmel,clk-divisors = <1 2 0 0>;
|
||||
clocks = <&pllb>;
|
||||
};
|
||||
|
||||
@ -356,6 +361,13 @@
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
};
|
||||
|
||||
rtc: rtc@fffffe00 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
reg = <0xfffffe00 0x40>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
tcb0: timer@fffa0000 {
|
||||
compatible = "atmel,at91rm9200-tcb";
|
||||
reg = <0xfffa0000 0x100>;
|
||||
|
||||
@ -77,6 +77,10 @@
|
||||
dbgu: serial@fffff200 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc: rtc@fffffe00 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
usb0: ohci@00300000 {
|
||||
|
||||
@ -69,6 +69,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram0: sram@002ff000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x002ff000 0x2000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -956,6 +961,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
compatible = "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffd20 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&clk32k>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffd40 0x10>;
|
||||
@ -966,6 +979,12 @@
|
||||
atmel,idle-halt;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd50 {
|
||||
compatible = "atmel,at91sam9260-gpbr", "syscon";
|
||||
reg = <0xfffffd50 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
||||
@ -60,6 +60,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x28000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -828,12 +833,26 @@
|
||||
clocks = <&mck>;
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
compatible = "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffd20 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&slow_xtal>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
compatible = "atmel,at91sam9260-wdt";
|
||||
reg = <0xfffffd40 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd50 {
|
||||
compatible = "atmel,at91sam9260-gpbr", "syscon";
|
||||
reg = <0xfffffd50 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -62,6 +62,16 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram0: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x14000>;
|
||||
};
|
||||
|
||||
sram1: sram@00500000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x4000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -122,9 +132,10 @@
|
||||
interrupts-extended = <&pmc AT91_PMC_LOCKB>;
|
||||
clocks = <&main>;
|
||||
reg = <1>;
|
||||
atmel,clk-input-range = <1000000 5000000>;
|
||||
atmel,clk-input-range = <1000000 32000000>;
|
||||
#atmel,pll-clk-output-range-cells = <4>;
|
||||
atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
|
||||
atmel,pll-clk-output-ranges = <80000000 200000000 0 1>,
|
||||
<190000000 240000000 2 1>;
|
||||
};
|
||||
|
||||
mck: masterck {
|
||||
@ -293,7 +304,7 @@
|
||||
reg = <17>;
|
||||
};
|
||||
|
||||
ac91_clk: ac97_clk {
|
||||
ac97_clk: ac97_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <18>;
|
||||
};
|
||||
@ -345,10 +356,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
ramc: ramc@ffffe200 {
|
||||
ramc0: ramc@ffffe200 {
|
||||
compatible = "atmel,at91sam9260-sdramc";
|
||||
reg = <0xffffe200 0x200
|
||||
0xffffe800 0x200>;
|
||||
reg = <0xffffe200 0x200>;
|
||||
};
|
||||
|
||||
ramc1: ramc@ffffe800 {
|
||||
compatible = "atmel,at91sam9260-sdramc";
|
||||
reg = <0xffffe800 0x200>;
|
||||
};
|
||||
|
||||
pit: timer@fffffd30 {
|
||||
@ -672,6 +687,24 @@
|
||||
};
|
||||
};
|
||||
|
||||
can {
|
||||
pinctrl_can_rx_tx: can_rx_tx {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* CANRX, conflicts with IRQ0 */
|
||||
AT91_PIOA 13 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* CANTX, conflicts with PCK0 */
|
||||
};
|
||||
};
|
||||
|
||||
ac97 {
|
||||
pinctrl_ac97: ac97-0 {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 0 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A AC97FS pin */
|
||||
AT91_PIOB 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A AC97CK pin */
|
||||
AT91_PIOB 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB14 periph A AC97TX pin */
|
||||
AT91_PIOB 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A AC97RX pin */
|
||||
};
|
||||
};
|
||||
|
||||
pioA: gpio@fffff200 {
|
||||
compatible = "atmel,at91rm9200-gpio";
|
||||
reg = <0xfffff200 0x200>;
|
||||
@ -800,6 +833,17 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ac97: sound@fffa0000 {
|
||||
compatible = "atmel,at91sam9263-ac97c";
|
||||
reg = <0xfffa0000 0x4000>;
|
||||
interrupts = <18 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_ac97>;
|
||||
clocks = <&ac97_clk>;
|
||||
clock-names = "ac97_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
macb0: ethernet@fffbc000 {
|
||||
compatible = "cdns,at32ap7000-macb", "cdns,macb";
|
||||
reg = <0xfffbc000 0x100>;
|
||||
@ -834,6 +878,7 @@
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfff80000 0x600>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mci0_clk>;
|
||||
@ -845,6 +890,7 @@
|
||||
compatible = "atmel,hsmci";
|
||||
reg = <0xfff84000 0x600>;
|
||||
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
pinctrl-names = "default";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&mci1_clk>;
|
||||
@ -898,6 +944,38 @@
|
||||
clock-names = "pwm_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can: can@fffac000 {
|
||||
compatible = "atmel,at91sam9263-can";
|
||||
reg = <0xfffac000 0x300>;
|
||||
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can_rx_tx>;
|
||||
clocks = <&can_clk>;
|
||||
clock-names = "can_clk";
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
compatible = "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffd20 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&slow_xtal>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fffffd50 {
|
||||
compatible = "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffd50 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&slow_xtal>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd60 {
|
||||
compatible = "atmel,at91sam9260-gpbr", "syscon";
|
||||
reg = <0xfffffd60 0x50>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
fb0: fb@0x00700000 {
|
||||
@ -906,6 +984,8 @@
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_fb>;
|
||||
clocks = <&lcd_clk>, <&lcd_clk>;
|
||||
clock-names = "lcdc_clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
@ -16,12 +16,25 @@
|
||||
reg = <0x20000000 0x08000000>;
|
||||
};
|
||||
|
||||
sram0: sram@002ff000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram1: sram@002fc000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x002fc000 0x8000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
apb {
|
||||
i2c0: i2c@fffac000 {
|
||||
compatible = "atmel,at91sam9g20-i2c";
|
||||
};
|
||||
|
||||
ssc0: ssc@fffbc000 {
|
||||
compatible = "atmel,at91sam9rl-ssc";
|
||||
};
|
||||
|
||||
adc0: adc@fffe0000 {
|
||||
atmel,adc-startup-time = <40>;
|
||||
};
|
||||
@ -40,6 +53,7 @@
|
||||
};
|
||||
|
||||
pllb: pllbck {
|
||||
compatible = "atmel,at91sam9g20-clk-pllb";
|
||||
atmel,clk-input-range = <2000000 32000000>;
|
||||
atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
|
||||
};
|
||||
|
||||
@ -112,9 +112,23 @@
|
||||
};
|
||||
};
|
||||
|
||||
shdwc@fffffd10 {
|
||||
atmel,wakeup-counter = <10>;
|
||||
atmel,wakeup-rtt-timer;
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
watchdog@fffffd40 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd50 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
nand0: nand@40000000 {
|
||||
|
||||
@ -74,6 +74,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x10000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -96,8 +101,14 @@
|
||||
|
||||
ramc0: ramc@ffffe400 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe400 0x200
|
||||
0xffffe600 0x200>;
|
||||
reg = <0xffffe400 0x200>;
|
||||
clocks = <&ddrck>;
|
||||
clock-names = "ddrck";
|
||||
};
|
||||
|
||||
ramc1: ramc@ffffe600 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe600 0x200>;
|
||||
clocks = <&ddrck>;
|
||||
clock-names = "ddrck";
|
||||
};
|
||||
@ -159,7 +170,7 @@
|
||||
compatible = "atmel,at91rm9200-clk-master";
|
||||
#clock-cells = <0>;
|
||||
interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>;
|
||||
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
|
||||
atmel,clk-output-range = <0 133333333>;
|
||||
atmel,clk-divisors = <1 2 4 3>;
|
||||
};
|
||||
@ -175,7 +186,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&pmc>;
|
||||
clocks = <&slow_xtal>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
||||
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
||||
|
||||
prog0: prog0 {
|
||||
#clock-cells = <0>;
|
||||
@ -486,6 +497,27 @@
|
||||
};
|
||||
};
|
||||
|
||||
isi {
|
||||
pinctrl_isi: isi-0 {
|
||||
atmel,pins = <AT91_PIOB 8 AT91_PERIPH_B AT91_PINCTRL_NONE /* D8 */
|
||||
AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* D9 */
|
||||
AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* D10 */
|
||||
AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE /* D11 */
|
||||
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* D0 */
|
||||
AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* D1 */
|
||||
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* D2 */
|
||||
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* D3 */
|
||||
AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* D4 */
|
||||
AT91_PIOB 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* D5 */
|
||||
AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* D6 */
|
||||
AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* D7 */
|
||||
AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PCK */
|
||||
AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* VSYNC */
|
||||
AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* HSYNC */
|
||||
AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_NONE /* MCK */>;
|
||||
};
|
||||
};
|
||||
|
||||
usart0 {
|
||||
pinctrl_usart0: usart0-0 {
|
||||
atmel,pins =
|
||||
@ -934,6 +966,13 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
trng@fffcc000 {
|
||||
compatible = "atmel,at91sam9g45-trng";
|
||||
reg = <0xfffcc000 0x4000>;
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&trng_clk>;
|
||||
};
|
||||
|
||||
i2c0: i2c@fff84000 {
|
||||
compatible = "atmel,at91sam9g10-i2c";
|
||||
reg = <0xfff84000 0x100>;
|
||||
@ -1022,6 +1061,17 @@
|
||||
};
|
||||
};
|
||||
|
||||
isi@fffb4000 {
|
||||
compatible = "atmel,at91sam9g45-isi";
|
||||
reg = <0xfffb4000 0x4000>;
|
||||
interrupts = <26 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
clocks = <&isi_clk>;
|
||||
clock-names = "isi_clk";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_isi>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@fffb8000 {
|
||||
compatible = "atmel,at91sam9rl-pwm";
|
||||
reg = <0xfffb8000 0x300>;
|
||||
@ -1159,6 +1209,53 @@
|
||||
atmel,can-isoc;
|
||||
};
|
||||
};
|
||||
|
||||
sckc@fffffd50 {
|
||||
compatible = "atmel,at91sam9x5-sckc";
|
||||
reg = <0xfffffd50 0x4>;
|
||||
|
||||
slow_osc: slow_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-osc";
|
||||
#clock-cells = <0>;
|
||||
atmel,startup-time-usec = <1200000>;
|
||||
clocks = <&slow_xtal>;
|
||||
};
|
||||
|
||||
slow_rc_osc: slow_rc_osc {
|
||||
compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
|
||||
#clock-cells = <0>;
|
||||
atmel,startup-time-usec = <75>;
|
||||
clock-frequency = <32768>;
|
||||
clock-accuracy = <50000000>;
|
||||
};
|
||||
|
||||
clk32k: slck {
|
||||
compatible = "atmel,at91sam9x5-clk-slow";
|
||||
#clock-cells = <0>;
|
||||
clocks = <&slow_rc_osc &slow_osc>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
compatible = "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffd20 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&clk32k>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fffffdb0 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
reg = <0xfffffdb0 0x30>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd60 {
|
||||
compatible = "atmel,at91sam9260-gpbr", "syscon";
|
||||
reg = <0xfffffd60 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
fb0: fb@0x00500000 {
|
||||
@ -1195,7 +1292,6 @@
|
||||
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
||||
reg = <0x00700000 0x100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
//TODO
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
@ -1205,7 +1301,6 @@
|
||||
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
||||
reg = <0x00800000 0x100000>;
|
||||
interrupts = <22 IRQ_TYPE_LEVEL_HIGH 2>;
|
||||
//TODO
|
||||
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
|
||||
clock-names = "usb_clk", "ehci_clk", "hclk", "uhpck";
|
||||
status = "disabled";
|
||||
|
||||
@ -160,6 +160,19 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm_leds>;
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd60 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
rtc@fffffdb0 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
fb0: fb@0x00500000 {
|
||||
|
||||
@ -64,6 +64,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x8000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -87,6 +92,8 @@
|
||||
ramc0: ramc@ffffe800 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe800 0x200>;
|
||||
clocks = <&ddrck>;
|
||||
clock-names = "ddrck";
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
@ -891,6 +898,13 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
reg = <0xfffffeb0 0x40>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm0: pwm@f8034000 {
|
||||
compatible = "atmel,at91sam9rl-pwm";
|
||||
reg = <0xf8034000 0x300>;
|
||||
|
||||
@ -54,7 +54,7 @@
|
||||
status = "okay";
|
||||
|
||||
wm8904: codec@1a {
|
||||
compatible = "wm8904";
|
||||
compatible = "wlf,wm8904";
|
||||
reg = <0x1a>;
|
||||
clocks = <&pck0>;
|
||||
clock-names = "mclk";
|
||||
@ -136,6 +136,8 @@
|
||||
};
|
||||
|
||||
usb0: ohci@00500000 {
|
||||
num-ports = <1>;
|
||||
atmel,vbus-gpio = <&pioB 7 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
@ -70,6 +70,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x10000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -204,7 +209,7 @@
|
||||
};
|
||||
|
||||
ssc0: ssc@fffc0000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
compatible = "atmel,at91sam9rl-ssc";
|
||||
reg = <0xfffc0000 0x4000>;
|
||||
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
@ -213,7 +218,7 @@
|
||||
};
|
||||
|
||||
ssc1: ssc@fffc4000 {
|
||||
compatible = "atmel,at91rm9200-ssc";
|
||||
compatible = "atmel,at91sam9rl-ssc";
|
||||
reg = <0xfffc4000 0x4000>;
|
||||
interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
@ -1059,6 +1064,27 @@
|
||||
clocks = <&slow_rc_osc &slow_osc>;
|
||||
};
|
||||
};
|
||||
|
||||
rtc@fffffeb0 {
|
||||
compatible = "atmel,at91rm9200-rtc";
|
||||
reg = <0xfffffeb0 0x40>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
rtc@fffffd20 {
|
||||
compatible = "atmel,at91sam9260-rtt";
|
||||
reg = <0xfffffd20 0x10>;
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
clocks = <&clk32k>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpbr: syscon@fffffd60 {
|
||||
compatible = "atmel,at91sam9260-gpbr", "syscon";
|
||||
reg = <0xfffffd60 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
@ -10,6 +10,7 @@
|
||||
#include "at91sam9x5_usart3.dtsi"
|
||||
#include "at91sam9x5_macb0.dtsi"
|
||||
#include "at91sam9x5_macb1.dtsi"
|
||||
#include "at91sam9x5_can.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X25 SoC";
|
||||
|
||||
@ -8,6 +8,7 @@
|
||||
|
||||
#include "at91sam9x5.dtsi"
|
||||
#include "at91sam9x5_macb0.dtsi"
|
||||
#include "at91sam9x5_can.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9X35 SoC";
|
||||
|
||||
@ -72,6 +72,11 @@
|
||||
};
|
||||
};
|
||||
|
||||
sram: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x8000>;
|
||||
};
|
||||
|
||||
ahb {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
@ -95,6 +100,8 @@
|
||||
ramc0: ramc@ffffe800 {
|
||||
compatible = "atmel,at91sam9g45-ddramc";
|
||||
reg = <0xffffe800 0x200>;
|
||||
clocks = <&ddrck>;
|
||||
clock-names = "ddrck";
|
||||
};
|
||||
|
||||
pmc: pmc@fffffc00 {
|
||||
@ -858,6 +865,9 @@
|
||||
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dbgu>;
|
||||
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(8)>,
|
||||
<&dma1 1 (AT91_DMA_CFG_PER_ID(9) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&mck>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
@ -869,6 +879,9 @@
|
||||
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart0>;
|
||||
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(3)>,
|
||||
<&dma0 1 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&usart0_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
@ -880,6 +893,9 @@
|
||||
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart1>;
|
||||
dmas = <&dma0 1 AT91_DMA_CFG_PER_ID(5)>,
|
||||
<&dma0 1 (AT91_DMA_CFG_PER_ID(6) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&usart1_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
@ -891,6 +907,9 @@
|
||||
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart2>;
|
||||
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(12)>,
|
||||
<&dma1 1 (AT91_DMA_CFG_PER_ID(13) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&usart2_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
@ -966,7 +985,7 @@
|
||||
adc0: adc@f804c000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "atmel,at91sam9260-adc";
|
||||
compatible = "atmel,at91sam9x5-adc";
|
||||
reg = <0xf804c000 0x100>;
|
||||
interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
|
||||
clocks = <&adc_clk>,
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/*
|
||||
* at91sam9x5_macb0.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
|
||||
* at91sam9x5_can.dtsi - Device Tree Include file for AT91SAM9x5 SoC with 1
|
||||
* Ethernet interface.
|
||||
*
|
||||
* Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
|
||||
@ -20,10 +20,50 @@
|
||||
reg = <29>;
|
||||
};
|
||||
|
||||
can1_clk: can1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <30>;
|
||||
};
|
||||
can1_clk: can1_clk {
|
||||
#clock-cells = <0>;
|
||||
reg = <30>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
can0: can@f8000000 {
|
||||
compatible = "atmel,at91sam9x5-can";
|
||||
reg = <0xf8000000 0x300>;
|
||||
interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can0_rx_tx>;
|
||||
clocks = <&can0_clk>;
|
||||
clock-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@f8004000 {
|
||||
compatible = "atmel,at91sam9x5-can";
|
||||
reg = <0xf8004000 0x300>;
|
||||
interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_can1_rx_tx>;
|
||||
clocks = <&can1_clk>;
|
||||
clock-names = "can_clk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl@fffff400 {
|
||||
can0 {
|
||||
pinctrl_can0_rx_tx: can0_rx_tx {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX0, conflicts with DRXD */
|
||||
AT91_PIOA 10 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX0, conflicts with DTXD */
|
||||
};
|
||||
};
|
||||
|
||||
can1 {
|
||||
pinctrl_can1_rx_tx: can1_rx_tx {
|
||||
atmel,pins =
|
||||
<AT91_PIOA 6 AT91_PERIPH_B AT91_PINCTRL_NONE /* CANRX1, conflicts with RXD1 */
|
||||
AT91_PIOA 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* CANTX1, conflicts with TXD1 */
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -57,6 +57,9 @@
|
||||
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usart3>;
|
||||
dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
|
||||
<&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
|
||||
dma-names = "tx", "rx";
|
||||
clocks = <&usart3_clk>;
|
||||
clock-names = "usart";
|
||||
status = "disabled";
|
||||
|
||||
@ -53,6 +53,8 @@
|
||||
};
|
||||
|
||||
usb2: gadget@f803c000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_board_usb2>;
|
||||
atmel,vbus-gpio = <&pioB 16 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
@ -80,6 +82,13 @@
|
||||
<AT91_PIOD 14 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>; /* PD14 gpio CD pin pull up and deglitch */
|
||||
};
|
||||
};
|
||||
|
||||
usb2 {
|
||||
pinctrl_board_usb2: usb2-board {
|
||||
atmel,pins =
|
||||
<AT91_PIOB 16 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>; /* PB16 gpio vbus sense, deglitch */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
spi0: spi@f0000000 {
|
||||
|
||||
60
sys/gnu/dts/arm/at91sam9xe.dtsi
Normal file
60
sys/gnu/dts/arm/at91sam9xe.dtsi
Normal file
@ -0,0 +1,60 @@
|
||||
/*
|
||||
* at91sam9xe.dtsi - Device Tree Include file for AT91SAM9XE family SoC
|
||||
*
|
||||
* Copyright (C) 2015 Atmel,
|
||||
* 2015 Alexandre Belloni <alexandre.Belloni@free-electrons.com>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "at91sam9260.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Atmel AT91SAM9XE family SoC";
|
||||
compatible = "atmel,at91sam9xe", "atmel,at91sam9260";
|
||||
|
||||
sram0: sram@002ff000 {
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sram1: sram@00300000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00300000 0x4000>;
|
||||
};
|
||||
};
|
||||
78
sys/gnu/dts/arm/atlas6-evb.dts
Normal file
78
sys/gnu/dts/arm/atlas6-evb.dts
Normal file
@ -0,0 +1,78 @@
|
||||
/*
|
||||
* DTS file for CSR SiRFatlas6 Evaluation Board
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "atlas6.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CSR SiRFatlas6 Evaluation Board";
|
||||
compatible = "sirf,atlas6-cb", "sirf,atlas6";
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x20000000>;
|
||||
};
|
||||
|
||||
axi {
|
||||
peri-iobg {
|
||||
uart@b0060000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart1_pins_a>;
|
||||
};
|
||||
spi@b00d0000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi0_pins_a>;
|
||||
spi@0 {
|
||||
compatible = "spidev";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <1000000>;
|
||||
};
|
||||
};
|
||||
spi@b0170000 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&spi1_pins_a>;
|
||||
};
|
||||
i2c0: i2c@b00e0000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&i2c0_pins_a>;
|
||||
lcd@40 {
|
||||
compatible = "sirf,lcd";
|
||||
reg = <0x40>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
disp-iobg {
|
||||
lcd@90010000 {
|
||||
status = "okay";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&lcd_24pins_a>;
|
||||
};
|
||||
};
|
||||
};
|
||||
display: display@0 {
|
||||
panels {
|
||||
panel0: panel@0 {
|
||||
panel-name = "Innolux TFT";
|
||||
hactive = <800>;
|
||||
vactive = <480>;
|
||||
left_margin = <20>;
|
||||
right_margin = <234>;
|
||||
upper_margin = <3>;
|
||||
lower_margin = <41>;
|
||||
hsync_len = <3>;
|
||||
vsync_len = <2>;
|
||||
pixclock = <33264000>;
|
||||
sync = <3>;
|
||||
timing = <0x88>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
802
sys/gnu/dts/arm/atlas6.dtsi
Normal file
802
sys/gnu/dts/arm/atlas6.dtsi
Normal file
@ -0,0 +1,802 @@
|
||||
/*
|
||||
* DTS file for CSR SiRFatlas6 SoC
|
||||
*
|
||||
* Copyright (c) 2012 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
compatible = "sirf,atlas6";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <32768>;
|
||||
i-cache-size = <32768>;
|
||||
/* from bootloader */
|
||||
timebase-frequency = <0>;
|
||||
bus-frequency = <0>;
|
||||
clock-frequency = <0>;
|
||||
clocks = <&clks 12>;
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
200000 1025000
|
||||
400000 1025000
|
||||
600000 1050000
|
||||
800000 1100000
|
||||
>;
|
||||
clock-latency = <150000>;
|
||||
};
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,cortex-a9-pmu";
|
||||
interrupts = <29>;
|
||||
};
|
||||
|
||||
axi {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x40000000 0x40000000 0x80000000>;
|
||||
|
||||
intc: interrupt-controller@80020000 {
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "sirf,prima2-intc";
|
||||
reg = <0x80020000 0x1000>;
|
||||
};
|
||||
|
||||
sys-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x88000000 0x88000000 0x40000>;
|
||||
|
||||
clks: clock-controller@88000000 {
|
||||
compatible = "sirf,atlas6-clkc";
|
||||
reg = <0x88000000 0x1000>;
|
||||
interrupts = <3>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
rstc: reset-controller@88010000 {
|
||||
compatible = "sirf,prima2-rstc";
|
||||
reg = <0x88010000 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
rsc-controller@88020000 {
|
||||
compatible = "sirf,prima2-rsc";
|
||||
reg = <0x88020000 0x1000>;
|
||||
};
|
||||
|
||||
cphifbg@88030000 {
|
||||
compatible = "sirf,prima2-cphifbg";
|
||||
reg = <0x88030000 0x1000>;
|
||||
clocks = <&clks 42>;
|
||||
};
|
||||
};
|
||||
|
||||
mem-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90000000 0x90000000 0x10000>;
|
||||
|
||||
memory-controller@90000000 {
|
||||
compatible = "sirf,prima2-memc";
|
||||
reg = <0x90000000 0x2000>;
|
||||
interrupts = <27>;
|
||||
clocks = <&clks 5>;
|
||||
};
|
||||
|
||||
memc-monitor {
|
||||
compatible = "sirf,prima2-memcmon";
|
||||
reg = <0x90002000 0x200>;
|
||||
interrupts = <4>;
|
||||
clocks = <&clks 32>;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x90010000 0x90010000 0x30000>;
|
||||
|
||||
lcd@90010000 {
|
||||
compatible = "sirf,prima2-lcd";
|
||||
reg = <0x90010000 0x20000>;
|
||||
interrupts = <30>;
|
||||
clocks = <&clks 34>;
|
||||
display=<&display>;
|
||||
/* later transfer to pwm */
|
||||
bl-gpio = <&gpio 7 0>;
|
||||
default-panel = <&panel0>;
|
||||
};
|
||||
|
||||
vpp@90020000 {
|
||||
compatible = "sirf,prima2-vpp";
|
||||
reg = <0x90020000 0x10000>;
|
||||
interrupts = <31>;
|
||||
clocks = <&clks 35>;
|
||||
resets = <&rstc 6>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x98000000 0x98000000 0x8000000>;
|
||||
|
||||
graphics@98000000 {
|
||||
compatible = "powervr,sgx510";
|
||||
reg = <0x98000000 0x8000000>;
|
||||
interrupts = <6>;
|
||||
clocks = <&clks 32>;
|
||||
};
|
||||
};
|
||||
|
||||
graphics2d-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa0000000 0xa0000000 0x8000000>;
|
||||
|
||||
ble@a0000000 {
|
||||
compatible = "sirf,atlas6-ble";
|
||||
reg = <0xa0000000 0x2000>;
|
||||
interrupts = <5>;
|
||||
clocks = <&clks 33>;
|
||||
};
|
||||
};
|
||||
|
||||
dsp-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xa8000000 0xa8000000 0x2000000>;
|
||||
|
||||
dspif@a8000000 {
|
||||
compatible = "sirf,prima2-dspif";
|
||||
reg = <0xa8000000 0x10000>;
|
||||
interrupts = <9>;
|
||||
resets = <&rstc 1>;
|
||||
};
|
||||
|
||||
gps@a8010000 {
|
||||
compatible = "sirf,prima2-gps";
|
||||
reg = <0xa8010000 0x10000>;
|
||||
interrupts = <7>;
|
||||
clocks = <&clks 9>;
|
||||
resets = <&rstc 2>;
|
||||
};
|
||||
|
||||
dsp@a9000000 {
|
||||
compatible = "sirf,prima2-dsp";
|
||||
reg = <0xa9000000 0x1000000>;
|
||||
interrupts = <8>;
|
||||
clocks = <&clks 8>;
|
||||
resets = <&rstc 0>;
|
||||
};
|
||||
};
|
||||
|
||||
peri-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0xb0000000 0x180000>,
|
||||
<0x56000000 0x56000000 0x1b00000>;
|
||||
|
||||
timer@b0020000 {
|
||||
compatible = "sirf,prima2-tick";
|
||||
reg = <0xb0020000 0x1000>;
|
||||
interrupts = <0>;
|
||||
clocks = <&clks 11>;
|
||||
};
|
||||
|
||||
nand@b0030000 {
|
||||
compatible = "sirf,prima2-nand";
|
||||
reg = <0xb0030000 0x10000>;
|
||||
interrupts = <41>;
|
||||
clocks = <&clks 26>;
|
||||
};
|
||||
|
||||
audio@b0040000 {
|
||||
compatible = "sirf,prima2-audio";
|
||||
reg = <0xb0040000 0x10000>;
|
||||
interrupts = <35>;
|
||||
clocks = <&clks 27>;
|
||||
};
|
||||
|
||||
uart0: uart@b0050000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0050000 0x1000>;
|
||||
interrupts = <17>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 13>;
|
||||
dmas = <&dmac1 5>, <&dmac0 2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
uart1: uart@b0060000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0060000 0x1000>;
|
||||
interrupts = <18>;
|
||||
fifosize = <32>;
|
||||
clocks = <&clks 14>;
|
||||
dma-names = "no-rx", "no-tx";
|
||||
};
|
||||
|
||||
uart2: uart@b0070000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-uart";
|
||||
reg = <0xb0070000 0x1000>;
|
||||
interrupts = <19>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 15>;
|
||||
dmas = <&dmac0 6>, <&dmac0 7>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
usp0: usp@b0080000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0080000 0x10000>;
|
||||
interrupts = <20>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 28>;
|
||||
dmas = <&dmac1 1>, <&dmac1 2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
usp1: usp@b0090000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-usp";
|
||||
reg = <0xb0090000 0x10000>;
|
||||
interrupts = <21>;
|
||||
fifosize = <128>;
|
||||
clocks = <&clks 29>;
|
||||
dmas = <&dmac0 14>, <&dmac0 15>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
dmac0: dma-controller@b00b0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb00b0000 0x10000>;
|
||||
interrupts = <12>;
|
||||
clocks = <&clks 24>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac1: dma-controller@b0160000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-dmac";
|
||||
reg = <0xb0160000 0x10000>;
|
||||
interrupts = <13>;
|
||||
clocks = <&clks 25>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
vip@b00C0000 {
|
||||
compatible = "sirf,prima2-vip";
|
||||
reg = <0xb00C0000 0x10000>;
|
||||
clocks = <&clks 31>;
|
||||
interrupts = <14>;
|
||||
sirf,vip-dma-rx-channel = <16>;
|
||||
};
|
||||
|
||||
spi0: spi@b00d0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb00d0000 0x10000>;
|
||||
interrupts = <15>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
dmas = <&dmac1 9>,
|
||||
<&dmac1 4>;
|
||||
dma-names = "rx", "tx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 19>;
|
||||
resets = <&rstc 26>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@b0170000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0xb0170000 0x10000>;
|
||||
interrupts = <16>;
|
||||
sirf,spi-num-chipselects = <1>;
|
||||
dmas = <&dmac0 12>,
|
||||
<&dmac0 13>;
|
||||
dma-names = "rx", "tx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 20>;
|
||||
resets = <&rstc 27>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@b00e0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00e0000 0x10000>;
|
||||
interrupts = <24>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 17>;
|
||||
};
|
||||
|
||||
i2c1: i2c@b00f0000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0xb00f0000 0x10000>;
|
||||
interrupts = <25>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&clks 18>;
|
||||
};
|
||||
|
||||
tsc@b0110000 {
|
||||
compatible = "sirf,prima2-tsc";
|
||||
reg = <0xb0110000 0x10000>;
|
||||
interrupts = <33>;
|
||||
clocks = <&clks 16>;
|
||||
};
|
||||
|
||||
gpio: pinctrl@b0120000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas6-pinctrl";
|
||||
reg = <0xb0120000 0x10000>;
|
||||
interrupts = <43 44 45 46 47>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
|
||||
lcd_16pins_a: lcd0@0 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_16bitsgrp";
|
||||
sirf,function = "lcd_16bits";
|
||||
};
|
||||
};
|
||||
lcd_18pins_a: lcd0@1 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_18bitsgrp";
|
||||
sirf,function = "lcd_18bits";
|
||||
};
|
||||
};
|
||||
lcd_24pins_a: lcd0@2 {
|
||||
lcd {
|
||||
sirf,pins = "lcd_24bitsgrp";
|
||||
sirf,function = "lcd_24bits";
|
||||
};
|
||||
};
|
||||
lcdrom_pins_a: lcdrom0@0 {
|
||||
lcd {
|
||||
sirf,pins = "lcdromgrp";
|
||||
sirf,function = "lcdrom";
|
||||
};
|
||||
};
|
||||
uart0_pins_a: uart0@0 {
|
||||
uart {
|
||||
sirf,pins = "uart0grp";
|
||||
sirf,function = "uart0";
|
||||
};
|
||||
};
|
||||
uart0_noflow_pins_a: uart0@1 {
|
||||
uart {
|
||||
sirf,pins = "uart0_nostreamctrlgrp";
|
||||
sirf,function = "uart0_nostreamctrl";
|
||||
};
|
||||
};
|
||||
uart1_pins_a: uart1@0 {
|
||||
uart {
|
||||
sirf,pins = "uart1grp";
|
||||
sirf,function = "uart1";
|
||||
};
|
||||
};
|
||||
uart2_pins_a: uart2@0 {
|
||||
uart {
|
||||
sirf,pins = "uart2grp";
|
||||
sirf,function = "uart2";
|
||||
};
|
||||
};
|
||||
uart2_noflow_pins_a: uart2@1 {
|
||||
uart {
|
||||
sirf,pins = "uart2_nostreamctrlgrp";
|
||||
sirf,function = "uart2_nostreamctrl";
|
||||
};
|
||||
};
|
||||
spi0_pins_a: spi0@0 {
|
||||
spi {
|
||||
sirf,pins = "spi0grp";
|
||||
sirf,function = "spi0";
|
||||
};
|
||||
};
|
||||
spi1_pins_a: spi1@0 {
|
||||
spi {
|
||||
sirf,pins = "spi1grp";
|
||||
sirf,function = "spi1";
|
||||
};
|
||||
};
|
||||
i2c0_pins_a: i2c0@0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c0grp";
|
||||
sirf,function = "i2c0";
|
||||
};
|
||||
};
|
||||
i2c1_pins_a: i2c1@0 {
|
||||
i2c {
|
||||
sirf,pins = "i2c1grp";
|
||||
sirf,function = "i2c1";
|
||||
};
|
||||
};
|
||||
pwm0_pins_a: pwm0@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm0grp";
|
||||
sirf,function = "pwm0";
|
||||
};
|
||||
};
|
||||
pwm1_pins_a: pwm1@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm1grp";
|
||||
sirf,function = "pwm1";
|
||||
};
|
||||
};
|
||||
pwm2_pins_a: pwm2@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm2grp";
|
||||
sirf,function = "pwm2";
|
||||
};
|
||||
};
|
||||
pwm3_pins_a: pwm3@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm3grp";
|
||||
sirf,function = "pwm3";
|
||||
};
|
||||
};
|
||||
pwm4_pins_a: pwm4@0 {
|
||||
pwm {
|
||||
sirf,pins = "pwm4grp";
|
||||
sirf,function = "pwm4";
|
||||
};
|
||||
};
|
||||
gps_pins_a: gps@0 {
|
||||
gps {
|
||||
sirf,pins = "gpsgrp";
|
||||
sirf,function = "gps";
|
||||
};
|
||||
};
|
||||
vip_pins_a: vip@0 {
|
||||
vip {
|
||||
sirf,pins = "vipgrp";
|
||||
sirf,function = "vip";
|
||||
};
|
||||
};
|
||||
sdmmc0_pins_a: sdmmc0@0 {
|
||||
sdmmc0 {
|
||||
sirf,pins = "sdmmc0grp";
|
||||
sirf,function = "sdmmc0";
|
||||
};
|
||||
};
|
||||
sdmmc1_pins_a: sdmmc1@0 {
|
||||
sdmmc1 {
|
||||
sirf,pins = "sdmmc1grp";
|
||||
sirf,function = "sdmmc1";
|
||||
};
|
||||
};
|
||||
sdmmc2_pins_a: sdmmc2@0 {
|
||||
sdmmc2 {
|
||||
sirf,pins = "sdmmc2grp";
|
||||
sirf,function = "sdmmc2";
|
||||
};
|
||||
};
|
||||
sdmmc2_nowp_pins_a: sdmmc2_nowp@0 {
|
||||
sdmmc2_nowp {
|
||||
sirf,pins = "sdmmc2_nowpgrp";
|
||||
sirf,function = "sdmmc2_nowp";
|
||||
};
|
||||
};
|
||||
sdmmc3_pins_a: sdmmc3@0 {
|
||||
sdmmc3 {
|
||||
sirf,pins = "sdmmc3grp";
|
||||
sirf,function = "sdmmc3";
|
||||
};
|
||||
};
|
||||
sdmmc5_pins_a: sdmmc5@0 {
|
||||
sdmmc5 {
|
||||
sirf,pins = "sdmmc5grp";
|
||||
sirf,function = "sdmmc5";
|
||||
};
|
||||
};
|
||||
i2s_mclk_pins_a: i2s_mclk@0 {
|
||||
i2s_mclk {
|
||||
sirf,pins = "i2smclkgrp";
|
||||
sirf,function = "i2s_mclk";
|
||||
};
|
||||
};
|
||||
i2s_ext_clk_input_pins_a: i2s_ext_clk_input@0 {
|
||||
i2s_ext_clk_input {
|
||||
sirf,pins = "i2s_ext_clk_inputgrp";
|
||||
sirf,function = "i2s_ext_clk_input";
|
||||
};
|
||||
};
|
||||
i2s_pins_a: i2s@0 {
|
||||
i2s {
|
||||
sirf,pins = "i2sgrp";
|
||||
sirf,function = "i2s";
|
||||
};
|
||||
};
|
||||
i2s_no_din_pins_a: i2s_no_din@0 {
|
||||
i2s_no_din {
|
||||
sirf,pins = "i2s_no_dingrp";
|
||||
sirf,function = "i2s_no_din";
|
||||
};
|
||||
};
|
||||
i2s_6chn_pins_a: i2s_6chn@0 {
|
||||
i2s_6chn {
|
||||
sirf,pins = "i2s_6chngrp";
|
||||
sirf,function = "i2s_6chn";
|
||||
};
|
||||
};
|
||||
ac97_pins_a: ac97@0 {
|
||||
ac97 {
|
||||
sirf,pins = "ac97grp";
|
||||
sirf,function = "ac97";
|
||||
};
|
||||
};
|
||||
nand_pins_a: nand@0 {
|
||||
nand {
|
||||
sirf,pins = "nandgrp";
|
||||
sirf,function = "nand";
|
||||
};
|
||||
};
|
||||
usp0_pins_a: usp0@0 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0grp";
|
||||
sirf,function = "usp0";
|
||||
};
|
||||
};
|
||||
usp0_uart_nostreamctrl_pins_a: usp0@1 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0_uart_nostreamctrl_grp";
|
||||
sirf,function = "usp0_uart_nostreamctrl";
|
||||
};
|
||||
};
|
||||
usp0_only_utfs_pins_a: usp0@2 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0_only_utfs_grp";
|
||||
sirf,function = "usp0_only_utfs";
|
||||
};
|
||||
};
|
||||
usp0_only_urfs_pins_a: usp0@3 {
|
||||
usp0 {
|
||||
sirf,pins = "usp0_only_urfs_grp";
|
||||
sirf,function = "usp0_only_urfs";
|
||||
};
|
||||
};
|
||||
usp1_pins_a: usp1@0 {
|
||||
usp1 {
|
||||
sirf,pins = "usp1grp";
|
||||
sirf,function = "usp1";
|
||||
};
|
||||
};
|
||||
usp1_uart_nostreamctrl_pins_a: usp1@1 {
|
||||
usp1 {
|
||||
sirf,pins = "usp1_uart_nostreamctrl_grp";
|
||||
sirf,function = "usp1_uart_nostreamctrl";
|
||||
};
|
||||
};
|
||||
usb0_upli_drvbus_pins_a: usb0_upli_drvbus@0 {
|
||||
usb0_upli_drvbus {
|
||||
sirf,pins = "usb0_upli_drvbusgrp";
|
||||
sirf,function = "usb0_upli_drvbus";
|
||||
};
|
||||
};
|
||||
usb1_utmi_drvbus_pins_a: usb1_utmi_drvbus@0 {
|
||||
usb1_utmi_drvbus {
|
||||
sirf,pins = "usb1_utmi_drvbusgrp";
|
||||
sirf,function = "usb1_utmi_drvbus";
|
||||
};
|
||||
};
|
||||
usb1_dp_dn_pins_a: usb1_dp_dn@0 {
|
||||
usb1_dp_dn {
|
||||
sirf,pins = "usb1_dp_dngrp";
|
||||
sirf,function = "usb1_dp_dn";
|
||||
};
|
||||
};
|
||||
uart1_route_io_usb1_pins_a: uart1_route_io_usb1@0 {
|
||||
uart1_route_io_usb1 {
|
||||
sirf,pins = "uart1_route_io_usb1grp";
|
||||
sirf,function = "uart1_route_io_usb1";
|
||||
};
|
||||
};
|
||||
warm_rst_pins_a: warm_rst@0 {
|
||||
warm_rst {
|
||||
sirf,pins = "warm_rstgrp";
|
||||
sirf,function = "warm_rst";
|
||||
};
|
||||
};
|
||||
pulse_count_pins_a: pulse_count@0 {
|
||||
pulse_count {
|
||||
sirf,pins = "pulse_countgrp";
|
||||
sirf,function = "pulse_count";
|
||||
};
|
||||
};
|
||||
cko0_pins_a: cko0@0 {
|
||||
cko0 {
|
||||
sirf,pins = "cko0grp";
|
||||
sirf,function = "cko0";
|
||||
};
|
||||
};
|
||||
cko1_pins_a: cko1@0 {
|
||||
cko1 {
|
||||
sirf,pins = "cko1grp";
|
||||
sirf,function = "cko1";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pwm@b0130000 {
|
||||
compatible = "sirf,prima2-pwm";
|
||||
reg = <0xb0130000 0x10000>;
|
||||
clocks = <&clks 21>;
|
||||
};
|
||||
|
||||
efusesys@b0140000 {
|
||||
compatible = "sirf,prima2-efuse";
|
||||
reg = <0xb0140000 0x10000>;
|
||||
clocks = <&clks 22>;
|
||||
};
|
||||
|
||||
pulsec@b0150000 {
|
||||
compatible = "sirf,prima2-pulsec";
|
||||
reg = <0xb0150000 0x10000>;
|
||||
interrupts = <48>;
|
||||
clocks = <&clks 23>;
|
||||
};
|
||||
|
||||
pci-iobg {
|
||||
compatible = "sirf,prima2-pciiobg", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x56000000 0x56000000 0x1b00000>;
|
||||
|
||||
sd0: sdhci@56000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56000000 0x100000>;
|
||||
interrupts = <38>;
|
||||
bus-width = <8>;
|
||||
clocks = <&clks 36>;
|
||||
};
|
||||
|
||||
sd1: sdhci@56100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56100000 0x100000>;
|
||||
interrupts = <38>;
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
clocks = <&clks 36>;
|
||||
};
|
||||
|
||||
sd2: sdhci@56200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56200000 0x100000>;
|
||||
interrupts = <23>;
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
clocks = <&clks 37>;
|
||||
};
|
||||
|
||||
sd3: sdhci@56300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56300000 0x100000>;
|
||||
interrupts = <23>;
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
clocks = <&clks 37>;
|
||||
};
|
||||
|
||||
sd5: sdhci@56500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,prima2-sdhc";
|
||||
reg = <0x56500000 0x100000>;
|
||||
interrupts = <39>;
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
clocks = <&clks 38>;
|
||||
};
|
||||
|
||||
pci-copy@57900000 {
|
||||
compatible = "sirf,prima2-pcicp";
|
||||
reg = <0x57900000 0x100000>;
|
||||
interrupts = <40>;
|
||||
};
|
||||
|
||||
rom-interface@57a00000 {
|
||||
compatible = "sirf,prima2-romif";
|
||||
reg = <0x57a00000 0x100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rtc-iobg {
|
||||
compatible = "sirf,prima2-rtciobg", "sirf-prima2-rtciobg-bus", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x80030000 0x10000>;
|
||||
|
||||
gpsrtc@1000 {
|
||||
compatible = "sirf,prima2-gpsrtc";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <55 56 57>;
|
||||
};
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,prima2-sysrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <52 53 54>;
|
||||
};
|
||||
|
||||
minigpsrtc@2000 {
|
||||
compatible = "sirf,prima2-minigpsrtc";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <54>;
|
||||
};
|
||||
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,prima2-pwrc";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
uus-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb8000000 0xb8000000 0x40000>;
|
||||
|
||||
usb0: usb@b00e0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8000000 0x10000>;
|
||||
interrupts = <10>;
|
||||
clocks = <&clks 40>;
|
||||
};
|
||||
|
||||
usb1: usb@b00f0000 {
|
||||
compatible = "chipidea,ci13611a-prima2";
|
||||
reg = <0xb8010000 0x10000>;
|
||||
interrupts = <11>;
|
||||
clocks = <&clks 41>;
|
||||
};
|
||||
|
||||
security@b00f0000 {
|
||||
compatible = "sirf,prima2-security";
|
||||
reg = <0xb8030000 0x10000>;
|
||||
interrupts = <42>;
|
||||
clocks = <&clks 7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
110
sys/gnu/dts/arm/atlas7-evb.dts
Normal file
110
sys/gnu/dts/arm/atlas7-evb.dts
Normal file
@ -0,0 +1,110 @@
|
||||
/*
|
||||
* DTS file for CSR SiRFatlas7 Evaluation Board
|
||||
*
|
||||
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "atlas7.dtsi"
|
||||
|
||||
/ {
|
||||
model = "CSR SiRFatlas7 Evaluation Board";
|
||||
compatible = "sirf,atlas7-cb", "sirf,atlas7";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttySiRF1,115200 earlyprintk";
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x40000000 0x20000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
vpp_reserved: vpp_mem@5e800000 {
|
||||
compatible = "sirf,reserved-memory";
|
||||
reg = <0x5e800000 0x800000>;
|
||||
};
|
||||
|
||||
nanddisk_reserved: nanddisk@46000000 {
|
||||
reg = <0x46000000 0x200000>;
|
||||
no-map;
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
noc {
|
||||
mediam {
|
||||
nand@17050000 {
|
||||
memory-region = <&nanddisk_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
gnssm {
|
||||
spi1: spi@18200000 {
|
||||
status = "okay";
|
||||
spiflash: macronix@0{
|
||||
status = "okay";
|
||||
compatible = "macronix,mx25l6405d";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <37500000>;
|
||||
spi-cpha;
|
||||
spi-cpol;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partitions@0 {
|
||||
label = "myspiboot";
|
||||
reg = <0x0 0x800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
btm {
|
||||
uart6: uart@11000000 {
|
||||
status = "okay";
|
||||
sirf,uart-has-rtscts;
|
||||
};
|
||||
};
|
||||
|
||||
disp-iobg {
|
||||
vpp@13110000 {
|
||||
memory-region = <&vpp_reserved>;
|
||||
};
|
||||
};
|
||||
|
||||
display0: display@0 {
|
||||
compatible = "lvds-panel";
|
||||
source = "lvds.0";
|
||||
|
||||
bl-gpios = <&gpio_1 63 0>;
|
||||
data-lines = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <60000000>;
|
||||
hactive = <1024>;
|
||||
vactive = <600>;
|
||||
hfront-porch = <220>;
|
||||
hback-porch = <100>;
|
||||
hsync-len = <1>;
|
||||
vback-porch = <10>;
|
||||
vfront-porch = <25>;
|
||||
vsync-len = <1>;
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
813
sys/gnu/dts/arm/atlas7.dtsi
Normal file
813
sys/gnu/dts/arm/atlas7.dtsi
Normal file
@ -0,0 +1,813 @@
|
||||
/*
|
||||
* DTS file for CSR SiRFatlas7 SoC
|
||||
*
|
||||
* Copyright (c) 2014 Cambridge Silicon Radio Limited, a CSR plc group company.
|
||||
*
|
||||
* Licensed under GPLv2 or later.
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
/ {
|
||||
compatible = "sirf,atlas7";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupt-parent = <&gic>;
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
serial1 = &uart1;
|
||||
serial2 = &uart2;
|
||||
serial3 = &uart3;
|
||||
serial4 = &uart4;
|
||||
serial5 = &uart5;
|
||||
serial6 = &uart6;
|
||||
serial9 = &usp2;
|
||||
};
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <0>;
|
||||
};
|
||||
cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a7";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
noc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10000000 0x10000000 0xc0000000>;
|
||||
|
||||
gic: interrupt-controller@10301000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
reg = <0x10301000 0x1000>,
|
||||
<0x10302000 0x0100>;
|
||||
};
|
||||
|
||||
pmu_regulator: pmu_regulator@10E30020 {
|
||||
compatible = "sirf,atlas7-pmu-ldo";
|
||||
reg = <0x10E30020 0x4>;
|
||||
ldo: ldo {
|
||||
regulator-name = "ldo";
|
||||
};
|
||||
};
|
||||
|
||||
atlas7_codec: atlas7_codec@10E30000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "sirf,atlas7-codec";
|
||||
reg = <0x10E30000 0x400>;
|
||||
clocks = <&car 62>;
|
||||
ldo-supply = <&ldo>;
|
||||
};
|
||||
|
||||
atlas7_iacc: atlas7_iacc@10D01000 {
|
||||
#sound-dai-cells = <0>;
|
||||
compatible = "sirf,atlas7-iacc";
|
||||
reg = <0x10D01000 0x100>;
|
||||
dmas = <&dmac3 0>, <&dmac3 7>, <&dmac3 8>,
|
||||
<&dmac3 3>, <&dmac3 9>;
|
||||
dma-names = "rx", "tx0", "tx1", "tx2", "tx3";
|
||||
clocks = <&car 62>;
|
||||
};
|
||||
|
||||
ipc@13240000 {
|
||||
compatible = "sirf,atlas7-ipc";
|
||||
ranges = <0x13240000 0x13240000 0x00010000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
hwspinlock {
|
||||
compatible = "sirf,hwspinlock";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
|
||||
num-spinlocks = <30>;
|
||||
};
|
||||
|
||||
ns_m3_rproc@0 {
|
||||
compatible = "sirf,ns2m30-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 123 0>;
|
||||
};
|
||||
|
||||
ns_m3_rproc@1 {
|
||||
compatible = "sirf,ns2m31-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 126 0>;
|
||||
};
|
||||
|
||||
ns_kal_rproc@0 {
|
||||
compatible = "sirf,ns2kal0-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 124 0>;
|
||||
};
|
||||
|
||||
ns_kal_rproc@1 {
|
||||
compatible = "sirf,ns2kal1-rproc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
interrupts = <0 127 0>;
|
||||
};
|
||||
};
|
||||
|
||||
pinctrl: ioc@18880000 {
|
||||
compatible = "sirf,atlas7-ioc";
|
||||
reg = <0x18880000 0x1000>,
|
||||
<0x10E40000 0x1000>;
|
||||
};
|
||||
|
||||
pmipc {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13240000 0x13240000 0x00010000>;
|
||||
pmipc@0x13240000 {
|
||||
compatible = "sirf,atlas7-pmipc";
|
||||
reg = <0x13240000 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
dramfw {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10830000 0x10830000 0x18000>;
|
||||
dramfw@10820000 {
|
||||
compatible = "sirf,nocfw-dramfw";
|
||||
reg = <0x10830000 0x18000>;
|
||||
};
|
||||
};
|
||||
|
||||
spramfw {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10250000 0x10250000 0x3000>;
|
||||
spramfw@10820000 {
|
||||
compatible = "sirf,nocfw-spramfw";
|
||||
reg = <0x10250000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
cpum {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10200000 0x10200000 0x3000>;
|
||||
cpum@10200000 {
|
||||
compatible = "sirf,nocfw-cpum";
|
||||
reg = <0x10200000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
cgum {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x18641000 0x18641000 0x3000>,
|
||||
<0x18620000 0x18620000 0x1000>;
|
||||
|
||||
cgum@18641000 {
|
||||
compatible = "sirf,nocfw-cgum";
|
||||
reg = <0x18641000 0x3000>;
|
||||
};
|
||||
|
||||
car: clock-controller@18620000 {
|
||||
compatible = "sirf,atlas7-car";
|
||||
reg = <0x18620000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gnssm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x18000000 0x18000000 0x0000ffff>,
|
||||
<0x18010000 0x18010000 0x1000>,
|
||||
<0x18020000 0x18020000 0x1000>,
|
||||
<0x18030000 0x18030000 0x1000>,
|
||||
<0x18040000 0x18040000 0x1000>,
|
||||
<0x18050000 0x18050000 0x1000>,
|
||||
<0x18060000 0x18060000 0x1000>,
|
||||
<0x18100000 0x18100000 0x3000>,
|
||||
<0x18250000 0x18250000 0x10000>,
|
||||
<0x18200000 0x18200000 0x1000>;
|
||||
|
||||
dmac0: dma-controller@18000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x18000000 0x1000>;
|
||||
interrupts = <0 12 0>;
|
||||
clocks = <&car 89>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
gnssmfw@0x18100000 {
|
||||
compatible = "sirf,nocfw-gnssm";
|
||||
reg = <0x18100000 0x3000>;
|
||||
};
|
||||
|
||||
uart0: uart@18010000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18010000 0x1000>;
|
||||
interrupts = <0 17 0>;
|
||||
clocks = <&car 90>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 3>, <&dmac0 2>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
uart1: uart@18020000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18020000 0x1000>;
|
||||
interrupts = <0 18 0>;
|
||||
clocks = <&car 88>;
|
||||
fifosize = <32>;
|
||||
};
|
||||
|
||||
uart2: uart@18030000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18030000 0x1000>;
|
||||
interrupts = <0 19 0>;
|
||||
clocks = <&car 91>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 6>, <&dmac0 7>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart3: uart@18040000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18040000 0x1000>;
|
||||
interrupts = <0 66 0>;
|
||||
clocks = <&car 92>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 4>, <&dmac0 5>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart4: uart@18050000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18050000 0x1000>;
|
||||
interrupts = <0 69 0>;
|
||||
clocks = <&car 93>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 0>, <&dmac0 1>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
uart5: uart@18060000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,atlas7-uart";
|
||||
reg = <0x18060000 0x1000>;
|
||||
interrupts = <0 71 0>;
|
||||
clocks = <&car 94>;
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac0 8>, <&dmac0 9>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
dspub@18250000 {
|
||||
compatible = "dx,cc44p";
|
||||
reg = <0x18250000 0x10000>;
|
||||
interrupts = <0 27 0>;
|
||||
};
|
||||
|
||||
spi1: spi@18200000 {
|
||||
compatible = "sirf,prima2-spi";
|
||||
reg = <0x18200000 0x1000>;
|
||||
interrupts = <0 16 0>;
|
||||
clocks = <&car 95>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
dmas = <&dmac0 12>, <&dmac0 13>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
|
||||
gpum {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13000000 0x13000000 0x3000>;
|
||||
gpum@0x13000000 {
|
||||
compatible = "sirf,nocfw-gpum";
|
||||
reg = <0x13000000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
mediam {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x16000000 0x16000000 0x00200000>,
|
||||
<0x17020000 0x17020000 0x1000>,
|
||||
<0x17030000 0x17030000 0x1000>,
|
||||
<0x17040000 0x17040000 0x1000>,
|
||||
<0x17050000 0x17050000 0x10000>,
|
||||
<0x17060000 0x17060000 0x200>,
|
||||
<0x17060200 0x17060200 0x100>,
|
||||
<0x17070000 0x17070000 0x200>,
|
||||
<0x17070200 0x17070200 0x100>,
|
||||
<0x170A0000 0x170A0000 0x3000>;
|
||||
|
||||
mediam@170A0000 {
|
||||
compatible = "sirf,nocfw-mediam";
|
||||
reg = <0x170A0000 0x3000>;
|
||||
};
|
||||
|
||||
gpio_0: gpio_mediam@17040000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas7-gpio";
|
||||
reg = <0x17040000 0x1000>;
|
||||
interrupts = <0 13 0>, <0 14 0>;
|
||||
clocks = <&car 107>;
|
||||
clock-names = "gpio0_io";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
nand@17050000 {
|
||||
compatible = "sirf,atlas7-nand";
|
||||
reg = <0x17050000 0x10000>;
|
||||
interrupts = <0 41 0>;
|
||||
clocks = <&car 108>, <&car 112>;
|
||||
clock-names = "nand_io", "nand_nand";
|
||||
};
|
||||
|
||||
sd0: sdhci@16000000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x16000000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
clocks = <&car 109>, <&car 111>;
|
||||
clock-names = "core", "iface";
|
||||
wp-inverted;
|
||||
non-removable;
|
||||
status = "disabled";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
sd1: sdhci@16100000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x16100000 0x100000>;
|
||||
interrupts = <0 38 0>;
|
||||
clocks = <&car 109>, <&car 111>;
|
||||
clock-names = "core", "iface";
|
||||
non-removable;
|
||||
status = "disabled";
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
usb0: usb@17060000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-usb";
|
||||
reg = <0x17060000 0x200>;
|
||||
interrupts = <0 10 0>;
|
||||
clocks = <&car 113>;
|
||||
sirf,usbphy = <&usbphy0>;
|
||||
phy_type = "utmi";
|
||||
dr_mode = "otg";
|
||||
maximum-speed = "high-speed";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usb1: usb@17070000 {
|
||||
cell-index = <1>;
|
||||
compatible = "sirf,atlas7-usb";
|
||||
reg = <0x17070000 0x200>;
|
||||
interrupts = <0 11 0>;
|
||||
clocks = <&car 114>;
|
||||
sirf,usbphy = <&usbphy1>;
|
||||
phy_type = "utmi";
|
||||
dr_mode = "host";
|
||||
maximum-speed = "high-speed";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy0: usbphy@0 {
|
||||
compatible = "sirf,atlas7-usbphy";
|
||||
reg = <0x17060200 0x100>;
|
||||
clocks = <&car 115>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy1: usbphy@1 {
|
||||
compatible = "sirf,atlas7-usbphy";
|
||||
reg = <0x17070200 0x100>;
|
||||
clocks = <&car 116>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c0: i2c@17020000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,prima2-i2c";
|
||||
reg = <0x17020000 0x1000>;
|
||||
interrupts = <0 24 0>;
|
||||
clocks = <&car 105>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
vdifm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13290000 0x13290000 0x3000>,
|
||||
<0x13300000 0x13300000 0x1000>,
|
||||
<0x14200000 0x14200000 0x600000>;
|
||||
|
||||
vdifm@13290000 {
|
||||
compatible = "sirf,nocfw-vdifm";
|
||||
reg = <0x13290000 0x3000>;
|
||||
};
|
||||
|
||||
gpio_1: gpio_vdifm@13300000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas7-gpio";
|
||||
reg = <0x13300000 0x1000>;
|
||||
interrupts = <0 43 0>, <0 44 0>, <0 45 0>;
|
||||
clocks = <&car 84>;
|
||||
clock-names = "gpio1_io";
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sd2: sdhci@14200000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14200000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
clocks = <&car 70>, <&car 75>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
sd-uhs-sdr50;
|
||||
vqmmc-supply = <&vqmmc>;
|
||||
vqmmc: vqmmc@2 {
|
||||
regulator-min-microvolt = <1650000>;
|
||||
regulator-max-microvolt = <1950000>;
|
||||
regulator-name = "vqmmc-ldo";
|
||||
regulator-type = "voltage";
|
||||
regulator-boot-on;
|
||||
regulator-allow-bypass;
|
||||
};
|
||||
};
|
||||
|
||||
sd3: sdhci@14300000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14300000 0x100000>;
|
||||
interrupts = <0 23 0>;
|
||||
clocks = <&car 76>, <&car 81>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sd5: sdhci@14500000 {
|
||||
cell-index = <5>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14500000 0x100000>;
|
||||
interrupts = <0 39 0>;
|
||||
clocks = <&car 71>, <&car 76>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
loop-dma;
|
||||
};
|
||||
|
||||
sd6: sdhci@14600000 {
|
||||
cell-index = <6>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14600000 0x100000>;
|
||||
interrupts = <0 98 0>;
|
||||
clocks = <&car 72>, <&car 77>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
sd7: sdhci@14700000 {
|
||||
cell-index = <7>;
|
||||
compatible = "sirf,atlas7-sdhc";
|
||||
reg = <0x14700000 0x100000>;
|
||||
interrupts = <0 98 0>;
|
||||
clocks = <&car 72>, <&car 77>;
|
||||
clock-names = "core", "iface";
|
||||
status = "disabled";
|
||||
bus-width = <4>;
|
||||
};
|
||||
};
|
||||
|
||||
audiom {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10d50000 0x10d50000 0x0000ffff>,
|
||||
<0x10d60000 0x10d60000 0x0000ffff>,
|
||||
<0x10d80000 0x10d80000 0x0000ffff>,
|
||||
<0x10d90000 0x10d90000 0x0000ffff>,
|
||||
<0x10ED0000 0x10ED0000 0x3000>,
|
||||
<0x10dc8000 0x10dc8000 0x1000>,
|
||||
<0x10dc0000 0x10dc0000 0x1000>,
|
||||
<0x10db0000 0x10db0000 0x4000>,
|
||||
<0x10d40000 0x10d40000 0x1000>,
|
||||
<0x10d30000 0x10d30000 0x1000>;
|
||||
|
||||
timer@10dc0000 {
|
||||
compatible = "sirf,atlas7-tick";
|
||||
reg = <0x10dc0000 0x1000>;
|
||||
interrupts = <0 0 0>,
|
||||
<0 1 0>,
|
||||
<0 2 0>,
|
||||
<0 49 0>,
|
||||
<0 50 0>,
|
||||
<0 51 0>;
|
||||
clocks = <&car 47>;
|
||||
};
|
||||
|
||||
timerb@10dc8000 {
|
||||
compatible = "sirf,atlas7-tick";
|
||||
reg = <0x10dc8000 0x1000>;
|
||||
interrupts = <0 74 0>,
|
||||
<0 75 0>,
|
||||
<0 76 0>,
|
||||
<0 77 0>,
|
||||
<0 78 0>,
|
||||
<0 79 0>;
|
||||
clocks = <&car 47>;
|
||||
};
|
||||
|
||||
vip0@10db0000 {
|
||||
compatible = "sirf,atlas7-vip0";
|
||||
reg = <0x10db0000 0x2000>;
|
||||
interrupts = <0 85 0>;
|
||||
sirf,vip_cma_size = <0xC00000>;
|
||||
};
|
||||
|
||||
cvd@10db2000 {
|
||||
compatible = "sirf,cvd";
|
||||
reg = <0x10db2000 0x2000>;
|
||||
clocks = <&car 46>;
|
||||
};
|
||||
|
||||
dmac2: dma-controller@10d50000 {
|
||||
cell-index = <2>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x10d50000 0xffff>;
|
||||
interrupts = <0 55 0>;
|
||||
clocks = <&car 60>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
dmac3: dma-controller@10d60000 {
|
||||
cell-index = <3>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x10d60000 0xffff>;
|
||||
interrupts = <0 56 0>;
|
||||
clocks = <&car 61>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
|
||||
adc: adc@10d80000 {
|
||||
compatible = "sirf,atlas7-adc";
|
||||
reg = <0x10d80000 0xffff>;
|
||||
interrupts = <0 34 0>;
|
||||
clocks = <&car 49>;
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
pulsec@10d90000 {
|
||||
compatible = "sirf,prima2-pulsec";
|
||||
reg = <0x10d90000 0xffff>;
|
||||
interrupts = <0 42 0>;
|
||||
clocks = <&car 54>;
|
||||
};
|
||||
|
||||
audiom@10ED0000 {
|
||||
compatible = "sirf,nocfw-audiom";
|
||||
reg = <0x10ED0000 0x3000>;
|
||||
interrupts = <0 102 0>;
|
||||
};
|
||||
|
||||
usp1: usp@10d30000 {
|
||||
cell-index = <1>;
|
||||
reg = <0x10d30000 0x1000>;
|
||||
fifosize = <512>;
|
||||
clocks = <&car 58>;
|
||||
dmas = <&dmac2 6>, <&dmac2 7>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
usp2: usp@10d40000 {
|
||||
cell-index = <2>;
|
||||
reg = <0x10d40000 0x1000>;
|
||||
interrupts = <0 22 0>;
|
||||
clocks = <&car 59>;
|
||||
dmas = <&dmac2 12>, <&dmac2 13>;
|
||||
dma-names = "rx", "tx";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
ddrm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x10820000 0x10820000 0x3000>,
|
||||
<0x10800000 0x10800000 0x2000>;
|
||||
ddrm@10820000 {
|
||||
compatible = "sirf,nocfw-ddrm";
|
||||
reg = <0x10820000 0x3000>;
|
||||
interrupts = <0 105 0>;
|
||||
};
|
||||
|
||||
memory-controller@0x10800000 {
|
||||
compatible = "sirf,atlas7-memc";
|
||||
reg = <0x10800000 0x2000>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
btm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x11002000 0x11002000 0x0000ffff>,
|
||||
<0x11010000 0x11010000 0x3000>,
|
||||
<0x11000000 0x11000000 0x1000>,
|
||||
<0x11001000 0x11001000 0x1000>;
|
||||
|
||||
dmac4: dma-controller@11002000 {
|
||||
cell-index = <4>;
|
||||
compatible = "sirf,atlas7-dmac";
|
||||
reg = <0x11002000 0x1000>;
|
||||
interrupts = <0 99 0>;
|
||||
clocks = <&car 130>;
|
||||
dma-channels = <16>;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
uart6: uart@11000000 {
|
||||
cell-index = <6>;
|
||||
compatible = "sirf,atlas7-bt-uart",
|
||||
"sirf,atlas7-uart";
|
||||
reg = <0x11000000 0x1000>;
|
||||
interrupts = <0 100 0>;
|
||||
clocks = <&car 131>, <&car 133>, <&car 134>;
|
||||
clock-names = "uart", "general", "noc";
|
||||
fifosize = <128>;
|
||||
dmas = <&dmac4 12>, <&dmac4 13>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usp3: usp@11001000 {
|
||||
compatible = "sirf,atlas7-bt-usp",
|
||||
"sirf,prima2-usp-pcm";
|
||||
cell-index = <3>;
|
||||
reg = <0x11001000 0x1000>;
|
||||
fifosize = <512>;
|
||||
clocks = <&car 132>, <&car 129>, <&car 133>,
|
||||
<&car 134>, <&car 135>;
|
||||
clock-names = "usp3_io", "a7ca_btss", "a7ca_io",
|
||||
"noc_btm_io", "thbtm_io";
|
||||
dmas = <&dmac4 0>, <&dmac4 1>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
|
||||
btm@11010000 {
|
||||
compatible = "sirf,nocfw-btm";
|
||||
reg = <0x11010000 0x3000>;
|
||||
};
|
||||
};
|
||||
|
||||
rtcm {
|
||||
compatible = "arteris, flexnoc", "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x18810000 0x18810000 0x3000>,
|
||||
<0x18840000 0x18840000 0x1000>,
|
||||
<0x18890000 0x18890000 0x1000>,
|
||||
<0x188B0000 0x188B0000 0x10000>,
|
||||
<0x188D0000 0x188D0000 0x1000>;
|
||||
rtcm@18810000 {
|
||||
compatible = "sirf,nocfw-rtcm";
|
||||
reg = <0x18810000 0x3000>;
|
||||
interrupts = <0 109 0>;
|
||||
};
|
||||
|
||||
gpio_2: gpio_rtcm@18890000 {
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
compatible = "sirf,atlas7-gpio";
|
||||
reg = <0x18890000 0x1000>;
|
||||
interrupts = <0 47 0>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
rtc-iobg@18840000 {
|
||||
compatible = "sirf,prima2-rtciobg",
|
||||
"sirf-prima2-rtciobg-bus",
|
||||
"simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x18840000 0x1000>;
|
||||
|
||||
sysrtc@2000 {
|
||||
compatible = "sirf,prima2-sysrtc";
|
||||
reg = <0x2000 0x100>;
|
||||
interrupts = <0 52 0>;
|
||||
};
|
||||
pwrc@3000 {
|
||||
compatible = "sirf,atlas7-pwrc";
|
||||
reg = <0x3000 0x100>;
|
||||
};
|
||||
};
|
||||
|
||||
qspi: flash@188B0000 {
|
||||
cell-index = <0>;
|
||||
compatible = "sirf,atlas7-qspi-nor";
|
||||
reg = <0x188B0000 0x10000>;
|
||||
interrupts = <0 15 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
|
||||
retain@0x188D0000 {
|
||||
compatible = "sirf,atlas7-retain";
|
||||
reg = <0x188D0000 0x1000>;
|
||||
};
|
||||
|
||||
};
|
||||
disp-iobg {
|
||||
/* lcdc0 */
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x13100000 0x13100000 0x20000>,
|
||||
<0x10e10000 0x10e10000 0x10000>;
|
||||
|
||||
lcd@13100000 {
|
||||
compatible = "sirf,atlas7-lcdc";
|
||||
reg = <0x13100000 0x10000>;
|
||||
interrupts = <0 30 0>;
|
||||
clocks = <&car 79>;
|
||||
};
|
||||
vpp@13110000 {
|
||||
compatible = "sirf,atlas7-vpp";
|
||||
reg = <0x13110000 0x10000>;
|
||||
interrupts = <0 31 0>;
|
||||
clocks = <&car 78>;
|
||||
resets = <&car 29>;
|
||||
};
|
||||
lvds@10e10000 {
|
||||
compatible = "sirf,atlas7-lvdsc";
|
||||
reg = <0x10e10000 0x10000>;
|
||||
interrupts = <0 64 0>;
|
||||
clocks = <&car 54>;
|
||||
resets = <&car 29>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
graphics-iobg {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x12000000 0x12000000 0x1000000>;
|
||||
|
||||
graphics@12000000 {
|
||||
compatible = "powervr,sgx531";
|
||||
reg = <0x12000000 0x1000000>;
|
||||
interrupts = <0 6 0>;
|
||||
clocks = <&car 126>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
51
sys/gnu/dts/arm/axm5516-amarillo.dts
Normal file
51
sys/gnu/dts/arm/axm5516-amarillo.dts
Normal file
@ -0,0 +1,51 @@
|
||||
/*
|
||||
* arch/arm/boot/dts/axm5516-amarillo.dts
|
||||
*
|
||||
* Copyright (C) 2013 LSI
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/memreserve/ 0x00000000 0x00400000;
|
||||
|
||||
#include "axm55xx.dtsi"
|
||||
#include "axm5516-cpus.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Amarillo AXM5516";
|
||||
compatible = "lsi,axm5516-amarillo", "lsi,axm5516";
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0 0x00000000 0x02 0x00000000>;
|
||||
};
|
||||
};
|
||||
|
||||
&serial0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&serial3 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpio1 {
|
||||
status = "okay";
|
||||
};
|
||||
204
sys/gnu/dts/arm/axm5516-cpus.dtsi
Normal file
204
sys/gnu/dts/arm/axm5516-cpus.dtsi
Normal file
@ -0,0 +1,204 @@
|
||||
/*
|
||||
* arch/arm/boot/dts/axm5516-cpus.dtsi
|
||||
*
|
||||
* Copyright (C) 2013 LSI
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu-map {
|
||||
cluster0 {
|
||||
core0 {
|
||||
cpu = <&CPU0>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU1>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU2>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU3>;
|
||||
};
|
||||
};
|
||||
cluster1 {
|
||||
core0 {
|
||||
cpu = <&CPU4>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU5>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU6>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU7>;
|
||||
};
|
||||
};
|
||||
cluster2 {
|
||||
core0 {
|
||||
cpu = <&CPU8>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU9>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU10>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU11>;
|
||||
};
|
||||
};
|
||||
cluster3 {
|
||||
core0 {
|
||||
cpu = <&CPU12>;
|
||||
};
|
||||
core1 {
|
||||
cpu = <&CPU13>;
|
||||
};
|
||||
core2 {
|
||||
cpu = <&CPU14>;
|
||||
};
|
||||
core3 {
|
||||
cpu = <&CPU15>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
CPU0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x00>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x01>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU2: cpu@2 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x02>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU3: cpu@3 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x03>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU4: cpu@100 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x100>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU5: cpu@101 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x101>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU6: cpu@102 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x102>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU7: cpu@103 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x103>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU8: cpu@200 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x200>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU9: cpu@201 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x201>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU10: cpu@202 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x202>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU11: cpu@203 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x203>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU12: cpu@300 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x300>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU13: cpu@301 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x301>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU14: cpu@302 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x302>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
|
||||
CPU15: cpu@303 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a15";
|
||||
reg = <0x303>;
|
||||
clock-frequency= <1400000000>;
|
||||
cpu-release-addr = <0>; // Fixed by the boot loader
|
||||
};
|
||||
};
|
||||
};
|
||||
204
sys/gnu/dts/arm/axm55xx.dtsi
Normal file
204
sys/gnu/dts/arm/axm55xx.dtsi
Normal file
@ -0,0 +1,204 @@
|
||||
/*
|
||||
* arch/arm/boot/dts/axm55xx.dtsi
|
||||
*
|
||||
* Copyright (C) 2013 LSI
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/lsi,axm5516-clks.h>
|
||||
|
||||
#include "skeleton64.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
aliases {
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
timer = &timer0;
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
clk_ref0: clk_ref0 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clk_ref1: clk_ref1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clk_ref2: clk_ref2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <125000000>;
|
||||
};
|
||||
|
||||
clks: clock-controller@2010020000 {
|
||||
compatible = "lsi,axm5516-clks";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x20 0x10020000 0 0x20000>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@2001001000 {
|
||||
compatible = "arm,cortex-a15-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x20 0x01001000 0 0x1000>,
|
||||
<0x20 0x01002000 0 0x1000>,
|
||||
<0x20 0x01004000 0 0x2000>,
|
||||
<0x20 0x01006000 0 0x2000>;
|
||||
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) |
|
||||
IRQ_TYPE_LEVEL_HIGH)>;
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv7-timer";
|
||||
interrupts =
|
||||
<GIC_PPI 13
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 14
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 11
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
||||
<GIC_PPI 10
|
||||
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
||||
};
|
||||
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a15-pmu";
|
||||
interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
device_type = "soc";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
syscon: syscon@2010030000 {
|
||||
compatible = "lsi,axxia-syscon", "syscon";
|
||||
reg = <0x20 0x10030000 0 0x2000>;
|
||||
};
|
||||
|
||||
reset: reset@2010031000 {
|
||||
compatible = "lsi,axm55xx-reset";
|
||||
syscon = <&syscon>;
|
||||
};
|
||||
|
||||
amba {
|
||||
compatible = "arm,amba-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
serial0: uart@2010080000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x20 0x10080000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial1: uart@2010081000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x20 0x10081000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial2: uart@2010082000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x20 0x10082000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
serial3: uart@2010083000 {
|
||||
compatible = "arm,pl011", "arm,primecell";
|
||||
reg = <0x20 0x10083000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer0: timer@2010091000 {
|
||||
compatible = "arm,sp804", "arm,primecell";
|
||||
reg = <0x20 0x10091000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
gpio0: gpio@2010092000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0x20 0x10092000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@2010093000 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
gpio-controller;
|
||||
reg = <0x20 0x10093000 0x00 0x1000>;
|
||||
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks AXXIA_CLK_PER>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/*
|
||||
Local Variables:
|
||||
mode: C
|
||||
End:
|
||||
*/
|
||||
97
sys/gnu/dts/arm/axp209.dtsi
Normal file
97
sys/gnu/dts/arm/axp209.dtsi
Normal file
@ -0,0 +1,97 @@
|
||||
/*
|
||||
* Copyright 2015 Chen-Yu Tsai
|
||||
*
|
||||
* Chen-Yu Tsai <wens@csie.org>
|
||||
*
|
||||
* This file is dual-licensed: you can use it either under the terms
|
||||
* of the GPL or the X11 license, at your option. Note that this dual
|
||||
* licensing only applies to this file, and not this project as a
|
||||
* whole.
|
||||
*
|
||||
* a) This file is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of the
|
||||
* License, or (at your option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public
|
||||
* License along with this file; if not, write to the Free
|
||||
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*
|
||||
* Or, alternatively,
|
||||
*
|
||||
* b) Permission is hereby granted, free of charge, to any person
|
||||
* obtaining a copy of this software and associated documentation
|
||||
* files (the "Software"), to deal in the Software without
|
||||
* restriction, including without limitation the rights to use,
|
||||
* copy, modify, merge, publish, distribute, sublicense, and/or
|
||||
* sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following
|
||||
* conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be
|
||||
* included in all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
|
||||
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
|
||||
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
|
||||
* OTHER DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* AXP202/209 Integrated Power Management Chip
|
||||
* http://www.x-powers.com/product/AXP20X.php
|
||||
* http://dl.linux-sunxi.org/AXP/AXP209%20Datasheet%20v1.0_cn.pdf
|
||||
*/
|
||||
|
||||
&axp209 {
|
||||
compatible = "x-powers,axp209";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
regulators {
|
||||
/* Default work frequency for buck regulators */
|
||||
x-powers,dcdc-freq = <1500>;
|
||||
|
||||
reg_dcdc2: dcdc2 {
|
||||
regulator-name = "dcdc2";
|
||||
};
|
||||
|
||||
reg_dcdc3: dcdc3 {
|
||||
regulator-name = "dcdc3";
|
||||
};
|
||||
|
||||
reg_ldo1: ldo1 {
|
||||
/* LDO1 is a fixed output regulator */
|
||||
regulator-always-on;
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1300000>;
|
||||
regulator-name = "ldo1";
|
||||
};
|
||||
|
||||
reg_ldo2: ldo2 {
|
||||
regulator-name = "ldo2";
|
||||
};
|
||||
|
||||
reg_ldo3: ldo3 {
|
||||
regulator-name = "ldo3";
|
||||
};
|
||||
|
||||
reg_ldo4: ldo4 {
|
||||
regulator-name = "ldo4";
|
||||
};
|
||||
|
||||
reg_ldo5: ldo5 {
|
||||
regulator-name = "ldo5";
|
||||
};
|
||||
};
|
||||
};
|
||||
91
sys/gnu/dts/arm/bcm-cygnus-clock.dtsi
Normal file
91
sys/gnu/dts/arm/bcm-cygnus-clock.dtsi
Normal file
@ -0,0 +1,91 @@
|
||||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
osc: oscillator {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <1>;
|
||||
clock-frequency = <25000000>;
|
||||
};
|
||||
|
||||
apb_clk: apb_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000000>;
|
||||
};
|
||||
|
||||
periph_clk: periph_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <500000000>;
|
||||
};
|
||||
|
||||
sdio_clk: lcpll_ch2 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <200000000>;
|
||||
};
|
||||
|
||||
axi81_clk: axi81_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
keypad_clk: keypad_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <31806>;
|
||||
};
|
||||
|
||||
adc_clk: adc_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1562500>;
|
||||
};
|
||||
|
||||
pwm_clk: pwm_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
lcd_clk: mipipll_ch1 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
};
|
||||
160
sys/gnu/dts/arm/bcm-cygnus.dtsi
Normal file
160
sys/gnu/dts/arm/bcm-cygnus.dtsi
Normal file
@ -0,0 +1,160 @@
|
||||
/*
|
||||
* BSD LICENSE
|
||||
*
|
||||
* Copyright(c) 2014 Broadcom Corporation. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,cygnus";
|
||||
model = "Broadcom Cygnus SoC";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
next-level-cache = <&L2>;
|
||||
reg = <0x0>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "bcm-cygnus-clock.dtsi"
|
||||
|
||||
amba {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "arm,amba-bus", "simple-bus";
|
||||
interrupt-parent = <&gic>;
|
||||
ranges;
|
||||
|
||||
wdt@18009000 {
|
||||
compatible = "arm,sp805" , "arm,primecell";
|
||||
reg = <0x18009000 0x1000>;
|
||||
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-names = "apb_pclk";
|
||||
};
|
||||
};
|
||||
|
||||
i2c0: i2c@18008000 {
|
||||
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
|
||||
reg = <0x18008000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@1800b000 {
|
||||
compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c";
|
||||
reg = <0x1800b000 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>;
|
||||
clock-frequency = <100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@18020000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x18020000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-frequency = <100000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@18021000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x18021000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-frequency = <100000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@18022000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x18020000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-frequency = <100000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@18023000 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x18023000 0x100>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&axi81_clk>;
|
||||
clock-frequency = <100000000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gic: interrupt-controller@19021000 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x19021000 0x1000>,
|
||||
<0x19020100 0x100>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x19022000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
timer@19020200 {
|
||||
compatible = "arm,cortex-a9-global-timer";
|
||||
reg = <0x19020200 0x100>;
|
||||
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&periph_clk>;
|
||||
};
|
||||
|
||||
};
|
||||
424
sys/gnu/dts/arm/bcm11351.dtsi
Normal file
424
sys/gnu/dts/arm/bcm11351.dtsi
Normal file
@ -0,0 +1,424 @@
|
||||
/*
|
||||
* Copyright (C) 2012-2013 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "dt-bindings/clock/bcm281xx.h"
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM11351 SoC";
|
||||
compatible = "brcm,bcm11351";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "brcm,bcm11351-cpu-method";
|
||||
secondary-boot-reg = <0x3500417c>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@3ff00100 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x3ff01000 0x1000>,
|
||||
<0x3ff00100 0x100>;
|
||||
};
|
||||
|
||||
smc@0x3404c000 {
|
||||
compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
|
||||
reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e000000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart@3e001000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e001000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart@3e003000 {
|
||||
compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e003000 0x1000>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
|
||||
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "brcm,bcm11351-a2-pl310-cache";
|
||||
reg = <0x3ff20000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
watchdog@35002f40 {
|
||||
compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
|
||||
reg = <0x35002f40 0x6c>;
|
||||
};
|
||||
|
||||
timer@35006000 {
|
||||
compatible = "brcm,kona-timer";
|
||||
reg = <0x35006000 0x1000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
|
||||
};
|
||||
|
||||
gpio: gpio@35003000 {
|
||||
compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
|
||||
reg = <0x35003000 0x800>;
|
||||
interrupts =
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sdio1: sdio@3f180000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f180000 0x10000>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: sdio@3f190000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f190000 0x10000>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: sdio@3f1a0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x10000>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio4: sdio@3f1b0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1b0000 0x10000>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pinctrl@35004800 {
|
||||
compatible = "brcm,bcm11351-pinctrl";
|
||||
reg = <0x35004800 0x430>;
|
||||
};
|
||||
|
||||
i2c@3e016000 {
|
||||
compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e016000 0x80>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3e017000 {
|
||||
compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e017000 0x80>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3e018000 {
|
||||
compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e018000 0x80>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3500d000 {
|
||||
compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3500d000 0x80>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm: pwm@3e01a000 {
|
||||
compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
|
||||
reg = <0x3e01a000 0xcc>;
|
||||
clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
|
||||
#pwm-cells = <3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
root_ccu: root_ccu {
|
||||
compatible = "brcm,bcm11351-root-ccu";
|
||||
reg = <0x35001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "frac_1m";
|
||||
};
|
||||
|
||||
hub_ccu: hub_ccu {
|
||||
compatible = "brcm,bcm11351-hub-ccu";
|
||||
reg = <0x34000000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "tmon_1m";
|
||||
};
|
||||
|
||||
aon_ccu: aon_ccu {
|
||||
compatible = "brcm,bcm11351-aon-ccu";
|
||||
reg = <0x35002000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "hub_timer",
|
||||
"pmu_bsc",
|
||||
"pmu_bsc_var";
|
||||
};
|
||||
|
||||
master_ccu: master_ccu {
|
||||
compatible = "brcm,bcm11351-master-ccu";
|
||||
reg = <0x3f001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "sdio1",
|
||||
"sdio2",
|
||||
"sdio3",
|
||||
"sdio4",
|
||||
"usb_ic",
|
||||
"hsic2_48m",
|
||||
"hsic2_12m";
|
||||
};
|
||||
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = "brcm,bcm11351-slave-ccu";
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"uartb4",
|
||||
"ssp0",
|
||||
"ssp2",
|
||||
"bsc1",
|
||||
"bsc2",
|
||||
"bsc3",
|
||||
"pwm";
|
||||
};
|
||||
|
||||
ref_1m_clk: ref_1m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
ref_32k_clk: ref_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
bbl_32k_clk: bbl_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ref_13m_clk: ref_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
var_13m_clk: var_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
dft_19_5m_clk: dft_19_5m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19500000>;
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
ref_cx40_clk: ref_cx40 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <40000000>;
|
||||
};
|
||||
|
||||
ref_52m_clk: ref_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
var_52m_clk: var_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
usb_otg_ahb_clk: usb_otg_ahb {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
#clock-cells = <0>;
|
||||
};
|
||||
|
||||
ref_96m_clk: ref_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
var_96m_clk: var_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
ref_104m_clk: ref_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
var_104m_clk: var_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
ref_156m_clk: ref_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
var_156m_clk: var_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
ref_208m_clk: ref_208m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <208000000>;
|
||||
};
|
||||
|
||||
var_208m_clk: var_208m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <208000000>;
|
||||
};
|
||||
|
||||
ref_312m_clk: ref_312m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <312000000>;
|
||||
};
|
||||
|
||||
var_312m_clk: var_312m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <312000000>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg: usb@3f120000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x3f120000 0x10000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_otg_ahb_clk>;
|
||||
clock-names = "otg";
|
||||
phys = <&usbphy>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@3f130000 {
|
||||
compatible = "brcm,kona-usb2-phy";
|
||||
reg = <0x3f130000 0x28>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
56
sys/gnu/dts/arm/bcm21664-garnet.dts
Normal file
56
sys/gnu/dts/arm/bcm21664-garnet.dts
Normal file
@ -0,0 +1,56 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "bcm21664.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM21664 Garnet board";
|
||||
compatible = "brcm,bcm21664-garnet", "brcm,bcm21664";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdio1: sdio@3f180000 {
|
||||
max-frequency = <48000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdio2: sdio@3f190000 {
|
||||
non-removable;
|
||||
max-frequency = <48000000>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdio4: sdio@3f1b0000 {
|
||||
max-frequency = <48000000>;
|
||||
cd-gpios = <&gpio 91 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbotg: usb@3f120000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@3f130000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
357
sys/gnu/dts/arm/bcm21664.dtsi
Normal file
357
sys/gnu/dts/arm/bcm21664.dtsi
Normal file
@ -0,0 +1,357 @@
|
||||
/*
|
||||
* Copyright (C) 2014 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
#include "dt-bindings/clock/bcm21664.h"
|
||||
|
||||
#include "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM21664 SoC";
|
||||
compatible = "brcm,bcm21664";
|
||||
interrupt-parent = <&gic>;
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200n8";
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
enable-method = "brcm,bcm11351-cpu-method";
|
||||
secondary-boot-reg = <0x35004178>;
|
||||
|
||||
cpu0: cpu@0 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
device_type = "cpu";
|
||||
compatible = "arm,cortex-a9";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
gic: interrupt-controller@3ff00100 {
|
||||
compatible = "arm,cortex-a9-gic";
|
||||
#interrupt-cells = <3>;
|
||||
#address-cells = <0>;
|
||||
interrupt-controller;
|
||||
reg = <0x3ff01000 0x1000>,
|
||||
<0x3ff00100 0x100>;
|
||||
};
|
||||
|
||||
smc@0x3404e000 {
|
||||
compatible = "brcm,bcm21664-smc", "brcm,kona-smc";
|
||||
reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e000000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB>;
|
||||
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart@3e001000 {
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e001000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB2>;
|
||||
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
uart@3e002000 {
|
||||
compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart";
|
||||
status = "disabled";
|
||||
reg = <0x3e002000 0x118>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_UARTB3>;
|
||||
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
};
|
||||
|
||||
L2: l2-cache {
|
||||
compatible = "arm,pl310-cache";
|
||||
reg = <0x3ff20000 0x1000>;
|
||||
cache-unified;
|
||||
cache-level = <2>;
|
||||
};
|
||||
|
||||
brcm,resetmgr@35001f00 {
|
||||
compatible = "brcm,bcm21664-resetmgr";
|
||||
reg = <0x35001f00 0x24>;
|
||||
};
|
||||
|
||||
timer@35006000 {
|
||||
compatible = "brcm,kona-timer";
|
||||
reg = <0x35006000 0x1c>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&aon_ccu BCM21664_AON_CCU_HUB_TIMER>;
|
||||
};
|
||||
|
||||
gpio: gpio@35003000 {
|
||||
compatible = "brcm,bcm21664-gpio", "brcm,kona-gpio";
|
||||
reg = <0x35003000 0x524>;
|
||||
interrupts =
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
|
||||
GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#gpio-cells = <2>;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-controller;
|
||||
interrupt-controller;
|
||||
};
|
||||
|
||||
sdio1: sdio@3f180000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f180000 0x801c>;
|
||||
interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio2: sdio@3f190000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f190000 0x801c>;
|
||||
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio3: sdio@3f1a0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1a0000 0x801c>;
|
||||
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdio4: sdio@3f1b0000 {
|
||||
compatible = "brcm,kona-sdhci";
|
||||
reg = <0x3f1b0000 0x801c>;
|
||||
interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&master_ccu BCM21664_MASTER_CCU_SDIO4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3e016000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e016000 0x70>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3e017000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e017000 0x70>;
|
||||
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3e018000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e018000 0x70>;
|
||||
interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC3>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@3e01c000 {
|
||||
compatible = "brcm,bcm21664-i2c", "brcm,kona-i2c";
|
||||
reg = <0x3e01c000 0x70>;
|
||||
interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&slave_ccu BCM21664_SLAVE_CCU_BSC4>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* Fixed clocks are defined before CCUs whose
|
||||
* clocks may depend on them.
|
||||
*/
|
||||
|
||||
ref_32k_clk: ref_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
bbl_32k_clk: bbl_32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
ref_13m_clk: ref_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
var_13m_clk: var_13m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <13000000>;
|
||||
};
|
||||
|
||||
dft_19_5m_clk: dft_19_5m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <19500000>;
|
||||
};
|
||||
|
||||
ref_crystal_clk: ref_crystal {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <26000000>;
|
||||
};
|
||||
|
||||
ref_52m_clk: ref_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
var_52m_clk: var_52m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
usb_otg_ahb_clk: usb_otg_ahb {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <52000000>;
|
||||
};
|
||||
|
||||
ref_96m_clk: ref_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
var_96m_clk: var_96m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <96000000>;
|
||||
};
|
||||
|
||||
ref_104m_clk: ref_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
var_104m_clk: var_104m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <104000000>;
|
||||
};
|
||||
|
||||
ref_156m_clk: ref_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
var_156m_clk: var_156m {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <156000000>;
|
||||
};
|
||||
|
||||
root_ccu: root_ccu {
|
||||
compatible = BCM21664_DT_ROOT_CCU_COMPAT;
|
||||
reg = <0x35001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "frac_1m";
|
||||
};
|
||||
|
||||
aon_ccu: aon_ccu {
|
||||
compatible = BCM21664_DT_AON_CCU_COMPAT;
|
||||
reg = <0x35002000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "hub_timer";
|
||||
};
|
||||
|
||||
master_ccu: master_ccu {
|
||||
compatible = BCM21664_DT_MASTER_CCU_COMPAT;
|
||||
reg = <0x3f001000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "sdio1",
|
||||
"sdio2",
|
||||
"sdio3",
|
||||
"sdio4",
|
||||
"sdio1_sleep",
|
||||
"sdio2_sleep",
|
||||
"sdio3_sleep",
|
||||
"sdio4_sleep";
|
||||
};
|
||||
|
||||
slave_ccu: slave_ccu {
|
||||
compatible = BCM21664_DT_SLAVE_CCU_COMPAT;
|
||||
reg = <0x3e011000 0x0f00>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "uartb",
|
||||
"uartb2",
|
||||
"uartb3",
|
||||
"bsc1",
|
||||
"bsc2",
|
||||
"bsc3",
|
||||
"bsc4";
|
||||
};
|
||||
};
|
||||
|
||||
usbotg: usb@3f120000 {
|
||||
compatible = "snps,dwc2";
|
||||
reg = <0x3f120000 0x10000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&usb_otg_ahb_clk>;
|
||||
clock-names = "otg";
|
||||
phys = <&usbphy>;
|
||||
phy-names = "usb2-phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@3f130000 {
|
||||
compatible = "brcm,kona-usb2-phy";
|
||||
reg = <0x3f130000 0x28>;
|
||||
#phy-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
121
sys/gnu/dts/arm/bcm28155-ap.dts
Normal file
121
sys/gnu/dts/arm/bcm28155-ap.dts
Normal file
@ -0,0 +1,121 @@
|
||||
/*
|
||||
* Copyright (C) 2013 Broadcom Corporation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
|
||||
#include "bcm11351.dtsi"
|
||||
|
||||
/ {
|
||||
model = "BCM28155 AP board";
|
||||
compatible = "brcm,bcm28155-ap", "brcm,bcm11351";
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x40000000>; /* 1 GB */
|
||||
};
|
||||
|
||||
uart@3e000000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
i2c@3e016000 {
|
||||
status="okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c@3e017000 {
|
||||
status="okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c@3e018000 {
|
||||
status="okay";
|
||||
clock-frequency = <400000>;
|
||||
};
|
||||
|
||||
i2c@3500d000 {
|
||||
status="okay";
|
||||
clock-frequency = <100000>;
|
||||
|
||||
pmu: pmu@8 {
|
||||
reg = <0x08>;
|
||||
};
|
||||
};
|
||||
|
||||
sdio2: sdio@3f190000 {
|
||||
non-removable;
|
||||
max-frequency = <48000000>;
|
||||
vmmc-supply = <&camldo1_reg>;
|
||||
vqmmc-supply = <&iosr1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
sdio4: sdio@3f1b0000 {
|
||||
max-frequency = <48000000>;
|
||||
cd-gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&sdldo_reg>;
|
||||
vqmmc-supply = <&sdxldo_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
pwm: pwm@3e01a000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbotg: usb@3f120000 {
|
||||
vusb_d-supply = <&usbldo_reg>;
|
||||
vusb_a-supply = <&iosr1_reg>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
usbphy: usb-phy@3f130000 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
#include "bcm59056.dtsi"
|
||||
|
||||
&pmu {
|
||||
compatible = "brcm,bcm59056";
|
||||
interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>;
|
||||
regulators {
|
||||
camldo1_reg: camldo1 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sdldo_reg: sdldo {
|
||||
regulator-min-microvolt = <3000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
};
|
||||
|
||||
sdxldo_reg: sdxldo {
|
||||
regulator-min-microvolt = <2700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
usbldo_reg: usbldo {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
iosr1_reg: iosr1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
30
sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
Normal file
30
sys/gnu/dts/arm/bcm2835-rpi-b-plus.dts
Normal file
@ -0,0 +1,30 @@
|
||||
/dts-v1/;
|
||||
/include/ "bcm2835-rpi.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,model-b-plus", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model B+";
|
||||
|
||||
leds {
|
||||
act {
|
||||
gpios = <&gpio 47 0>;
|
||||
};
|
||||
|
||||
pwr {
|
||||
label = "PWR";
|
||||
gpios = <&gpio 35 0>;
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-0 = <&gpioout &alt0 &i2s_alt0 &alt3>;
|
||||
|
||||
/* I2S interface */
|
||||
i2s_alt0: i2s_alt0 {
|
||||
brcm,pins = <18 19 20 21>;
|
||||
brcm,function = <4>; /* alt0 */
|
||||
};
|
||||
};
|
||||
23
sys/gnu/dts/arm/bcm2835-rpi-b.dts
Normal file
23
sys/gnu/dts/arm/bcm2835-rpi-b.dts
Normal file
@ -0,0 +1,23 @@
|
||||
/dts-v1/;
|
||||
/include/ "bcm2835-rpi.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "raspberrypi,model-b", "brcm,bcm2835";
|
||||
model = "Raspberry Pi Model B";
|
||||
|
||||
leds {
|
||||
act {
|
||||
gpios = <&gpio 16 1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-0 = <&gpioout &alt0 &i2s_alt2 &alt3>;
|
||||
|
||||
/* I2S interface */
|
||||
i2s_alt2: i2s_alt2 {
|
||||
brcm,pins = <28 29 30 31>;
|
||||
brcm,function = <6>; /* alt2 */
|
||||
};
|
||||
};
|
||||
51
sys/gnu/dts/arm/bcm2835-rpi.dtsi
Normal file
51
sys/gnu/dts/arm/bcm2835-rpi.dtsi
Normal file
@ -0,0 +1,51 @@
|
||||
/include/ "bcm2835.dtsi"
|
||||
|
||||
/ {
|
||||
memory {
|
||||
reg = <0 0x10000000>;
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
act {
|
||||
label = "ACT";
|
||||
default-state = "keep";
|
||||
linux,default-trigger = "heartbeat";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&gpio {
|
||||
pinctrl-names = "default";
|
||||
|
||||
gpioout: gpioout {
|
||||
brcm,pins = <6>;
|
||||
brcm,function = <1>; /* GPIO out */
|
||||
};
|
||||
|
||||
alt0: alt0 {
|
||||
brcm,pins = <0 1 2 3 4 5 7 8 9 10 11 14 15 40 45>;
|
||||
brcm,function = <4>; /* alt0 */
|
||||
};
|
||||
|
||||
alt3: alt3 {
|
||||
brcm,pins = <48 49 50 51 52 53>;
|
||||
brcm,function = <7>; /* alt3 */
|
||||
};
|
||||
};
|
||||
|
||||
&i2c0 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
status = "okay";
|
||||
clock-frequency = <100000>;
|
||||
};
|
||||
|
||||
&sdhci {
|
||||
status = "okay";
|
||||
bus-width = <4>;
|
||||
};
|
||||
183
sys/gnu/dts/arm/bcm2835.dtsi
Normal file
183
sys/gnu/dts/arm/bcm2835.dtsi
Normal file
@ -0,0 +1,183 @@
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "brcm,bcm2835";
|
||||
model = "BCM2835";
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
chosen {
|
||||
bootargs = "earlyprintk console=ttyAMA0";
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x7e000000 0x20000000 0x02000000>;
|
||||
|
||||
timer@7e003000 {
|
||||
compatible = "brcm,bcm2835-system-timer";
|
||||
reg = <0x7e003000 0x1000>;
|
||||
interrupts = <1 0>, <1 1>, <1 2>, <1 3>;
|
||||
clock-frequency = <1000000>;
|
||||
};
|
||||
|
||||
dma: dma@7e007000 {
|
||||
compatible = "brcm,bcm2835-dma";
|
||||
reg = <0x7e007000 0xf00>;
|
||||
interrupts = <1 16>,
|
||||
<1 17>,
|
||||
<1 18>,
|
||||
<1 19>,
|
||||
<1 20>,
|
||||
<1 21>,
|
||||
<1 22>,
|
||||
<1 23>,
|
||||
<1 24>,
|
||||
<1 25>,
|
||||
<1 26>,
|
||||
<1 27>,
|
||||
<1 28>;
|
||||
|
||||
#dma-cells = <1>;
|
||||
brcm,dma-channel-mask = <0x7f35>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@7e00b200 {
|
||||
compatible = "brcm,bcm2835-armctrl-ic";
|
||||
reg = <0x7e00b200 0x200>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
watchdog@7e100000 {
|
||||
compatible = "brcm,bcm2835-pm-wdt";
|
||||
reg = <0x7e100000 0x28>;
|
||||
};
|
||||
|
||||
rng@7e104000 {
|
||||
compatible = "brcm,bcm2835-rng";
|
||||
reg = <0x7e104000 0x10>;
|
||||
};
|
||||
|
||||
gpio: gpio@7e200000 {
|
||||
compatible = "brcm,bcm2835-gpio";
|
||||
reg = <0x7e200000 0xb4>;
|
||||
/*
|
||||
* The GPIO IP block is designed for 3 banks of GPIOs.
|
||||
* Each bank has a GPIO interrupt for itself.
|
||||
* There is an overall "any bank" interrupt.
|
||||
* In order, these are GIC interrupts 17, 18, 19, 20.
|
||||
* Since the BCM2835 only has 2 banks, the 2nd bank
|
||||
* interrupt output appears to be mirrored onto the
|
||||
* 3rd bank's interrupt signal.
|
||||
* So, a bank0 interrupt shows up on 17, 20, and
|
||||
* a bank1 interrupt shows up on 18, 19, 20!
|
||||
*/
|
||||
interrupts = <2 17>, <2 18>, <2 19>, <2 20>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
uart@7e201000 {
|
||||
compatible = "brcm,bcm2835-pl011", "arm,pl011", "arm,primecell";
|
||||
reg = <0x7e201000 0x1000>;
|
||||
interrupts = <2 25>;
|
||||
clock-frequency = <3000000>;
|
||||
arm,primecell-periphid = <0x00241011>;
|
||||
};
|
||||
|
||||
i2s: i2s@7e203000 {
|
||||
compatible = "brcm,bcm2835-i2s";
|
||||
reg = <0x7e203000 0x20>,
|
||||
<0x7e101098 0x02>;
|
||||
|
||||
dmas = <&dma 2>,
|
||||
<&dma 3>;
|
||||
dma-names = "tx", "rx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi: spi@7e204000 {
|
||||
compatible = "brcm,bcm2835-spi";
|
||||
reg = <0x7e204000 0x1000>;
|
||||
interrupts = <2 22>;
|
||||
clocks = <&clk_spi>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@20205000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e205000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clk_i2c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhci: sdhci@7e300000 {
|
||||
compatible = "brcm,bcm2835-sdhci";
|
||||
reg = <0x7e300000 0x100>;
|
||||
interrupts = <2 30>;
|
||||
clocks = <&clk_mmc>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c1: i2c@7e804000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e804000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clk_i2c>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
usb@7e980000 {
|
||||
compatible = "brcm,bcm2835-usb";
|
||||
reg = <0x7e980000 0x10000>;
|
||||
interrupts = <1 9>;
|
||||
};
|
||||
|
||||
arm-pmu {
|
||||
compatible = "arm,arm1176-pmu";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
clk_mmc: clock@0 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <0>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "mmc";
|
||||
clock-frequency = <100000000>;
|
||||
};
|
||||
|
||||
clk_i2c: clock@1 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <1>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "i2c";
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
|
||||
clk_spi: clock@2 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <2>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "spi";
|
||||
clock-frequency = <250000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
130
sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts
Normal file
130
sys/gnu/dts/arm/bcm4708-buffalo-wzr-1750dhp.dts
Normal file
@ -0,0 +1,130 @@
|
||||
/*
|
||||
* Broadcom BCM470X / BCM5301X ARM platform code.
|
||||
* DTS for Buffalo WZR-1750DHP
|
||||
*
|
||||
* Copyright (C) 2014 Rafał Miłecki <zajec5@gmail.com>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "buffalo,wzr-1750dhp", "brcm,bcm4708";
|
||||
model = "Buffalo WZR-1750DHP (BCM4708)";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
spi {
|
||||
compatible = "spi-gpio";
|
||||
num-chipselects = <1>;
|
||||
gpio-sck = <&chipcommon 7 0>;
|
||||
gpio-mosi = <&chipcommon 4 0>;
|
||||
cs-gpios = <&chipcommon 6 0>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hc595: gpio_spi@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
reg = <0>;
|
||||
registers-number = <1>;
|
||||
spi-max-frequency = <100000>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
power0 {
|
||||
label = "bcm53xx:red:power";
|
||||
gpios = <&hc595 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
power1 {
|
||||
label = "bcm53xx:white:power";
|
||||
gpios = <&hc595 2 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
router0 {
|
||||
label = "bcm53xx:blue:router";
|
||||
gpios = <&hc595 3 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
router1 {
|
||||
label = "bcm53xx:amber:router";
|
||||
gpios = <&hc595 4 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wan {
|
||||
label = "bcm53xx:blue:wan";
|
||||
gpios = <&hc595 5 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
wireless0 {
|
||||
label = "bcm53xx:blue:wireless";
|
||||
gpios = <&hc595 6 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wireless1 {
|
||||
label = "bcm53xx:amber:wireless";
|
||||
gpios = <&hc595 7 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
aoss {
|
||||
label = "AOSS";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&chipcommon 12 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* Commit mode set by switch? */
|
||||
mode {
|
||||
label = "Mode";
|
||||
linux,code = <KEY_SETUP>;
|
||||
gpios = <&chipcommon 13 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
/* Switch: AP mode */
|
||||
sw_ap {
|
||||
label = "AP";
|
||||
linux,code = <BTN_0>;
|
||||
gpios = <&chipcommon 14 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
eject {
|
||||
label = "USB eject";
|
||||
linux,code = <KEY_EJECTCD>;
|
||||
gpios = <&chipcommon 15 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
60
sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts
Normal file
60
sys/gnu/dts/arm/bcm4708-luxul-xwc-1000.dts
Normal file
@ -0,0 +1,60 @@
|
||||
/*
|
||||
* Broadcom BCM470X / BCM5301X ARM platform code.
|
||||
* DTS for Luxul XWC-1000
|
||||
*
|
||||
* Copyright 2014 Luxul Inc.
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "luxul,xwc-1000", "brcm,bcm4708";
|
||||
model = "Luxul XWC-1000 (BCM4708)";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
axi@18000000 {
|
||||
nand@28000 {
|
||||
reg = <0x00028000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
partition@0 {
|
||||
label = "ubi";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
status {
|
||||
label = "bcm53xx:green:status";
|
||||
gpios = <&chipcommon 0 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "timer";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
93
sys/gnu/dts/arm/bcm4708-netgear-r6250.dts
Normal file
93
sys/gnu/dts/arm/bcm4708-netgear-r6250.dts
Normal file
@ -0,0 +1,93 @@
|
||||
/*
|
||||
* Broadcom BCM470X / BCM5301X arm platform code.
|
||||
* DTS for Netgear R6250 V1
|
||||
*
|
||||
* Copyright 2013 Hauke Mehrtens <hauke@hauke-m.de>
|
||||
*
|
||||
* Licensed under the GNU/GPL. See COPYING for details.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "bcm4708.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "netgear,r6250v1", "brcm,bcm4708";
|
||||
model = "Netgear R6250 V1 (BCM4708)";
|
||||
|
||||
chosen {
|
||||
bootargs = "console=ttyS0,115200";
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
chipcommonA {
|
||||
uart0: serial@0300 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
uart1: serial@0400 {
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
logo {
|
||||
label = "bcm53xx:white:logo";
|
||||
gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
power0 {
|
||||
label = "bcm53xx:green:power";
|
||||
gpios = <&chipcommon 2 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
power1 {
|
||||
label = "bcm53xx:amber:power";
|
||||
gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
usb {
|
||||
label = "bcm53xx:blue:usb";
|
||||
gpios = <&chipcommon 8 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
|
||||
wireless {
|
||||
label = "bcm53xx:blue:wireless";
|
||||
gpios = <&chipcommon 11 GPIO_ACTIVE_LOW>;
|
||||
linux,default-trigger = "default-off";
|
||||
};
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wps {
|
||||
label = "WPS";
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
gpios = <&chipcommon 4 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
rfkill {
|
||||
label = "WiFi";
|
||||
linux,code = <KEY_RFKILL>;
|
||||
gpios = <&chipcommon 5 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
restart {
|
||||
label = "Reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&chipcommon 6 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
};
|
||||
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Reference in New Issue
Block a user