mirror of
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Add driver for usbclock generator for earlier amlogic chip.
Differential Revision: https://reviews.freebsd.org/D2590 Submitted by: John Wehle
This commit is contained in:
Ganbold Tsagaankhuu
parent
e39d48908b
commit
3c17c95097
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=283186
428
sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c
Normal file
428
sys/arm/amlogic/aml8726/aml8726_usb_phy-m3.c
Normal file
@ -0,0 +1,428 @@
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/*-
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* Copyright 2014-2015 John Wehle <john@feith.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Amlogic aml8726-m3 USB physical layer driver.
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*
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* Both USB physical interfaces share the same configuration register.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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struct aml8726_usb_phy_gpio {
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device_t dev;
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uint32_t pin;
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uint32_t pol;
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};
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struct aml8726_usb_phy_softc {
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device_t dev;
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struct resource *res[1];
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uint32_t npwr_en;
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struct aml8726_usb_phy_gpio *pwr_en;
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};
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static struct resource_spec aml8726_usb_phy_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define AML_USB_PHY_CFG_REG 0
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#define AML_USB_PHY_CFG_A_CLK_DETECTED (1U << 31)
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#define AML_USB_PHY_CFG_CLK_DIV_MASK (0x7f << 24)
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#define AML_USB_PHY_CFG_CLK_DIV_SHIFT 24
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#define AML_USB_PHY_CFG_B_CLK_DETECTED (1 << 22)
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#define AML_USB_PHY_CFG_A_PLL_RST (1 << 19)
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#define AML_USB_PHY_CFG_A_PHYS_RST (1 << 18)
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#define AML_USB_PHY_CFG_A_RST (1 << 17)
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#define AML_USB_PHY_CFG_B_PLL_RST (1 << 13)
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#define AML_USB_PHY_CFG_B_PHYS_RST (1 << 12)
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#define AML_USB_PHY_CFG_B_RST (1 << 11)
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#define AML_USB_PHY_CFG_CLK_EN (1 << 8)
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#define AML_USB_PHY_CFG_CLK_SEL_MASK (7 << 5)
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#define AML_USB_PHY_CFG_CLK_SEL_XTAL (0 << 5)
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#define AML_USB_PHY_CFG_CLK_SEL_XTAL_DIV2 (1 << 5)
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#define AML_USB_PHY_CFG_B_POR (1 << 1)
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#define AML_USB_PHY_CFG_A_POR (1 << 0)
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#define AML_USB_PHY_CFG_CLK_DETECTED \
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(AML_USB_PHY_CFG_A_CLK_DETECTED | AML_USB_PHY_CFG_B_CLK_DETECTED)
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#define AML_USB_PHY_MISC_A_REG 12
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#define AML_USB_PHY_MISC_B_REG 16
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#define AML_USB_PHY_MISC_ID_OVERIDE_EN (1 << 23)
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#define AML_USB_PHY_MISC_ID_OVERIDE_DEVICE (1 << 22)
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#define AML_USB_PHY_MISC_ID_OVERIDE_HOST (0 << 22)
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#define CSR_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], reg, (val))
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#define CSR_READ_4(sc, reg) bus_read_4((sc)->res[0], reg)
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#define CSR_BARRIER(sc, reg) bus_barrier((sc)->res[0], reg, 4, \
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(BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE))
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#define PIN_ON_FLAG(pol) ((pol) == 0 ? \
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GPIO_PIN_LOW : GPIO_PIN_HIGH)
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#define PIN_OFF_FLAG(pol) ((pol) == 0 ? \
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GPIO_PIN_HIGH : GPIO_PIN_LOW)
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static int
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aml8726_usb_phy_mode(const char *dwcotg_path, uint32_t *mode)
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{
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char *usb_mode;
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phandle_t node;
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ssize_t len;
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if ((node = OF_finddevice(dwcotg_path)) == 0)
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return (ENXIO);
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if (fdt_is_compatible_strict(node, "synopsys,designware-hs-otg2") == 0)
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return (ENXIO);
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*mode = 0;
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len = OF_getprop_alloc(node, "dr_mode",
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sizeof(char), (void **)&usb_mode);
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if (len <= 0)
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return (0);
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if (strcasecmp(usb_mode, "host") == 0) {
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*mode = AML_USB_PHY_MISC_ID_OVERIDE_EN |
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AML_USB_PHY_MISC_ID_OVERIDE_HOST;
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} else if (strcasecmp(usb_mode, "peripheral") == 0) {
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*mode = AML_USB_PHY_MISC_ID_OVERIDE_EN |
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AML_USB_PHY_MISC_ID_OVERIDE_DEVICE;
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}
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free(usb_mode, M_OFWPROP);
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return (0);
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}
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static int
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aml8726_usb_phy_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "amlogic,aml8726-m3-usb-phy"))
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return (ENXIO);
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device_set_desc(dev, "Amlogic aml8726-m3 USB PHY");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aml8726_usb_phy_attach(device_t dev)
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{
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struct aml8726_usb_phy_softc *sc = device_get_softc(dev);
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int err;
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int npwr_en;
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pcell_t *prop;
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phandle_t node;
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ssize_t len;
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uint32_t div;
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uint32_t i;
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uint32_t mode_a;
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uint32_t mode_b;
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uint32_t value;
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sc->dev = dev;
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if (aml8726_usb_phy_mode("/soc/usb@c9040000", &mode_a) != 0) {
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device_printf(dev, "missing usb@c9040000 node in FDT\n");
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return (ENXIO);
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}
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if (aml8726_usb_phy_mode("/soc/usb@c90c0000", &mode_b) != 0) {
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device_printf(dev, "missing usb@c90c0000 node in FDT\n");
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return (ENXIO);
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}
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if (bus_alloc_resources(dev, aml8726_usb_phy_spec, sc->res)) {
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device_printf(dev, "can not allocate resources for device\n");
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return (ENXIO);
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}
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node = ofw_bus_get_node(dev);
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err = 0;
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len = OF_getencprop_alloc(node, "usb-pwr-en",
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3 * sizeof(pcell_t), (void **)&prop);
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npwr_en = (len > 0) ? len : 0;
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sc->npwr_en = 0;
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sc->pwr_en = (struct aml8726_usb_phy_gpio *)
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malloc(npwr_en * sizeof (*sc->pwr_en), M_DEVBUF, M_WAITOK);
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for (i = 0; i < npwr_en; i++) {
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sc->pwr_en[i].dev = OF_device_from_xref(prop[i * 3]);
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sc->pwr_en[i].pin = prop[i * 3 + 1];
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sc->pwr_en[i].pol = prop[i * 3 + 2];
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if (sc->pwr_en[i].dev == NULL) {
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err = 1;
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break;
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}
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}
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free(prop, M_OFWPROP);
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if (err) {
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device_printf(dev, "unable to parse gpio\n");
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goto fail;
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}
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/* Turn on power by setting pin and then enabling output driver. */
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for (i = 0; i < npwr_en; i++) {
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if (GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin,
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PIN_ON_FLAG(sc->pwr_en[i].pol)) != 0 ||
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GPIO_PIN_SETFLAGS(sc->pwr_en[i].dev, sc->pwr_en[i].pin,
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GPIO_PIN_OUTPUT) != 0) {
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device_printf(dev,
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"could not use gpio to control power\n");
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goto fail;
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}
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sc->npwr_en++;
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}
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/*
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* Configure the clock source and divider.
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*/
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div = 2;
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value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
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value &= ~(AML_USB_PHY_CFG_CLK_DIV_MASK | AML_USB_PHY_CFG_CLK_SEL_MASK);
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value &= ~(AML_USB_PHY_CFG_A_RST | AML_USB_PHY_CFG_B_RST);
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value &= ~(AML_USB_PHY_CFG_A_PLL_RST | AML_USB_PHY_CFG_B_PLL_RST);
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value &= ~(AML_USB_PHY_CFG_A_PHYS_RST | AML_USB_PHY_CFG_B_PHYS_RST);
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value &= ~(AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR);
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value |= AML_USB_PHY_CFG_CLK_SEL_XTAL;
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value |= ((div - 1) << AML_USB_PHY_CFG_CLK_DIV_SHIFT) &
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AML_USB_PHY_CFG_CLK_DIV_MASK;
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value |= AML_USB_PHY_CFG_CLK_EN;
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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/*
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* Issue the reset sequence.
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*/
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value |= (AML_USB_PHY_CFG_A_RST | AML_USB_PHY_CFG_B_RST);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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value &= ~(AML_USB_PHY_CFG_A_RST | AML_USB_PHY_CFG_B_RST);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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value |= (AML_USB_PHY_CFG_A_PLL_RST | AML_USB_PHY_CFG_B_PLL_RST);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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value &= ~(AML_USB_PHY_CFG_A_PLL_RST | AML_USB_PHY_CFG_B_PLL_RST);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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value |= (AML_USB_PHY_CFG_A_PHYS_RST | AML_USB_PHY_CFG_B_PHYS_RST);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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value &= ~(AML_USB_PHY_CFG_A_PHYS_RST | AML_USB_PHY_CFG_B_PHYS_RST);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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/*
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* Enable by clearing the power on reset.
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*/
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value &= ~(AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR);
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CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
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CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
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DELAY(200);
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/*
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* Check if the clock was detected.
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*/
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value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
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if ((value & AML_USB_PHY_CFG_CLK_DETECTED) !=
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AML_USB_PHY_CFG_CLK_DETECTED)
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device_printf(dev, "PHY Clock not detected\n");
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/*
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* Configure the mode for each port.
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*/
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value = CSR_READ_4(sc, AML_USB_PHY_MISC_A_REG);
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value &= ~(AML_USB_PHY_MISC_ID_OVERIDE_EN |
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AML_USB_PHY_MISC_ID_OVERIDE_DEVICE |
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AML_USB_PHY_MISC_ID_OVERIDE_HOST);
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value |= mode_a;
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CSR_WRITE_4(sc, AML_USB_PHY_MISC_A_REG, value);
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value = CSR_READ_4(sc, AML_USB_PHY_MISC_B_REG);
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value &= ~(AML_USB_PHY_MISC_ID_OVERIDE_EN |
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AML_USB_PHY_MISC_ID_OVERIDE_DEVICE |
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AML_USB_PHY_MISC_ID_OVERIDE_HOST);
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value |= mode_b;
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CSR_WRITE_4(sc, AML_USB_PHY_MISC_B_REG, value);
|
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CSR_BARRIER(sc, AML_USB_PHY_MISC_B_REG);
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return (0);
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fail:
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/* In the event of problems attempt to turn things back off. */
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i = sc->npwr_en;
|
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while (i-- != 0) {
|
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GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin,
|
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PIN_OFF_FLAG(sc->pwr_en[i].pol));
|
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}
|
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free (sc->pwr_en, M_DEVBUF);
|
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sc->pwr_en = NULL;
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|
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bus_release_resources(dev, aml8726_usb_phy_spec, sc->res);
|
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|
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return (ENXIO);
|
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}
|
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|
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static int
|
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aml8726_usb_phy_detach(device_t dev)
|
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{
|
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struct aml8726_usb_phy_softc *sc = device_get_softc(dev);
|
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uint32_t i;
|
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uint32_t value;
|
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|
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/*
|
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* Disable by issuing a power on reset.
|
||||
*/
|
||||
|
||||
value = CSR_READ_4(sc, AML_USB_PHY_CFG_REG);
|
||||
|
||||
value |= (AML_USB_PHY_CFG_A_POR | AML_USB_PHY_CFG_B_POR);
|
||||
|
||||
CSR_WRITE_4(sc, AML_USB_PHY_CFG_REG, value);
|
||||
|
||||
CSR_BARRIER(sc, AML_USB_PHY_CFG_REG);
|
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|
||||
/* Turn off power */
|
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i = sc->npwr_en;
|
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while (i-- != 0) {
|
||||
(void)GPIO_PIN_SET(sc->pwr_en[i].dev, sc->pwr_en[i].pin,
|
||||
PIN_OFF_FLAG(sc->pwr_en[i].pol));
|
||||
}
|
||||
free (sc->pwr_en, M_DEVBUF);
|
||||
sc->pwr_en = NULL;
|
||||
|
||||
bus_release_resources(dev, aml8726_usb_phy_spec, sc->res);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static device_method_t aml8726_usb_phy_methods[] = {
|
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/* Device interface */
|
||||
DEVMETHOD(device_probe, aml8726_usb_phy_probe),
|
||||
DEVMETHOD(device_attach, aml8726_usb_phy_attach),
|
||||
DEVMETHOD(device_detach, aml8726_usb_phy_detach),
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t aml8726_usb_phy_driver = {
|
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"usbphy",
|
||||
aml8726_usb_phy_methods,
|
||||
sizeof(struct aml8726_usb_phy_softc),
|
||||
};
|
||||
|
||||
static devclass_t aml8726_usb_phy_devclass;
|
||||
|
||||
DRIVER_MODULE(aml8726_m3usbphy, simplebus, aml8726_usb_phy_driver,
|
||||
aml8726_usb_phy_devclass, 0, 0);
|
||||
MODULE_DEPEND(aml8726_m3usbphy, aml8726_gpio, 1, 1, 1);
|
||||
@ -30,6 +30,7 @@ arm/amlogic/aml8726/aml8726_sdxc-m8.c optional mmc gpio
|
||||
arm/amlogic/aml8726/aml8726_pinctrl.c optional fdt_pinctrl
|
||||
#arm/amlogic/aml8726/aml8726_rng.c optional random
|
||||
arm/amlogic/aml8726/uart_dev_aml8726.c optional uart
|
||||
arm/amlogic/aml8726/aml8726_usb_phy-m3.c optional dwcotg usb gpio
|
||||
arm/amlogic/aml8726/aml8726_usb_phy-m6.c optional dwcotg usb gpio
|
||||
|
||||
dev/dwc/if_dwc.c optional dwc
|
||||
|
||||
Loading…
Reference in New Issue
Block a user