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Add cache handling code for sparc64.
This commit is contained in:
Thomas Moestl
parent
8838ea170e
commit
3c78eb652c
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=86221
126
sys/sparc64/include/cache.h
Normal file
126
sys/sparc64/include/cache.h
Normal file
@ -0,0 +1,126 @@
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/*
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* Copyright (c) 1996
|
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* The President and Fellows of Harvard College. All rights reserved.
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This software was developed by the Computer Systems Engineering group
|
||||
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
|
||||
* contributed to Berkeley.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Aaron Brown and
|
||||
* Harvard University.
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
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*
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* from: @(#)cache.h 8.1 (Berkeley) 6/11/93
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* from: NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CACHE_H_
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#define _MACHINE_CACHE_H_
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/ofw/openfirm.h>
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/*
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* Cache diagnostic access definitions.
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*/
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/* ASI offsets for I$ diagnostic access */
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#define ICDA_SET_SHIFT 13
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#define ICDA_SET_MASK (1UL << 13)
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#define ICDA_SET(a) (((a) << ICDA_SET_SHIFT) & ICDA_SET_MASK)
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/* I$ tag/valid format */
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#define ICDT_TAG_SHIFT 8
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#define ICDT_TAG_BITS 28
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#define ICDT_TAG_MASK (((1UL << ICDT_TAG_BITS) - 1) << ICDT_TAG_SHIFT)
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#define ICDT_TAG(x) (((x) & ICDT_TAG_MASK) >> ICDT_TAG_SHIFT)
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#define ICDT_VALID (1UL << 36)
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/* D$ tag/valid format */
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#define DCDT_TAG_SHIFT 2
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#define DCDT_TAG_BITS 28
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#define DCDT_TAG_MASK (((1UL << DCDT_TAG_BITS) - 1) << DCDT_TAG_SHIFT)
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#define DCDT_TAG(x) (((x) & DCDT_TAG_MASK) >> DCDT_TAG_SHIFT)
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#define DCDT_VALID_BITS 2
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#define DCDT_VALID_MASK ((1UL << DCDT_VALID_BITS) - 1)
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/* E$ ASI_ECACHE_W/ASI_ECACHE_R address flags */
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#define ECDA_DATA (1UL << 39)
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#define ECDA_TAG (1UL << 40)
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/* E$ tag/state/parity format */
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#define ECDT_TAG_BITS 13
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#define ECDT_TAG_SIZE (1UL << ECDT_TAG_BITS)
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#define ECDT_TAG_MASK (ECDT_TAG_SIZE - 1)
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/*
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* Do two virtual addresses (at which the same page is mapped) form and illegal
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* alias in D$? XXX: should use cache.dc_size here.
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*/
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#define DCACHE_BOUNDARY 0x4000
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#define DCACHE_BMASK (DCACHE_BOUNDARY - 1)
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#define CACHE_BADALIAS(v1, v2) \
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(((v1) & DCACHE_BMASK) != ((v2) & DCACHE_BMASK))
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/*
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* Routines for dealing with the cache.
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*/
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void cache_init __P((phandle_t)); /* turn it on */
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void icache_flush __P((vm_offset_t, vm_offset_t));
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void icache_inval_phys __P((vm_offset_t, vm_offset_t));
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void dcache_flush __P((vm_offset_t, vm_offset_t));
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void dcache_inval __P((pmap_t, vm_offset_t, vm_offset_t));
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void dcache_blast __P((void));
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void ecache_flush __P((vm_offset_t, vm_offset_t));
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#if 0
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void ecache_inval_phys __P((vm_offset_t, vm_offset_t));
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#endif
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/*
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* Cache control information.
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*/
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struct cacheinfo {
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int c_enabled; /* true => cache is enabled */
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int ic_size; /* instruction cache */
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int ic_l2set;
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int ic_assoc;
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int ic_linesize;
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int dc_size; /* data cache */
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int dc_l2size;
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int dc_assoc;
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int dc_linesize;
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int ec_size; /* external cache info */
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int ec_assoc;
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int ec_l2set;
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int ec_linesize;
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int ec_l2linesize;
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};
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#endif /* !_MACHINE_CACHE_H_ */
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405
sys/sparc64/sparc64/cache.c
Normal file
405
sys/sparc64/sparc64/cache.c
Normal file
@ -0,0 +1,405 @@
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/*
|
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* Copyright (c) 1996
|
||||
* The President and Fellows of Harvard College. All rights reserved.
|
||||
* Copyright (c) 1992, 1993
|
||||
* The Regents of the University of California. All rights reserved.
|
||||
*
|
||||
* This software was developed by the Computer Systems Engineering group
|
||||
* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
|
||||
* contributed to Berkeley.
|
||||
*
|
||||
* All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Harvard University.
|
||||
* This product includes software developed by the University of
|
||||
* California, Lawrence Berkeley Laboratory.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Aaron Brown and
|
||||
* Harvard University.
|
||||
* This product includes software developed by the University of
|
||||
* California, Berkeley and its contributors.
|
||||
* 4. Neither the name of the University nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
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* SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2001 by Thomas Moestl <tmm@FreeBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
||||
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
|
||||
* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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* from: @(#)cache.c 8.2 (Berkeley) 10/30/93
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* from: NetBSD: cache.c,v 1.5 2000/12/06 01:47:50 mrg Exp
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*
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* $FreeBSD$
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*/
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/*
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* Cache routines.
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*
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* UltraSPARCs have an virtually indexed, physically tagged (VIPT) level 1 data
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* cache (D$) and physically indexed, physically tagged (PIPT) level 1
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* instruction (I$) and Level 2 (E$) caches.
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* D$ is directly mapped, I$ is pseudo 2-way associative. The Level 2 cache (E$)
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* is documented to be directly mapped on the UltraSPARC IIi, but there are
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* apparently models (using the IIe version) that have a 4-way associative E$.
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*
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* D$ uses a write-through model, while E$ uses write-back and is
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* write-allocating. The lines present in D$ are forced to be a subset of those
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* in E$.
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* This means that lines that are present in D$ always have an identical
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* corresponding (sub-) line in E$.
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*
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* The term "main memory" is used in the following to refer to the non-cache
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* memory as well as to memory-mapped device i/o space.
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*
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* There are 3 documented ways to flush the D$ and E$ caches:
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* - displacement flushing (a sequence of loads of addresses that alias to
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* to-be-flushed ones in the caches). This only works for directly mapped
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* caches, and is recommended to flush D$ and E$ in the IIi manual. It is not
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* used to flush E$ because of the aforementioned models that have a
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* multiple-associative E$. Displacement flushing invalidates the cache
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* entries and writes modified lines back to main memory.
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* - diagnostic acceses can be used to invalidate cache pages. All lines
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* are discarded, which means that changes in D$/E$ that have not been
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* committed to main memory are lost.
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* - block-commit stores. Those use the block transfer ASIs to load a
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* 64-byte block to a set of FP registers and store them back using a
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* special ASI that will cause the data to be immediately committed to main
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* memory. This method has the same properties as the first method, but
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* (hopefully) works regardless of the associativity of the caches. It is
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* expected to be slow.
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*
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* I$ can be handled using the flush instruction.
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*
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* Some usage guidelines:
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*
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* The inval functions are variants of the flush ones that discard modified
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* cache lines.
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* PCI DMA transactions are cache-coherent and do not require flushing
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* before DMA reads or after DMA writes. It is unclear from the manual
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* how far this applies to UPA transactions.
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*
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* icache_flush(): needed before code that has been written to memory is
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* executed, because I$ is not necessarily consistent with D$, E$, or
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* main memory. An exception is that I$ snoops DMA transfers, so no
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* flush is required after to-be-executed data has been fetched this way.
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* icache_inval_phys(): has roughly same effect as icache_flush() since there
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* are no writes to I$.
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*
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* dcache_flush(): required when a page mapping is changed from cacheable to
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* noncacheable, or to resolve illegal aliases. Both cases should happen
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* seldom. Mapping address changes do not require this, since D$ is VIPT.
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* dcache_inval(): has roughly same effect as dcache_flush() since D$ is
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* write-through.
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* dcache_blast(): discards all lines in D$.
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*
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* ecache_flush(): needed to commit modified lines to main memory, and to make
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* sure that no stale data is used when the main memory has changed without
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* the cache controller noticing. This is e.g. needed for device i/o space.
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* It is usually better to use a non-cacheable mapping in this case.
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* ecache_flush() is guaranteed to also flush the relevant addresses out of
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* D$.
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* ecache_inval_phys(): like ecache_flush(), but invalidates a physical range
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* in the cache. This function is usually dangerous and should not be used.
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*
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* All operations have a line size granularity!
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*
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* All flush methods tend to be expensive, so unnecessary flushes should be
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* avoided.
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*/
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#include <sys/param.h>
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#include <sys/proc.h>
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#include <sys/systm.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cache.h>
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#include <machine/cpufunc.h>
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#include <machine/fp.h>
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#include <machine/pcb.h>
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#include <machine/pmap.h>
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#include <machine/tte.h>
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#include <machine/vmparam.h>
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static struct cacheinfo cache;
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#define CDIAG_CLR(asi, addr) \
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__asm __volatile("stxa %%g0, [%0] %1" : : "r" (addr), "I" (asi))
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/* Read to %g0, needed for E$ access. */
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#define CDIAG_RDG0(asi, addr) \
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__asm __volatile("ldxa [%0] %1, %%g0" : : "r" (addr), "I" (asi))
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#define CDIAG_RD(asi, addr, r) \
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__asm __volatile("ldxa [%1] %2, %0" : "=r" (r) : "r" (addr), "I" (asi))
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/* Sigh. I$ diagnostic registers want ldda. */
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#define ICDIAG_RD(asi, addr, r) \
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__asm __volatile("ldda [%1] %2, %%o4; mov %%o5, %0" : "=r" (r) : \
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"r" (addr), "I" (asi) : "%o4", "%o5");
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#define OF_GET(h, n, v) OF_getprop((h), (n), &(v), sizeof(v))
|
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/*
|
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* Fill in the cache parameters using the cpu node.
|
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*/
|
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void
|
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cache_init(phandle_t node)
|
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{
|
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u_long set;
|
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|
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if (OF_GET(node, "icache-size", cache.ic_size) == -1 ||
|
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OF_GET(node, "icache-line-size", cache.ic_linesize) == -1 ||
|
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OF_GET(node, "icache-associativity", cache.ic_assoc) == -1 ||
|
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OF_GET(node, "dcache-size", cache.dc_size) == -1 ||
|
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OF_GET(node, "dcache-line-size", cache.dc_linesize) == -1 ||
|
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OF_GET(node, "dcache-associativity", cache.dc_assoc) == -1 ||
|
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OF_GET(node, "ecache-size", cache.ec_size) == -1 ||
|
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OF_GET(node, "ecache-line-size", cache.ec_linesize) == -1 ||
|
||||
OF_GET(node, "ecache-associativity", cache.ec_assoc) == -1)
|
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panic("cache_init: could not retrieve cache parameters");
|
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|
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set = cache.ic_size / cache.ic_assoc;
|
||||
cache.ic_l2set = ffs(set) - 1;
|
||||
if ((set & ~(1UL << cache.ic_l2set)) != 0)
|
||||
panic("cache_init: I$ set size not a power of 2");
|
||||
cache.dc_l2size = ffs(cache.dc_size) - 1;
|
||||
if ((cache.dc_size & ~(1UL << cache.dc_l2size)) != 0)
|
||||
panic("cache_init: D$ size not a power of 2");
|
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if (cache.dc_assoc != 1)
|
||||
panic("cache_init: D$ is not directly mapped!");
|
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set = cache.ec_size / cache.ec_assoc;
|
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cache.ec_l2set = ffs(set) - 1;
|
||||
if ((set & ~(1UL << cache.ec_l2set)) != 0)
|
||||
panic("cache_init: E$ set size not a power of 2");
|
||||
cache.c_enabled = 1; /* enable cache flushing */
|
||||
}
|
||||
|
||||
/* Flush a range of addresses from I$ using the flush instruction. */
|
||||
void
|
||||
icache_flush(vm_offset_t start, vm_offset_t end)
|
||||
{
|
||||
char *p, *ep;
|
||||
int ls;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
|
||||
ls = cache.ic_linesize;
|
||||
ep = (char *)ulmin(end, start + cache.ic_size);
|
||||
for (p = (char *)start; p < ep; p += ls)
|
||||
flush(p);
|
||||
}
|
||||
|
||||
/*
|
||||
* Blast a I$ physical range using diagnostic accesses.
|
||||
* NOTE: there is a race between checking the tag and invalidating it. It
|
||||
* cannot be closed by disabling interrupts, since the fetch for the next
|
||||
* instruction may be in that line, so we don't even bother.
|
||||
* Since blasting a line does not discard data, this has no ill effect except
|
||||
* a minor slowdown.
|
||||
*/
|
||||
void
|
||||
icache_inval_phys(vm_offset_t start, vm_offset_t end)
|
||||
{
|
||||
vm_offset_t addr, ica;
|
||||
u_long tag;
|
||||
u_long j;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
|
||||
for (addr = start & ~(cache.ic_linesize - 1); addr <= end;
|
||||
addr += cache.ic_linesize) {
|
||||
for (j = 0; j < 2; j++) {
|
||||
ica = (addr & (cache.ic_size - 1)) | ICDA_SET(j);
|
||||
ICDIAG_RD(ASI_ICACHE_TAG, ica, tag);
|
||||
if (ICDT_TAG(tag) != addr >> cache.ic_l2set)
|
||||
continue;
|
||||
CDIAG_CLR(ASI_ICACHE_TAG, ica);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Flush a range of addresses from D$ using displacement flushes. This does
|
||||
* not necessarily flush E$, because we do not take care of flushing the
|
||||
* correct physical colors and E$ may not be directly mapped.
|
||||
*/
|
||||
void
|
||||
dcache_flush(vm_offset_t start, vm_offset_t end)
|
||||
{
|
||||
int j;
|
||||
vm_offset_t baseoff;
|
||||
u_long i, mask;
|
||||
char *kp;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
|
||||
mask = cache.dc_size - 1;
|
||||
/* No need to flush lines more than once. */
|
||||
baseoff = start & mask;
|
||||
/*
|
||||
* Use a locked page for flushing. D$ should be smaller than 4M, which
|
||||
* is somewhat likely...
|
||||
*/
|
||||
kp = (char *)KERNBASE;
|
||||
j = 0;
|
||||
for (i = 0; i <= ulmin((end - start), cache.dc_size);
|
||||
i += cache.dc_linesize)
|
||||
j += kp[(baseoff + i) & mask];
|
||||
}
|
||||
|
||||
/*
|
||||
* Blast a D$ range using diagnostic accesses.
|
||||
* This has the same (harmless) races as icache_blast().
|
||||
* Assumes a page in the kernel map.
|
||||
*/
|
||||
void
|
||||
dcache_inval(pmap_t pmap, vm_offset_t start, vm_offset_t end)
|
||||
{
|
||||
vm_offset_t va, pa, offs, dca;
|
||||
u_long tag;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
for (va = start & ~(cache.dc_linesize - 1); va <= end;
|
||||
va = (va + PAGE_SIZE_MIN) & ~PAGE_MASK_MIN) {
|
||||
if ((pa = pmap_extract(pmap, va)) == 0)
|
||||
continue;
|
||||
for (offs = start & PAGE_MASK_MIN;
|
||||
offs < ulmin(PAGE_SIZE_MIN, end - va + 1);
|
||||
offs += cache.dc_linesize) {
|
||||
dca = (va + offs) & (cache.dc_size - 1);
|
||||
CDIAG_RD(ASI_DCACHE_TAG, dca, tag);
|
||||
if (DCDT_TAG(tag) != (pa + offs) >> PAGE_SHIFT_MIN)
|
||||
continue;
|
||||
CDIAG_CLR(ASI_DCACHE_TAG, dca);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Discard all lines in D$. */
|
||||
void
|
||||
dcache_blast()
|
||||
{
|
||||
vm_offset_t dca;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
for (dca = 0; dca < cache.dc_size; dca += cache.dc_linesize)
|
||||
CDIAG_CLR(ASI_DCACHE_TAG, dca);
|
||||
}
|
||||
|
||||
/* Flush a E$ physical range using block commit stores. */
|
||||
void
|
||||
ecache_flush(vm_offset_t start, vm_offset_t end)
|
||||
{
|
||||
vm_offset_t addr;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
|
||||
/* XXX: not needed in all cases, provide a wrapper in fp.c */
|
||||
savefpctx(&curthread->td_pcb->pcb_fpstate);
|
||||
wr(fprs, 0, FPRS_FEF);
|
||||
|
||||
for (addr = start & ~(cache.ec_linesize - 1); addr <= end;
|
||||
addr += cache.ec_linesize) {
|
||||
__asm __volatile("ldda [%0] %1, %%f0; membar #Sync; "
|
||||
"stda %%f0, [%0] %2" : : "r" (addr), "I" (ASI_BLK_S),
|
||||
"I" (ASI_BLK_COMMIT_S));
|
||||
}
|
||||
membar(Sync);
|
||||
|
||||
restorefpctx(&curthread->td_pcb->pcb_fpstate);
|
||||
}
|
||||
|
||||
#if 0
|
||||
/*
|
||||
* Blast a E$ range using diagnostic accesses.
|
||||
* This is disabled: it suffers from the same races as dcache_blast() and
|
||||
* icache_blast_phys(), but they may be fatal here because blasting an E$ line
|
||||
* can discard modified data.
|
||||
* There is no really use for this anyway.
|
||||
*/
|
||||
void
|
||||
ecache_inval_phys(vm_offset_t start, vm_offset_t end)
|
||||
{
|
||||
vm_offset_t addr, eca;
|
||||
critical_t c;
|
||||
u_long tag, j;
|
||||
|
||||
if (!cache.c_enabled)
|
||||
return;
|
||||
|
||||
for (addr = start & ~(cache.ec_linesize - 1); addr <= end;
|
||||
addr += cache.ec_linesize) {
|
||||
for (j = 0; j < cache.ec_assoc; j++) {
|
||||
/* XXX: guesswork... */
|
||||
eca = (addr & (cache.ec_size - 1)) |
|
||||
(j << (cache.ec_l2set));
|
||||
c = critical_enter();
|
||||
/*
|
||||
* Retrieve the tag:
|
||||
* A read from the appropriate VA in ASI_ECACHE_R
|
||||
* will transfer the tag from the tag RAM to the
|
||||
* data register (ASI_ECACHE_TAG_DATA, VA 0).
|
||||
*/
|
||||
CDIAG_RDG0(ASI_ECACHE_R, ECDA_TAG | eca);
|
||||
CDIAG_RD(ASI_ECACHE_TAG_DATA, 0, tag);
|
||||
if ((addr & ~cache.ec_size) >> cache.ec_l2set ==
|
||||
(tag & ECDT_TAG_MASK)) {
|
||||
/*
|
||||
* Clear. Works like retrieving the tag, but
|
||||
* the other way round.
|
||||
*/
|
||||
CDIAG_CLR(ASI_ECACHE_TAG_DATA, 0);
|
||||
CDIAG_CLR(ASI_ECACHE_W, ECDA_TAG | eca);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user