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Minor cleanup of the Promise code.
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parent
66abb7a636
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3cb179a848
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=111812
@ -926,14 +926,17 @@ ata_promise_ident(device_t dev)
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{ ATA_PDC20263, 0, PRNEW, 0x00, ATA_UDMA4, "Promise" },
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{ ATA_PDC20265, 0, PRNEW, 0x00, ATA_UDMA5, "Promise" },
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{ ATA_PDC20267, 0, PRNEW, 0x00, ATA_UDMA5, "Promise" },
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{ ATA_PDC20268, 0, PRTX2, PRTX4, ATA_UDMA5, "Promise TX2" },
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{ ATA_PDC20268R, 0, PRTX2, PRTX4, ATA_UDMA5, "Promise TX2" },
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{ ATA_PDC20269, 0, PRTX2, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20271, 0, PRTX2, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20275, 0, PRTX2, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20276, 0, PRTX2, PRSX6K, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20277, 0, PRTX2, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20376, 0, PRTX2, 0x00, ATA_UDMA6, "Promise SATA" },
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{ ATA_PDC20268, 0, PRTX, PRTX4, ATA_UDMA5, "Promise TX2" },
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{ ATA_PDC20268R, 0, PRTX, PRTX4, ATA_UDMA5, "Promise TX2" },
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{ ATA_PDC20269, 0, PRTX, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20271, 0, PRTX, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20275, 0, PRTX, 0x00, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20276, 0, PRTX, PRSX6K, ATA_UDMA6, "Promise TX2" },
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{ ATA_PDC20277, 0, PRTX, 0x00, ATA_UDMA6, "Promise TX2" },
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#if notyet
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{ ATA_PDC20376, 0, PRCH, 0x00, ATA_UDMA6, "Promise SATA" },
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{ ATA_PDC20621, 0, PRCH, 0x00, ATA_UDMA6, "Promise SX4000" },
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#endif
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{ 0, 0, 0, 0, 0, 0}};
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char *desc, buffer[64];
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uintptr_t devid = 0;
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@ -942,20 +945,19 @@ ata_promise_ident(device_t dev)
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return ENXIO;
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/* if we are on a SuperTrak SX6000 dont attach */
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if (idx->cfg2 & PRSX6K &&
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if ((idx->cfg2 & PRSX6K) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
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!BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
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GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
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devid == ATA_I960RM && pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE)
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devid == ATA_I960RM)
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return ENXIO;
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if (idx->cfg2 & PRTX4 &&
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/* if we are on a FastTrak TX4, adjust the interrupt resource */
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if ((idx->cfg2 & PRTX4) && pci_get_class(GRANDPARENT(dev))==PCIC_BRIDGE &&
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!BUS_READ_IVAR(device_get_parent(GRANDPARENT(dev)),
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GRANDPARENT(dev), PCI_IVAR_DEVID, &devid) &&
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devid == ATA_DEC_21150 &&
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pci_get_class(GRANDPARENT(dev)) == PCIC_BRIDGE) {
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devid == ATA_DEC_21150) {
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static long start = 0, end = 0;
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/* we belive we are on a TX4, now do our (simple) magic */
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if (pci_get_slot(dev) == 1) {
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bus_get_resource(dev, SYS_RES_IRQ, 0, &start, &end);
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desc = "Promise TX4 (channel 0+1)";
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@ -991,7 +993,7 @@ ata_promise_chipinit(device_t dev)
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return ENXIO;
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}
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if ((bus_setup_intr(dev, ctlr->r_irq, INTR_TYPE_BIO | INTR_ENTROPY,
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ctlr->chip->cfg1 == PRTX2 ?
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ctlr->chip->cfg1 == PRTX ?
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ata_promise_tx2_intr : ata_promise_intr,
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ctlr, &ctlr->handle))) {
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device_printf(dev, "unable to setup interrupt\n");
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@ -1083,7 +1085,7 @@ ata_promise_setmode(struct ata_device *atadev, int mode)
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mode = ata_limit_mode(atadev, mode, ctlr->chip->max_dma);
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/* is this a TX2 or later chip ? */
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if (ctlr->chip->cfg1 >= PRTX2) {
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if (ctlr->chip->cfg1 >= PRTX) {
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ATA_OUTB(atadev->channel->r_bmio, ATA_BMDEVSPEC_0, 0x0b);
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if (mode > ATA_UDMA2 &&
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ATA_INB(atadev->channel->r_bmio, ATA_BMDEVSPEC_1) & 0x04) {
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@ -1110,7 +1112,7 @@ ata_promise_setmode(struct ata_device *atadev, int mode)
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(error) ? "failed" : "success",
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ata_mode2str(mode), ctlr->chip->text);
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if (!error) {
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if (ctlr->chip->cfg1 < PRTX2)
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if (ctlr->chip->cfg1 < PRTX)
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pci_write_config(device_get_parent(atadev->channel->dev),
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0x60 + (devno << 2),
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timings33[ctlr->chip->cfg1][ata_mode2idx(mode)],4);
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@ -128,6 +128,7 @@ struct ata_pci_controller {
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#define ATA_PDC20276 0x5275105a
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#define ATA_PDC20277 0x7275105a
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#define ATA_PDC20376 0x3376105a
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#define ATA_PDC20621 0x6621105a
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#define ATA_SERVERWORKS_ID 0x1166
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#define ATA_ROSB4 0x02111166
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@ -212,7 +213,8 @@ struct ata_pci_controller {
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#define PROLD 0
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#define PRNEW 1
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#define PRTX2 2
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#define PRTX 2
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#define PRCH 3
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#define PRTX4 0x01
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#define PRSX6K 0x02
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