mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-27 11:55:06 +00:00
Enhance the support for PCI legacy INTx interrupts and enable them in
the virtio backends. - Add a new ioctl to export the count of pins on the I/O APIC from vmm to the hypervisor. - Use pins on the I/O APIC >= 16 for PCI interrupts leaving 0-15 for ISA interrupts. - Populate the MP Table with I/O interrupt entries for any PCI INTx interrupts. - Create a _PRT table under the PCI root bridge in ACPI to route any PCI INTx interrupts appropriately. - Track which INTx interrupts are in use per-slot so that functions that share a slot attempt to distribute their INTx interrupts across the four available pins. - Implicitly mask INTx interrupts if either MSI or MSI-X is enabled and when the INTx DIS bit is set in a function's PCI command register. Either assert or deassert the associated I/O APIC pin when the state of one of those conditions changes. - Add INTx support to the virtio backends. - Always advertise the MSI capability in the virtio backends. Submitted by: neel (7) Reviewed by: neel MFC after: 2 weeks
This commit is contained in:
John Baldwin
parent
819c6bfc81
commit
3cbf3585cb
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=261268
@ -453,6 +453,13 @@ vm_ioapic_pulse_irq(struct vmctx *ctx, int irq)
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return (ioctl(ctx->fd, VM_IOAPIC_PULSE_IRQ, &ioapic_irq));
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}
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int
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vm_ioapic_pincount(struct vmctx *ctx, int *pincount)
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{
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return (ioctl(ctx->fd, VM_IOAPIC_PINCOUNT, pincount));
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}
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int
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vm_inject_nmi(struct vmctx *ctx, int vcpu)
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{
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@ -72,6 +72,7 @@ int vm_lapic_msi(struct vmctx *ctx, uint64_t addr, uint64_t msg);
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int vm_ioapic_assert_irq(struct vmctx *ctx, int irq);
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int vm_ioapic_deassert_irq(struct vmctx *ctx, int irq);
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int vm_ioapic_pulse_irq(struct vmctx *ctx, int irq);
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int vm_ioapic_pincount(struct vmctx *ctx, int *pincount);
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int vm_inject_nmi(struct vmctx *ctx, int vcpu);
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int vm_capability_name2type(const char *capname);
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const char *vm_capability_type2name(int type);
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@ -181,7 +181,8 @@ enum {
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IOCNUM_IOAPIC_DEASSERT_IRQ = 34,
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IOCNUM_IOAPIC_PULSE_IRQ = 35,
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IOCNUM_LAPIC_MSI = 36,
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IOCNUM_LAPIC_LOCAL_IRQ = 37,
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IOCNUM_LAPIC_LOCAL_IRQ = 37,
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IOCNUM_IOAPIC_PINCOUNT = 38,
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/* PCI pass-thru */
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IOCNUM_BIND_PPTDEV = 40,
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@ -228,6 +229,8 @@ enum {
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_IOW('v', IOCNUM_IOAPIC_DEASSERT_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_PULSE_IRQ \
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_IOW('v', IOCNUM_IOAPIC_PULSE_IRQ, struct vm_ioapic_irq)
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#define VM_IOAPIC_PINCOUNT \
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_IOR('v', IOCNUM_IOAPIC_PINCOUNT, int)
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#define VM_SET_CAPABILITY \
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_IOW('v', IOCNUM_SET_CAPABILITY, struct vm_capability)
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#define VM_GET_CAPABILITY \
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@ -318,6 +318,9 @@ vmmdev_ioctl(struct cdev *cdev, u_long cmd, caddr_t data, int fflag,
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ioapic_irq = (struct vm_ioapic_irq *)data;
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error = vioapic_pulse_irq(sc->vm, ioapic_irq->irq);
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break;
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case VM_IOAPIC_PINCOUNT:
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*(int *)data = vioapic_pincount(sc->vm);
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break;
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case VM_MAP_MEMORY:
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seg = (struct vm_memory_segment *)data;
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error = vm_malloc(sc->vm, seg->gpa, seg->len);
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@ -17,7 +17,7 @@ SRCS= \
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dbgport.c \
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elcr.c \
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inout.c \
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legacy_irq.c \
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ioapic.c \
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mem.c \
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mevent.c \
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mptbl.c \
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@ -55,7 +55,7 @@ __FBSDID("$FreeBSD$");
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#include "acpi.h"
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#include "inout.h"
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#include "dbgport.h"
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#include "legacy_irq.h"
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#include "ioapic.h"
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#include "mem.h"
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#include "mevent.h"
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#include "mptbl.h"
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@ -695,7 +695,7 @@ main(int argc, char *argv[])
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init_mem();
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init_inout();
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legacy_irq_init();
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ioapic_init(ctx);
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rtc_init(ctx);
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@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* Copyright (c) 2014 Advanced Computing Technologies LLC
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* Written by: John H. Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -11,10 +12,10 @@
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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@ -22,59 +23,52 @@
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <stdbool.h>
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#include <assert.h>
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <machine/vmm.h>
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#include <vmmapi.h>
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#include "ioapic.h"
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/*
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* Used to keep track of legacy interrupt owners/requestors
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* Assign PCI INTx interrupts to I/O APIC pins in a round-robin
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* fashion. Note that we have no idea what the HPET is using, but the
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* HPET is also programmable whereas this is intended for hardwired
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* PCI interrupts.
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*
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* This assumes a single I/O APIC where pins >= 16 are permitted for
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* PCI devices.
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*/
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#define NLIRQ 16
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static struct lirqinfo {
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bool li_generic;
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bool li_allocated;
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} lirq[NLIRQ];
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static int pci_pins;
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void
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legacy_irq_init(void)
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ioapic_init(struct vmctx *ctx)
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{
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/*
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* Allow ISA IRQs 5,10,11,12, and 15 to be available for generic use.
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*/
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lirq[5].li_generic = true;
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lirq[10].li_generic = true;
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lirq[11].li_generic = true;
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lirq[12].li_generic = true;
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lirq[15].li_generic = true;
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if (vm_ioapic_pincount(ctx, &pci_pins) < 0) {
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pci_pins = 0;
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return;
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}
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/* Ignore the first 16 pins. */
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if (pci_pins <= 16) {
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pci_pins = 0;
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return;
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}
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pci_pins -= 16;
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}
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int
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legacy_irq_alloc(int irq)
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ioapic_pci_alloc_irq(void)
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{
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int i;
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static int last_pin;
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assert(irq < NLIRQ);
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if (irq < 0) {
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for (i = 0; i < NLIRQ; i++) {
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if (lirq[i].li_generic && !lirq[i].li_allocated) {
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irq = i;
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break;
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}
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}
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} else {
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if (lirq[irq].li_allocated)
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irq = -1;
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}
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if (irq >= 0) {
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lirq[irq].li_allocated = true;
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return (irq);
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} else
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if (pci_pins == 0)
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return (-1);
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return (16 + (last_pin++ % pci_pins));
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}
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@ -1,5 +1,6 @@
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/*-
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* Copyright (c) 2013 Neel Natu <neel@freebsd.org>
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* Copyright (c) 2014 Advanced Computing Technologies LLC
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* Written by: John H. Baldwin <jhb@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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@ -11,10 +12,10 @@
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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@ -26,16 +27,13 @@
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* $FreeBSD$
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*/
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#ifndef _LEGACY_IRQ_H_
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#define _LEGACY_IRQ_H_
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#ifndef _IOAPIC_H_
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#define _IOAPIC_H_
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/*
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* Allocate a legacy irq. The argument 'irq' can be set to -1 to allocate any
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* available irq.
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*
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* Returns -1 on failure or the allocated irq number on success.
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* Allocate a PCI IRQ from the I/O APIC.
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*/
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int legacy_irq_alloc(int irq);
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void legacy_irq_init(void);
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void ioapic_init(struct vmctx *ctx);
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int ioapic_pci_alloc_irq(void);
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#endif
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@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
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#include "acpi.h"
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#include "bhyverun.h"
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#include "mptbl.h"
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#include "pci_emul.h"
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#define MPTABLE_BASE 0xF0000
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@ -75,9 +76,6 @@ __FBSDID("$FreeBSD$");
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/* Number of local intr entries */
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#define MPEII_NUM_LOCAL_IRQ 2
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/* Number of i/o intr entries */
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#define MPEII_MAX_IRQ 24
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/* Bus entry defines */
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#define MPE_NUM_BUSES 2
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#define MPE_BUSNAME_LEN 6
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@ -195,8 +193,42 @@ mpt_build_ioapic_entries(io_apic_entry_ptr mpei, int id)
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mpei->apic_address = IOAPIC_PADDR;
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}
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static int
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mpt_count_ioint_entries(void)
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{
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/*
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* Always include entries for the first 16 pins along with a entry
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* for each active PCI INTx pin.
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*/
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return (16 + pci_count_lintr());
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}
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static void
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mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
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mpt_generate_pci_int(int slot, int pin, int ioapic_irq, void *arg)
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{
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int_entry_ptr *mpiep, mpie;
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mpiep = arg;
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mpie = *mpiep;
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memset(mpie, 0, sizeof(*mpie));
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/*
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* This is always after another I/O interrupt entry, so cheat
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* and fetch the I/O APIC ID from the prior entry.
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*/
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mpie->type = MPCT_ENTRY_INT;
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mpie->int_type = INTENTRY_TYPE_INT;
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mpie->src_bus_id = 0;
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mpie->src_bus_irq = slot << 2 | (pin - 1);
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mpie->dst_apic_id = mpie[-1].dst_apic_id;
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mpie->dst_apic_int = ioapic_irq;
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*mpiep = mpie + 1;
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}
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static void
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mpt_build_ioint_entries(int_entry_ptr mpie, int id)
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{
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int pin;
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@ -206,8 +238,8 @@ mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
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* just use the default config, tweek later if needed.
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*/
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/* Run through all 16 pins. */
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for (pin = 0; pin < num_pins; pin++) {
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/* First, generate the first 16 pins. */
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for (pin = 0; pin < 16; pin++) {
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memset(mpie, 0, sizeof(*mpie));
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mpie->type = MPCT_ENTRY_INT;
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mpie->src_bus_id = 1;
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@ -235,16 +267,6 @@ mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
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mpie->int_type = INTENTRY_TYPE_INT;
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mpie->src_bus_irq = SCI_INT;
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break;
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case 5:
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case 10:
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case 11:
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/*
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* PCI Irqs set to level triggered and active-lo.
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*/
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mpie->int_flags = INTENTRY_FLAGS_POLARITY_ACTIVELO |
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INTENTRY_FLAGS_TRIGGER_LEVEL;
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mpie->src_bus_id = 0;
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/* fall through.. */
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default:
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/* All other pins are identity mapped. */
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mpie->int_type = INTENTRY_TYPE_INT;
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@ -254,6 +276,8 @@ mpt_build_ioint_entries(int_entry_ptr mpie, int num_pins, int id)
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mpie++;
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}
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/* Next, generate entries for any PCI INTx interrupts. */
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pci_walk_lintr(mpt_generate_pci_int, &mpie);
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}
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void
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@ -273,6 +297,7 @@ mptable_build(struct vmctx *ctx, int ncpu)
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proc_entry_ptr mpep;
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mpfps_t mpfp;
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int_entry_ptr mpie;
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int ioints;
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char *curraddr;
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char *startaddr;
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@ -307,9 +332,10 @@ mptable_build(struct vmctx *ctx, int ncpu)
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mpch->entry_count++;
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mpie = (int_entry_ptr) curraddr;
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mpt_build_ioint_entries(mpie, MPEII_MAX_IRQ, 0);
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curraddr += sizeof(*mpie) * MPEII_MAX_IRQ;
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mpch->entry_count += MPEII_MAX_IRQ;
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ioints = mpt_count_ioint_entries();
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mpt_build_ioint_entries(mpie, 0);
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curraddr += sizeof(*mpie) * ioints;
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mpch->entry_count += ioints;
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mpie = (int_entry_ptr)curraddr;
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mpt_build_localint_entries(mpie);
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@ -34,6 +34,7 @@ __FBSDID("$FreeBSD$");
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#include <sys/errno.h>
|
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|
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#include <ctype.h>
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#include <pthread.h>
|
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#include <stdio.h>
|
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#include <stdlib.h>
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#include <string.h>
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@ -47,7 +48,7 @@ __FBSDID("$FreeBSD$");
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#include "acpi.h"
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#include "bhyverun.h"
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#include "inout.h"
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#include "legacy_irq.h"
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#include "ioapic.h"
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#include "mem.h"
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#include "pci_emul.h"
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#include "pci_lpc.h"
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@ -71,11 +72,21 @@ do { \
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#define MAXSLOTS (PCI_SLOTMAX + 1)
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#define MAXFUNCS (PCI_FUNCMAX + 1)
|
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|
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static struct slotinfo {
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char *si_name;
|
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char *si_param;
|
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struct pci_devinst *si_devi;
|
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} pci_slotinfo[MAXSLOTS][MAXFUNCS];
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struct funcinfo {
|
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char *fi_name;
|
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char *fi_param;
|
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struct pci_devinst *fi_devi;
|
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};
|
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|
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struct intxinfo {
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int ii_count;
|
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int ii_ioapic_irq;
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};
|
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|
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struct slotinfo {
|
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struct intxinfo si_intpins[4];
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struct funcinfo si_funcs[MAXFUNCS];
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} pci_slotinfo[MAXSLOTS];
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|
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SET_DECLARE(pci_devemu_set, struct pci_devemu);
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@ -92,6 +103,7 @@ static uint64_t pci_emul_membase64;
|
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#define PCI_EMUL_MEMLIMIT64 0xFD00000000UL
|
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|
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static struct pci_devemu *pci_emul_finddev(char *name);
|
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static void pci_lintr_update(struct pci_devinst *pi);
|
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|
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static int pci_emul_devices;
|
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static struct mem_range pci_mem_hole;
|
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@ -154,7 +166,7 @@ pci_parse_slot(char *opt)
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goto done;
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}
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if (pci_slotinfo[snum][fnum].si_name != NULL) {
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if (pci_slotinfo[snum].si_funcs[fnum].fi_name != NULL) {
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fprintf(stderr, "pci slot %d:%d already occupied!\n",
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snum, fnum);
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goto done;
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@ -167,8 +179,8 @@ pci_parse_slot(char *opt)
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}
|
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error = 0;
|
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pci_slotinfo[snum][fnum].si_name = emul;
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pci_slotinfo[snum][fnum].si_param = config;
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pci_slotinfo[snum].si_funcs[fnum].fi_name = emul;
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pci_slotinfo[snum].si_funcs[fnum].fi_param = config;
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done:
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if (error)
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@ -666,7 +678,10 @@ pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func,
|
||||
pdi->pi_bus = 0;
|
||||
pdi->pi_slot = slot;
|
||||
pdi->pi_func = func;
|
||||
pdi->pi_lintr_pin = -1;
|
||||
pthread_mutex_init(&pdi->pi_lintr.lock, NULL);
|
||||
pdi->pi_lintr.pin = 0;
|
||||
pdi->pi_lintr.state = IDLE;
|
||||
pdi->pi_lintr.ioapic_irq = 0;
|
||||
pdi->pi_d = pde;
|
||||
snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot);
|
||||
|
||||
@ -682,7 +697,7 @@ pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int slot, int func,
|
||||
free(pdi);
|
||||
} else {
|
||||
pci_emul_devices++;
|
||||
pci_slotinfo[slot][func].si_devi = pdi;
|
||||
pci_slotinfo[slot].si_funcs[func].fi_devi = pdi;
|
||||
}
|
||||
|
||||
return (err);
|
||||
@ -816,6 +831,7 @@ msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
|
||||
|
||||
pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE;
|
||||
pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK;
|
||||
pci_lintr_update(pi);
|
||||
}
|
||||
|
||||
CFGWRITE(pi, offset, val, bytes);
|
||||
@ -854,6 +870,7 @@ msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
|
||||
} else {
|
||||
pi->pi_msi.maxmsgnum = 0;
|
||||
}
|
||||
pci_lintr_update(pi);
|
||||
}
|
||||
|
||||
CFGWRITE(pi, offset, val, bytes);
|
||||
@ -993,7 +1010,7 @@ int
|
||||
init_pci(struct vmctx *ctx)
|
||||
{
|
||||
struct pci_devemu *pde;
|
||||
struct slotinfo *si;
|
||||
struct funcinfo *fi;
|
||||
size_t lowmem;
|
||||
int slot, func;
|
||||
int error;
|
||||
@ -1004,12 +1021,12 @@ init_pci(struct vmctx *ctx)
|
||||
|
||||
for (slot = 0; slot < MAXSLOTS; slot++) {
|
||||
for (func = 0; func < MAXFUNCS; func++) {
|
||||
si = &pci_slotinfo[slot][func];
|
||||
if (si->si_name != NULL) {
|
||||
pde = pci_emul_finddev(si->si_name);
|
||||
fi = &pci_slotinfo[slot].si_funcs[func];
|
||||
if (fi->fi_name != NULL) {
|
||||
pde = pci_emul_finddev(fi->fi_name);
|
||||
assert(pde != NULL);
|
||||
error = pci_emul_init(ctx, pde, slot, func,
|
||||
si->si_param);
|
||||
fi->fi_param);
|
||||
if (error)
|
||||
return (error);
|
||||
}
|
||||
@ -1042,11 +1059,27 @@ init_pci(struct vmctx *ctx)
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_prt_entry(int slot, int pin, int ioapic_irq, void *arg)
|
||||
{
|
||||
int *count;
|
||||
|
||||
count = arg;
|
||||
dsdt_line(" Package (0x04)");
|
||||
dsdt_line(" {");
|
||||
dsdt_line(" 0x%X,", slot << 16 | 0xffff);
|
||||
dsdt_line(" 0x%02X,", pin - 1);
|
||||
dsdt_line(" Zero,");
|
||||
dsdt_line(" 0x%X", ioapic_irq);
|
||||
dsdt_line(" }%s", *count == 1 ? "" : ",");
|
||||
(*count)--;
|
||||
}
|
||||
|
||||
void
|
||||
pci_write_dsdt(void)
|
||||
{
|
||||
struct pci_devinst *pi;
|
||||
int slot, func;
|
||||
int count, slot, func;
|
||||
|
||||
dsdt_indent(1);
|
||||
dsdt_line("Scope (_SB)");
|
||||
@ -1107,11 +1140,20 @@ pci_write_dsdt(void)
|
||||
PCI_EMUL_MEMLIMIT64 - PCI_EMUL_MEMBASE64);
|
||||
dsdt_line(" ,, , AddressRangeMemory, TypeStatic)");
|
||||
dsdt_line(" })");
|
||||
count = pci_count_lintr();
|
||||
if (count != 0) {
|
||||
dsdt_indent(2);
|
||||
dsdt_line("Name (_PRT, Package (0x%02X)", count);
|
||||
dsdt_line("{");
|
||||
pci_walk_lintr(pci_prt_entry, &count);
|
||||
dsdt_line("})");
|
||||
dsdt_unindent(2);
|
||||
}
|
||||
|
||||
dsdt_indent(2);
|
||||
for (slot = 0; slot < MAXSLOTS; slot++) {
|
||||
for (func = 0; func < MAXFUNCS; func++) {
|
||||
pi = pci_slotinfo[slot][func].si_devi;
|
||||
pi = pci_slotinfo[slot].si_funcs[func].fi_devi;
|
||||
if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL)
|
||||
pi->pi_d->pe_write_dsdt(pi);
|
||||
}
|
||||
@ -1176,18 +1218,54 @@ pci_generate_msi(struct pci_devinst *pi, int index)
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
pci_lintr_request(struct pci_devinst *pi, int req)
|
||||
static bool
|
||||
pci_lintr_permitted(struct pci_devinst *pi)
|
||||
{
|
||||
int irq;
|
||||
uint16_t cmd;
|
||||
|
||||
irq = legacy_irq_alloc(req);
|
||||
if (irq < 0)
|
||||
return (-1);
|
||||
cmd = pci_get_cfgdata16(pi, PCIR_COMMAND);
|
||||
return (!(pi->pi_msi.enabled || pi->pi_msix.enabled ||
|
||||
(cmd & PCIM_CMD_INTxDIS)));
|
||||
}
|
||||
|
||||
pi->pi_lintr_pin = irq;
|
||||
int
|
||||
pci_lintr_request(struct pci_devinst *pi)
|
||||
{
|
||||
struct slotinfo *si;
|
||||
int bestpin, bestcount, irq, pin;
|
||||
|
||||
/*
|
||||
* First, allocate a pin from our slot.
|
||||
*/
|
||||
si = &pci_slotinfo[pi->pi_slot];
|
||||
bestpin = 0;
|
||||
bestcount = si->si_intpins[0].ii_count;
|
||||
for (pin = 1; pin < 4; pin++) {
|
||||
if (si->si_intpins[pin].ii_count < bestcount) {
|
||||
bestpin = pin;
|
||||
bestcount = si->si_intpins[pin].ii_count;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Attempt to allocate an I/O APIC pin for this intpin. If
|
||||
* 8259A support is added we will need a separate field to
|
||||
* assign the intpin to an input pin on the PCI interrupt
|
||||
* router.
|
||||
*/
|
||||
if (si->si_intpins[bestpin].ii_count == 0) {
|
||||
irq = ioapic_pci_alloc_irq();
|
||||
if (irq < 0)
|
||||
return (-1);
|
||||
si->si_intpins[bestpin].ii_ioapic_irq = irq;
|
||||
} else
|
||||
irq = si->si_intpins[bestpin].ii_ioapic_irq;
|
||||
si->si_intpins[bestpin].ii_count++;
|
||||
|
||||
pi->pi_lintr.pin = bestpin + 1;
|
||||
pi->pi_lintr.ioapic_irq = irq;
|
||||
pci_set_cfgdata8(pi, PCIR_INTLINE, irq);
|
||||
pci_set_cfgdata8(pi, PCIR_INTPIN, 1);
|
||||
pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -1195,23 +1273,77 @@ void
|
||||
pci_lintr_assert(struct pci_devinst *pi)
|
||||
{
|
||||
|
||||
assert(pi->pi_lintr_pin >= 0);
|
||||
assert(pi->pi_lintr.pin > 0);
|
||||
|
||||
if (pi->pi_lintr_state == 0) {
|
||||
pi->pi_lintr_state = 1;
|
||||
vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr_pin);
|
||||
pthread_mutex_lock(&pi->pi_lintr.lock);
|
||||
if (pi->pi_lintr.state == IDLE) {
|
||||
if (pci_lintr_permitted(pi)) {
|
||||
pi->pi_lintr.state = ASSERTED;
|
||||
vm_ioapic_assert_irq(pi->pi_vmctx,
|
||||
pi->pi_lintr.ioapic_irq);
|
||||
} else
|
||||
pi->pi_lintr.state = PENDING;
|
||||
}
|
||||
pthread_mutex_unlock(&pi->pi_lintr.lock);
|
||||
}
|
||||
|
||||
void
|
||||
pci_lintr_deassert(struct pci_devinst *pi)
|
||||
{
|
||||
|
||||
assert(pi->pi_lintr_pin >= 0);
|
||||
assert(pi->pi_lintr.pin > 0);
|
||||
|
||||
if (pi->pi_lintr_state == 1) {
|
||||
pi->pi_lintr_state = 0;
|
||||
vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr_pin);
|
||||
pthread_mutex_lock(&pi->pi_lintr.lock);
|
||||
if (pi->pi_lintr.state == ASSERTED) {
|
||||
pi->pi_lintr.state = IDLE;
|
||||
vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
|
||||
} else if (pi->pi_lintr.state == PENDING)
|
||||
pi->pi_lintr.state = IDLE;
|
||||
pthread_mutex_unlock(&pi->pi_lintr.lock);
|
||||
}
|
||||
|
||||
static void
|
||||
pci_lintr_update(struct pci_devinst *pi)
|
||||
{
|
||||
|
||||
pthread_mutex_lock(&pi->pi_lintr.lock);
|
||||
if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) {
|
||||
vm_ioapic_deassert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
|
||||
pi->pi_lintr.state = PENDING;
|
||||
} else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) {
|
||||
pi->pi_lintr.state = ASSERTED;
|
||||
vm_ioapic_assert_irq(pi->pi_vmctx, pi->pi_lintr.ioapic_irq);
|
||||
}
|
||||
pthread_mutex_unlock(&pi->pi_lintr.lock);
|
||||
}
|
||||
|
||||
int
|
||||
pci_count_lintr(void)
|
||||
{
|
||||
int count, slot, pin;
|
||||
|
||||
count = 0;
|
||||
for (slot = 0; slot < MAXSLOTS; slot++) {
|
||||
for (pin = 0; pin < 4; pin++) {
|
||||
if (pci_slotinfo[slot].si_intpins[pin].ii_count != 0)
|
||||
count++;
|
||||
}
|
||||
}
|
||||
return (count);
|
||||
}
|
||||
|
||||
void
|
||||
pci_walk_lintr(pci_lintr_cb cb, void *arg)
|
||||
{
|
||||
struct intxinfo *ii;
|
||||
int slot, pin;
|
||||
|
||||
for (slot = 0; slot < MAXSLOTS; slot++) {
|
||||
for (pin = 0; pin < 4; pin++) {
|
||||
ii = &pci_slotinfo[slot].si_intpins[pin];
|
||||
if (ii->ii_count != 0)
|
||||
cb(slot, pin + 1, ii->ii_ioapic_irq, arg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1226,7 +1358,7 @@ pci_emul_is_mfdev(int slot)
|
||||
|
||||
numfuncs = 0;
|
||||
for (f = 0; f < MAXFUNCS; f++) {
|
||||
if (pci_slotinfo[slot][f].si_devi != NULL) {
|
||||
if (pci_slotinfo[slot].si_funcs[f].fi_devi != NULL) {
|
||||
numfuncs++;
|
||||
}
|
||||
}
|
||||
@ -1348,6 +1480,12 @@ pci_emul_cmdwrite(struct pci_devinst *pi, uint32_t new, int bytes)
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* If INTx has been unmasked and is pending, assert the
|
||||
* interrupt.
|
||||
*/
|
||||
pci_lintr_update(pi);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -1362,7 +1500,7 @@ pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
|
||||
assert(bytes == 1 || bytes == 2 || bytes == 4);
|
||||
|
||||
if (cfgbus == 0)
|
||||
pi = pci_slotinfo[cfgslot][cfgfunc].si_devi;
|
||||
pi = pci_slotinfo[cfgslot].si_funcs[cfgfunc].fi_devi;
|
||||
else
|
||||
pi = NULL;
|
||||
|
||||
|
||||
@ -32,6 +32,7 @@
|
||||
#include <sys/types.h>
|
||||
#include <sys/queue.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/_pthreadtypes.h>
|
||||
|
||||
#include <dev/pci/pcireg.h>
|
||||
|
||||
@ -102,15 +103,26 @@ struct msix_table_entry {
|
||||
#define MAX_MSIX_TABLE_ENTRIES 2048
|
||||
#define PBA_TABLE_ENTRY_SIZE 8
|
||||
|
||||
enum lintr_stat {
|
||||
IDLE,
|
||||
ASSERTED,
|
||||
PENDING
|
||||
};
|
||||
|
||||
struct pci_devinst {
|
||||
struct pci_devemu *pi_d;
|
||||
struct vmctx *pi_vmctx;
|
||||
uint8_t pi_bus, pi_slot, pi_func;
|
||||
int8_t pi_lintr_pin;
|
||||
int8_t pi_lintr_state;
|
||||
char pi_name[PI_NAMESZ];
|
||||
int pi_bar_getsize;
|
||||
|
||||
struct {
|
||||
int8_t pin;
|
||||
enum lintr_stat state;
|
||||
int ioapic_irq;
|
||||
pthread_mutex_t lock;
|
||||
} pi_lintr;
|
||||
|
||||
struct {
|
||||
int enabled;
|
||||
uint64_t addr;
|
||||
@ -187,6 +199,8 @@ struct pciecap {
|
||||
uint16_t slot_status2;
|
||||
} __packed;
|
||||
|
||||
typedef void (*pci_lintr_cb)(int slot, int pin, int ioapic_irq, void *arg);
|
||||
|
||||
int init_pci(struct vmctx *ctx);
|
||||
void msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset,
|
||||
int bytes, uint32_t val);
|
||||
@ -203,7 +217,7 @@ void pci_generate_msi(struct pci_devinst *pi, int msgnum);
|
||||
void pci_generate_msix(struct pci_devinst *pi, int msgnum);
|
||||
void pci_lintr_assert(struct pci_devinst *pi);
|
||||
void pci_lintr_deassert(struct pci_devinst *pi);
|
||||
int pci_lintr_request(struct pci_devinst *pi, int ivec);
|
||||
int pci_lintr_request(struct pci_devinst *pi);
|
||||
int pci_msi_enabled(struct pci_devinst *pi);
|
||||
int pci_msix_enabled(struct pci_devinst *pi);
|
||||
int pci_msix_table_bar(struct pci_devinst *pi);
|
||||
@ -215,6 +229,8 @@ int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
|
||||
int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
|
||||
uint64_t value);
|
||||
uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
|
||||
int pci_count_lintr(void);
|
||||
void pci_walk_lintr(pci_lintr_cb cb, void *arg);
|
||||
void pci_write_dsdt(void);
|
||||
|
||||
static __inline void
|
||||
|
||||
@ -91,7 +91,7 @@ pci_uart_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
struct uart_softc *sc;
|
||||
|
||||
pci_emul_alloc_bar(pi, 0, PCIBAR_IO, UART_IO_BAR_SIZE);
|
||||
pci_lintr_request(pi, -1);
|
||||
pci_lintr_request(pi);
|
||||
|
||||
/* initialize config space */
|
||||
pci_set_cfgdata16(pi, PCIR_DEVICE, COM_DEV);
|
||||
|
||||
@ -117,6 +117,7 @@ static int pci_vtblk_debug;
|
||||
*/
|
||||
struct pci_vtblk_softc {
|
||||
struct virtio_softc vbsc_vs;
|
||||
pthread_mutex_t vsc_mtx;
|
||||
struct vqueue_info vbsc_vq;
|
||||
int vbsc_fd;
|
||||
struct vtblk_config vbsc_cfg;
|
||||
@ -304,8 +305,12 @@ pci_vtblk_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
/* record fd of storage device/file */
|
||||
sc->vbsc_fd = fd;
|
||||
|
||||
pthread_mutex_init(&sc->vsc_mtx, NULL);
|
||||
|
||||
/* init virtio softc and virtqueues */
|
||||
vi_softc_linkup(&sc->vbsc_vs, &vtblk_vi_consts, sc, pi, &sc->vbsc_vq);
|
||||
sc->vbsc_vs.vs_mtx = &sc->vsc_mtx;
|
||||
|
||||
sc->vbsc_vq.vq_qsize = VTBLK_RINGSZ;
|
||||
/* sc->vbsc_vq.vq_notify = we have no per-queue notify */
|
||||
|
||||
@ -339,6 +344,8 @@ pci_vtblk_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
|
||||
pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_TYPE_BLOCK);
|
||||
|
||||
pci_lintr_request(pi);
|
||||
|
||||
if (vi_intr_init(&sc->vbsc_vs, 1, fbsdrun_virtio_msix()))
|
||||
return (1);
|
||||
vi_set_io_bar(&sc->vbsc_vs, 0);
|
||||
|
||||
@ -519,6 +519,8 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
pthread_mutex_init(&sc->vsc_mtx, NULL);
|
||||
|
||||
vi_softc_linkup(&sc->vsc_vs, &vtnet_vi_consts, sc, pi, sc->vsc_queues);
|
||||
sc->vsc_vs.vs_mtx = &sc->vsc_mtx;
|
||||
|
||||
sc->vsc_queues[VTNET_RXQ].vq_qsize = VTNET_RINGSZ;
|
||||
sc->vsc_queues[VTNET_RXQ].vq_notify = pci_vtnet_ping_rxq;
|
||||
sc->vsc_queues[VTNET_TXQ].vq_qsize = VTNET_RINGSZ;
|
||||
@ -608,6 +610,8 @@ pci_vtnet_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
|
||||
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_NETWORK);
|
||||
pci_set_cfgdata16(pi, PCIR_SUBDEV_0, VIRTIO_TYPE_NET);
|
||||
|
||||
pci_lintr_request(pi);
|
||||
|
||||
/* link always up */
|
||||
sc->vsc_config.status = 1;
|
||||
|
||||
|
||||
@ -99,7 +99,11 @@ vi_reset_dev(struct virtio_softc *vs)
|
||||
vs->vs_negotiated_caps = 0;
|
||||
vs->vs_curq = 0;
|
||||
/* vs->vs_status = 0; -- redundant */
|
||||
VS_LOCK(vs);
|
||||
if (vs->vs_isr)
|
||||
pci_lintr_deassert(vs->vs_pi);
|
||||
vs->vs_isr = 0;
|
||||
VS_UNLOCK(vs);
|
||||
vs->vs_msix_cfg_idx = VIRTIO_MSI_NO_VECTOR;
|
||||
}
|
||||
|
||||
@ -137,11 +141,10 @@ vi_intr_init(struct virtio_softc *vs, int barnum, int use_msix)
|
||||
nvec = vs->vs_vc->vc_nvq + 1;
|
||||
if (pci_emul_add_msixcap(vs->vs_pi, nvec, barnum))
|
||||
return (1);
|
||||
} else {
|
||||
} else
|
||||
vs->vs_flags &= ~VIRTIO_USE_MSIX;
|
||||
/* Only 1 MSI vector for bhyve */
|
||||
pci_emul_add_msicap(vs->vs_pi, 1);
|
||||
}
|
||||
/* Only 1 MSI vector for bhyve */
|
||||
pci_emul_add_msicap(vs->vs_pi, 1);
|
||||
return (0);
|
||||
}
|
||||
|
||||
@ -591,6 +594,8 @@ vi_pci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
|
||||
case VTCFG_R_ISR:
|
||||
value = vs->vs_isr;
|
||||
vs->vs_isr = 0; /* a read clears this flag */
|
||||
if (value)
|
||||
pci_lintr_deassert(pi);
|
||||
break;
|
||||
case VTCFG_R_CFGVEC:
|
||||
value = vs->vs_msix_cfg_idx;
|
||||
|
||||
@ -328,6 +328,18 @@ struct virtio_softc {
|
||||
uint16_t vs_msix_cfg_idx; /* MSI-X vector for config event */
|
||||
};
|
||||
|
||||
#define VS_LOCK(vs) \
|
||||
do { \
|
||||
if (vs->vs_mtx) \
|
||||
pthread_mutex_lock(vs->vs_mtx); \
|
||||
} while (0)
|
||||
|
||||
#define VS_UNLOCK(vs) \
|
||||
do { \
|
||||
if (vs->vs_mtx) \
|
||||
pthread_mutex_unlock(vs->vs_mtx); \
|
||||
} while (0)
|
||||
|
||||
struct virtio_consts {
|
||||
const char *vc_name; /* name of driver (for diagnostics) */
|
||||
int vc_nvq; /* number of virtual queues */
|
||||
@ -431,11 +443,14 @@ static inline void
|
||||
vq_interrupt(struct virtio_softc *vs, struct vqueue_info *vq)
|
||||
{
|
||||
|
||||
if (vs->vs_flags & VIRTIO_USE_MSIX)
|
||||
if (pci_msix_enabled(vs->vs_pi))
|
||||
pci_generate_msix(vs->vs_pi, vq->vq_msix_idx);
|
||||
else {
|
||||
VS_LOCK(vs);
|
||||
vs->vs_isr |= VTCFG_ISR_QUEUES;
|
||||
pci_generate_msi(vs->vs_pi, 0);
|
||||
pci_lintr_assert(vs->vs_pi);
|
||||
VS_UNLOCK(vs);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user