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Add mechanism to track TSB misses in tsb miss handler
Remove unused debug code
This commit is contained in:
Kip Macy
parent
7c3d7aad2e
commit
3cf970e7bc
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=164485
@ -233,6 +233,8 @@ ASSYM(PC_TSBWBUF, offsetof(struct pcpu, pc_tsbwbuf));
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ASSYM(PCB_KSTACK, offsetof(struct pcb, pcb_kstack));
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ASSYM(INTR_REPORT_SIZE, INTR_REPORT_SIZE);
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ASSYM(PM_TSB_MISS_COUNT, offsetof(struct pmap, pm_tsb_miss_count));
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ASSYM(PM_TSB_CAP_MISS_COUNT, offsetof(struct pmap, pm_tsb_cap_miss_count));
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#else
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ASSYM(PC_MID, offsetof(struct pcpu, pc_mid));
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ASSYM(PC_TLB_CTX, offsetof(struct pcpu, pc_tlb_ctx));
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@ -73,6 +73,8 @@ struct pmap {
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pmap_cpumask_t pm_active; /* mask of cpus currently using pmap */
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pmap_cpumask_t pm_tlbactive; /* mask of cpus that have used this pmap */
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struct pmap_statistics pm_stats;
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uint32_t pm_tsb_miss_count;
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uint32_t pm_tsb_cap_miss_count;
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};
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#define PMAP_LOCK(pmap) mtx_lock(&(pmap)->pm_mtx)
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@ -63,10 +63,14 @@ __FBSDID("$FreeBSD$")
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#define PCB_REG %g6
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#define PUTCHAR(x) \
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0: ; \
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mov x, %o0 ; \
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mov CONS_WRITE, %o5 ; \
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ta FAST_TRAP
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/*
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ta FAST_TRAP ; \
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brnz %o0, 0b ; \
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nop
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/*
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* Atomically set the reference bit in a tte.
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*/
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#define TTE_SET_BIT(r1, r2, r3, bit) \
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@ -1410,7 +1414,7 @@ ENTRY(tl0_trap)
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nop
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ENTRY(tl0_utrap)
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GET_PCPU_SCRATCH
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cmp %g2, UT_MAX
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bge,a,pn %xcc, skip_utrap
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nop
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@ -1543,7 +1547,7 @@ END(tl0_intr)
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#define ENTER #Sync
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#define EXIT #Sync
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#endif
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#define THE_LOCK_ENTER(addr, lock_bit, oldval, newval, label1) \
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mov 1, lock_bit ; \
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add addr, 8, addr ; \
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@ -1789,7 +1793,7 @@ tsb_miss_found:
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cmp %g3, TT_DATA_MISS ! TSB data miss
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be,pt %xcc, 9f
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or %l7, VTD_REF, %l7 ! set referenced unconditionally
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cmp %g3, TT_INSTRUCTION_MISS ! TSB instruction miss
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cmp %g3, TT_INSTRUCTION_MISS ! TSB instruction miss
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be,pt %xcc, 9f
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nop
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cmp %g3, TT_DATA_PROTECTION ! protection fault
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@ -1805,44 +1809,48 @@ tsb_miss_found:
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and %g4, %l1, %g3 ! size of TSB in pages
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andn %g4, %l1, %l3 ! TSB real address
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sllx %g3, (PAGE_SHIFT - TTE_SHIFT), %g3 ! nttes
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#ifdef notyet
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mov 1, %l2
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add %g3, (PAGE_SHIFT - TTE_SHIFT), %g3 ! add shift value for number of ttes / page
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sllx %l2, %g3, %g3 ! nttes
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#else
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sllx %g3, (PAGE_SHIFT - TTE_SHIFT), %g3
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#endif
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subx %g3, 1, %g3 ! TSB_MASK
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and %g3, %l4, %g3 ! masked index
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sllx %g3, TTE_SHIFT, %g3 ! masked byte offset
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add %g3, %l3, %g3 ! TTE RA
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#if 0
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#ifdef PMAP_DEBUG
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ldxa [%g3]%asi, %l2
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ldxa [%g3 + 8]%asi, %l3
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cmp %l3, %l7
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bne,pt %xcc, 12f
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cmp %l2, %l6
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bne,pt %xcc, 12f
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rdpr %tl, %l2 ! don't track misses for kernel context
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brz,pn %g6, 13f
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dec %l2
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brnz,pn %l2, 13f ! don't track misses at tl > 1
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nop
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#ifndef SMP
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! MAGIC_TRAP_ON;MAGIC_TRAP_ON;MAGIC_EXIT ! die if all we're doing
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! is storing same data
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#else
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mov %o0, %l2
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mov %o5, %g4
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PUTCHAR(0x5a)
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lda [PCPU_REG + PC_CPUID]%asi, %o0
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add %o0, 0x30, %o0
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PUTCHAR(%o0)
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PUTCHAR(0x5a)
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mov %l2, %o0
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mov %g4, %o5
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! MAGIC_TRAP_ON; MAGIC_TRAP_OFF
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#endif
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12:
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#endif
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#endif
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stxa %g0, [%g3 + 8]%asi ! invalidate data
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#ifndef WORKING
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membar #Sync
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#endif
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ldx [PCPU(PMAP)], %l1
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ld [%l1 + PM_TSB_MISS_COUNT], %l3
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add 1, %l3, %l3
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st %l3, [%l1 + PM_TSB_MISS_COUNT]
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! if the data value is zero then this is not a capacity miss
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ldda [%g3]ASI_LDTD_N, %l2
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brz,pt %l3, 13f
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nop
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! compare the tag bits - if they're the same we're merely
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! changing the mapping
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brz,pt %l3, 13f
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nop
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cmp %l6, %l2
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beq,pt %xcc, 13f
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nop
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ld [%l1 + PM_TSB_CAP_MISS_COUNT], %l3
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add 1, %l3, %l3
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st %l3, [%l1 + PM_TSB_CAP_MISS_COUNT]
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13: stxa %g0, [%g3 + 8]%asi ! invalidate data
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membar #StoreStore
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stxa %l6, [%g3]%asi ! store tag
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stxa %l7, [%g3 + 8]%asi ! store data
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stxa %l7, [%g2 + 8]%asi ! update TTE with ref bit
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@ -1897,10 +1905,10 @@ END(prot_fault_trap)
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* Programming error
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*/
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ENTRY(unsupported_fault_trap)
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add 0x20, %g3, %g1
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PUTCHAR(0x5b)
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PUTCHAR(0x5b)
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PUTCHAR(0x5b)
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! MAGIC_TRAP_ON;MAGIC_TRAP_ON;MAGIC_EXIT
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PUTCHAR(%g1)
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PUTCHAR(0x5d)
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END(unsupported_fault_trap)
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@ -1938,7 +1946,7 @@ ENTRY(tl1_trap)
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wr %g0, ASI_REAL, %asi
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TTRACE_ADD_SAFE(%g6, 0, 0, 0, 0, 0)
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#endif
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! assume no tl1 handler
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! assume no tl1 handler
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rdpr %tpc, %g7
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set rtt_fill_start, %g6
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