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https://git.FreeBSD.org/src.git
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Transition to using bus_space macros rather than the inb/outb/etc.
Use EP_{READ,WRITE}{,_MULTI}_{1,2,4} instead. I've had several people submit patches like this over the years of varying qualities, markm being the last. The names were chosen in consulation with mdodd on irc. I've tested this with only PCMCIA cards: 3CCE589EC and 3CCSH572BT. I've not tried with my more extensive ISA, EISA and cbus collection. Reviewed by: mdodd
This commit is contained in:
parent
2c18019f14
commit
3dc59524c7
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=121206
@ -112,7 +112,7 @@ eeprom_rdy(struct ep_softc *sc)
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{
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int i;
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for (i = 0; is_eeprom_busy(BASE) && i < MAX_EEPROMBUSY; i++)
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for (i = 0; is_eeprom_busy(sc) && i < MAX_EEPROMBUSY; i++)
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DELAY(100);
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if (i >= MAX_EEPROMBUSY) {
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@ -134,13 +134,13 @@ get_e(struct ep_softc *sc, u_int16_t offset, u_int16_t *result)
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if (eeprom_rdy(sc))
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return (ENXIO);
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outw(BASE + EP_W0_EEPROM_COMMAND,
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EP_WRITE_2(sc, EP_W0_EEPROM_COMMAND,
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(EEPROM_CMD_RD << sc->epb.cmd_off) | offset);
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if (eeprom_rdy(sc))
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return (ENXIO);
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(*result) = inw(BASE + EP_W0_EEPROM_DATA);
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(*result) = EP_READ_2(sc, EP_W0_EEPROM_DATA);
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return (0);
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}
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@ -194,10 +194,8 @@ ep_alloc(device_t dev)
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sc->unit = device_get_unit(dev);
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sc->stat = 0; /* 16 bit access */
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sc->ep_io_addr = rman_get_start(sc->iobase);
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sc->ep_btag = rman_get_bustag(sc->iobase);
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sc->ep_bhandle = rman_get_bushandle(sc->iobase);
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sc->bst = rman_get_bustag(sc->iobase);
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sc->bsh = rman_get_bushandle(sc->iobase);
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sc->ep_connectors = 0;
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sc->ep_connector = 0;
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@ -225,7 +223,7 @@ ep_get_media(struct ep_softc *sc)
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u_int16_t config;
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GO_WINDOW(0);
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config = inw(BASE + EP_W0_CONFIG_CTRL);
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config = EP_READ_2(sc, EP_W0_CONFIG_CTRL);
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if (config & IS_AUI)
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sc->ep_connectors |= AUI;
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if (config & IS_BNC)
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@ -242,7 +240,7 @@ ep_get_media(struct ep_softc *sc)
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* The cards that require something different can override
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* this later on.
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*/
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sc->ep_connector = inw(BASE + EP_W0_ADDRESS_CFG) >> ACF_CONNECTOR_BITS;
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sc->ep_connector = EP_READ_2(sc, EP_W0_ADDRESS_CFG) >> ACF_CONNECTOR_BITS;
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}
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void
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@ -281,7 +279,7 @@ ep_attach(struct ep_softc *sc)
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p = (u_short *)&sc->arpcom.ac_enaddr;
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GO_WINDOW(2);
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for (i = 0; i < 3; i++)
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outw(BASE + EP_W2_ADDR_0 + (i * 2), ntohs(p[i]));
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EP_WRITE_2(sc, EP_W2_ADDR_0 + (i * 2), ntohs(p[i]));
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device_printf(sc->dev, "Ethernet address %6D\n",
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sc->arpcom.ac_enaddr, ":");
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@ -379,54 +377,54 @@ ep_if_init(void *xsc)
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return;
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s = splimp();
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while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
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while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
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GO_WINDOW(0);
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outw(BASE + EP_COMMAND, STOP_TRANSCEIVER);
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EP_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
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GO_WINDOW(4);
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outw(BASE + EP_W4_MEDIA_TYPE, DISABLE_UTP);
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EP_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
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GO_WINDOW(0);
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/* Disable the card */
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outw(BASE + EP_W0_CONFIG_CTRL, 0);
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EP_WRITE_2(sc, EP_W0_CONFIG_CTRL, 0);
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/* Enable the card */
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outw(BASE + EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
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EP_WRITE_2(sc, EP_W0_CONFIG_CTRL, ENABLE_DRQ_IRQ);
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GO_WINDOW(2);
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/* Reload the ether_addr. */
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for (i = 0; i < 6; i++)
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outb(BASE + EP_W2_ADDR_0 + i, sc->arpcom.ac_enaddr[i]);
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EP_WRITE_1(sc, EP_W2_ADDR_0 + i, sc->arpcom.ac_enaddr[i]);
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outw(BASE + EP_COMMAND, RX_RESET);
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outw(BASE + EP_COMMAND, TX_RESET);
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while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
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EP_WRITE_2(sc, EP_COMMAND, RX_RESET);
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EP_WRITE_2(sc, EP_COMMAND, TX_RESET);
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while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
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/* Window 1 is operating window */
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GO_WINDOW(1);
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for (i = 0; i < 31; i++)
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inb(BASE + EP_W1_TX_STATUS);
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EP_READ_1(sc, EP_W1_TX_STATUS);
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/* get rid of stray intr's */
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outw(BASE + EP_COMMAND, ACK_INTR | 0xff);
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EP_WRITE_2(sc, EP_COMMAND, ACK_INTR | 0xff);
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outw(BASE + EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
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EP_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK | S_5_INTS);
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outw(BASE + EP_COMMAND, SET_INTR_MASK | S_5_INTS);
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EP_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
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if (ifp->if_flags & IFF_PROMISC)
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outw(BASE + EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
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EP_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
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FIL_GROUP | FIL_BRDCST | FIL_ALL);
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else
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outw(BASE + EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
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EP_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER | FIL_INDIVIDUAL |
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FIL_GROUP | FIL_BRDCST);
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if (!sc->epb.mii_trans)
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ep_ifmedia_upd(ifp);
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outw(BASE + EP_COMMAND, RX_ENABLE);
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outw(BASE + EP_COMMAND, TX_ENABLE);
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EP_WRITE_2(sc, EP_COMMAND, RX_ENABLE);
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EP_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE; /* just in case */
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@ -440,8 +438,8 @@ ep_if_init(void *xsc)
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m_freem(sc->top);
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sc->top = sc->mcur = 0;
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}
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outw(BASE + EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
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outw(BASE + EP_COMMAND, SET_TX_START_THRESH | 16);
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EP_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
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EP_WRITE_2(sc, EP_COMMAND, SET_TX_START_THRESH | 16);
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/*
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* Store up a bunch of mbuf's for use later. (MAX_MBS).
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@ -467,7 +465,7 @@ ep_if_start(struct ifnet *ifp)
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if (sc->gone)
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return;
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while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
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while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
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if (ifp->if_flags & IFF_OACTIVE)
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return;
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@ -492,48 +490,48 @@ ep_if_start(struct ifnet *ifp)
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m_freem(m0);
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goto readcheck;
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}
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if (inw(BASE + EP_W1_FREE_TX) < len + pad + 4) {
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if (EP_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) {
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/* no room in FIFO */
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outw(BASE + EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
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EP_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | (len + pad + 4));
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/* make sure */
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if (inw(BASE + EP_W1_FREE_TX) < len + pad + 4) {
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if (EP_READ_2(sc, EP_W1_FREE_TX) < len + pad + 4) {
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ifp->if_flags |= IFF_OACTIVE;
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IF_PREPEND(&ifp->if_snd, m0);
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return;
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}
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} else
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outw(BASE + EP_COMMAND,
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EP_WRITE_2(sc, EP_COMMAND,
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SET_TX_AVAIL_THRESH | EP_THRESH_DISABLE);
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s = splhigh();
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outw(BASE + EP_W1_TX_PIO_WR_1, len);
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EP_WRITE_2(sc, EP_W1_TX_PIO_WR_1, len);
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/* Second dword meaningless */
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outw(BASE + EP_W1_TX_PIO_WR_1, 0x0);
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EP_WRITE_2(sc, EP_W1_TX_PIO_WR_1, 0x0);
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if (EP_FTST(sc, F_ACCESS_32_BITS)) {
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for (m = m0; m != NULL; m = m->m_next) {
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if (m->m_len > 3)
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outsl(BASE + EP_W1_TX_PIO_WR_1,
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mtod(m, caddr_t), m->m_len / 4);
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EP_WRITE_MULTI_4(sc, EP_W1_TX_PIO_WR_1,
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mtod(m, uint32_t *), m->m_len / 4);
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if (m->m_len & 3)
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outsb(BASE + EP_W1_TX_PIO_WR_1,
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mtod(m, caddr_t)+(m->m_len & (~3)),
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EP_WRITE_MULTI_1(sc, EP_W1_TX_PIO_WR_1,
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mtod(m, uint8_t *)+(m->m_len & (~3)),
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m->m_len & 3);
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}
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} else {
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for (m = m0; m != NULL; m = m->m_next) {
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if (m->m_len > 1)
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outsw(BASE + EP_W1_TX_PIO_WR_1,
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mtod(m, caddr_t), m->m_len / 2);
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EP_WRITE_MULTI_2(sc, EP_W1_TX_PIO_WR_1,
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mtod(m, uint16_t *), m->m_len / 2);
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if (m->m_len & 1)
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outb(BASE + EP_W1_TX_PIO_WR_1,
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*(mtod(m, caddr_t)+m->m_len - 1));
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EP_WRITE_1(sc, EP_W1_TX_PIO_WR_1,
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*(mtod(m, uint8_t *)+m->m_len - 1));
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}
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}
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while (pad--)
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outb(BASE + EP_W1_TX_PIO_WR_1, 0); /* Padding */
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EP_WRITE_1(sc, EP_W1_TX_PIO_WR_1, 0); /* Padding */
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splx(s);
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@ -548,13 +546,13 @@ ep_if_start(struct ifnet *ifp)
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* the tiny RX fifo.
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*/
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readcheck:
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if (inw(BASE + EP_W1_RX_STATUS) & RX_BYTES_MASK) {
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if (EP_READ_2(sc, EP_W1_RX_STATUS) & RX_BYTES_MASK) {
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/*
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* we check if we have packets left, in that case
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* we prepare to come back later
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*/
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if (ifp->if_snd.ifq_head)
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outw(BASE + EP_COMMAND, SET_TX_AVAIL_THRESH | 8);
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EP_WRITE_2(sc, EP_COMMAND, SET_TX_AVAIL_THRESH | 8);
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return;
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}
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goto startagain;
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@ -575,20 +573,20 @@ ep_intr(void *arg)
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/*
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* quick fix: Try to detect an interrupt when the card goes away.
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*/
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if (sc->gone || inw(BASE + EP_STATUS) == 0xffff) {
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if (sc->gone || EP_READ_2(sc, EP_STATUS) == 0xffff) {
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splx(x);
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return;
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}
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ifp = &sc->arpcom.ac_if;
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outw(BASE + EP_COMMAND, SET_INTR_MASK); /* disable all Ints */
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EP_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK); /* disable all Ints */
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rescan:
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while ((status = inw(BASE + EP_STATUS)) & S_5_INTS) {
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while ((status = EP_READ_2(sc, EP_STATUS)) & S_5_INTS) {
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/* first acknowledge all interrupt sources */
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outw(BASE + EP_COMMAND, ACK_INTR | (status & S_MASK));
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EP_WRITE_2(sc, EP_COMMAND, ACK_INTR | (status & S_MASK));
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if (status & (S_RX_COMPLETE | S_RX_EARLY))
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epread(sc);
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@ -597,7 +595,7 @@ ep_intr(void *arg)
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ifp->if_timer = 0;
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ifp->if_flags &= ~IFF_OACTIVE;
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GO_WINDOW(1);
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inw(BASE + EP_W1_FREE_TX);
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EP_READ_2(sc, EP_W1_FREE_TX);
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ep_if_start(ifp);
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}
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if (status & S_CARD_FAILURE) {
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@ -606,7 +604,7 @@ ep_intr(void *arg)
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printf("\nep%d:\n\tStatus: %x\n", sc->unit, status);
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GO_WINDOW(4);
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printf("\tFIFO Diagnostic: %x\n",
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inw(BASE + EP_W4_FIFO_DIAG));
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EP_READ_2(sc, EP_W4_FIFO_DIAG));
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printf("\tStat: %x\n", sc->stat);
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printf("\tIpackets=%d, Opackets=%d\n",
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ifp->if_ipackets, ifp->if_opackets);
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@ -635,13 +633,13 @@ ep_intr(void *arg)
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* We need to read TX_STATUS until we get a
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* 0 status in order to turn off the interrupt flag.
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*/
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while ((status = inb(BASE + EP_W1_TX_STATUS)) &
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while ((status = EP_READ_1(sc, EP_W1_TX_STATUS)) &
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TXS_COMPLETE) {
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if (status & TXS_SUCCES_INTR_REQ);
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else if (status &
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(TXS_UNDERRUN | TXS_JABBER |
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TXS_MAX_COLLISION)) {
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outw(BASE + EP_COMMAND, TX_RESET);
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EP_WRITE_2(sc, EP_COMMAND, TX_RESET);
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if (status & TXS_UNDERRUN) {
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#ifdef EP_LOCAL_STATS
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sc->tx_underrun++;
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@ -656,32 +654,32 @@ ep_intr(void *arg)
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*/
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}
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++ifp->if_oerrors;
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outw(BASE + EP_COMMAND, TX_ENABLE);
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EP_WRITE_2(sc, EP_COMMAND, TX_ENABLE);
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/*
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* To have a tx_avail_int but giving
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* the chance to the Reception
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*/
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if (ifp->if_snd.ifq_head)
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outw(BASE + EP_COMMAND,
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EP_WRITE_2(sc, EP_COMMAND,
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SET_TX_AVAIL_THRESH | 8);
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}
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/* pops up the next status */
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outb(BASE + EP_W1_TX_STATUS, 0x0);
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EP_WRITE_1(sc, EP_W1_TX_STATUS, 0x0);
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} /* while */
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ifp->if_flags &= ~IFF_OACTIVE;
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GO_WINDOW(1);
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inw(BASE + EP_W1_FREE_TX);
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EP_READ_2(sc, EP_W1_FREE_TX);
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ep_if_start(ifp);
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} /* end TX_COMPLETE */
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}
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outw(BASE + EP_COMMAND, C_INTR_LATCH); /* ACK int Latch */
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EP_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH); /* ACK int Latch */
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if ((status = inw(BASE + EP_STATUS)) & S_5_INTS)
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if ((status = EP_READ_2(sc, EP_STATUS)) & S_5_INTS)
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goto rescan;
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/* re-enable Ints */
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outw(BASE + EP_COMMAND, SET_INTR_MASK | S_5_INTS);
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EP_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK | S_5_INTS);
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splx(x);
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}
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@ -697,7 +695,7 @@ epread(struct ep_softc *sc)
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short rx_fifo;
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ifp = &sc->arpcom.ac_if;
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status = inw(BASE + EP_W1_RX_STATUS);
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status = EP_READ_2(sc, EP_W1_RX_STATUS);
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read_again:
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@ -731,8 +729,8 @@ epread(struct ep_softc *sc)
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top->m_data += EOFF;
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/* Read what should be the header. */
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insw(BASE + EP_W1_RX_PIO_RD_1,
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mtod(top, caddr_t), sizeof(struct ether_header) / 2);
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EP_READ_MULTI_2(sc, EP_W1_RX_PIO_RD_1,
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mtod(top, uint16_t *), sizeof(struct ether_header) / 2);
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top->m_len = sizeof(struct ether_header);
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rx_fifo -= sizeof(struct ether_header);
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sc->cur_len = rx_fifo2;
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@ -759,21 +757,21 @@ epread(struct ep_softc *sc)
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}
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if (EP_FTST(sc, F_ACCESS_32_BITS)) {
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/* default for EISA configured cards */
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insl(BASE + EP_W1_RX_PIO_RD_1,
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mtod(m, caddr_t)+m->m_len,
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EP_READ_MULTI_4(sc, EP_W1_RX_PIO_RD_1,
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mtod(m, uint32_t *)+m->m_len,
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lenthisone / 4);
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m->m_len += (lenthisone & ~3);
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if (lenthisone & 3)
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insb(BASE + EP_W1_RX_PIO_RD_1,
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EP_READ_MULTI_1(sc, EP_W1_RX_PIO_RD_1,
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mtod(m, caddr_t)+m->m_len, lenthisone & 3);
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m->m_len += (lenthisone & 3);
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} else {
|
||||
insw(BASE + EP_W1_RX_PIO_RD_1,
|
||||
mtod(m, caddr_t)+m->m_len, lenthisone / 2);
|
||||
EP_READ_MULTI_2(sc, EP_W1_RX_PIO_RD_1,
|
||||
mtod(m, uint16_t *)+m->m_len, lenthisone / 2);
|
||||
m->m_len += lenthisone;
|
||||
if (lenthisone & 1)
|
||||
*(mtod(m, caddr_t)+m->m_len - 1) =
|
||||
inb(BASE + EP_W1_RX_PIO_RD_1);
|
||||
EP_READ_1(sc, EP_W1_RX_PIO_RD_1);
|
||||
}
|
||||
rx_fifo -= lenthisone;
|
||||
}
|
||||
@ -786,7 +784,7 @@ epread(struct ep_softc *sc)
|
||||
sc->rx_no_first++;
|
||||
#endif
|
||||
EP_FRST(sc, F_RX_FIRST);
|
||||
status = inw(BASE + EP_W1_RX_STATUS);
|
||||
status = EP_READ_2(sc, EP_W1_RX_STATUS);
|
||||
if (!status & ERR_RX_INCOMPLETE) {
|
||||
/*
|
||||
* We see if by now, the packet has completly
|
||||
@ -794,11 +792,11 @@ epread(struct ep_softc *sc)
|
||||
*/
|
||||
goto read_again;
|
||||
}
|
||||
outw(BASE + EP_COMMAND,
|
||||
EP_WRITE_2(sc, EP_COMMAND,
|
||||
SET_RX_EARLY_THRESH | RX_NEXT_EARLY_THRESH);
|
||||
return;
|
||||
}
|
||||
outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
|
||||
EP_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
|
||||
++ifp->if_ipackets;
|
||||
EP_FSET(sc, F_RX_FIRST);
|
||||
top->m_pkthdr.rcvif = &sc->arpcom.ac_if;
|
||||
@ -806,12 +804,12 @@ epread(struct ep_softc *sc)
|
||||
|
||||
(*ifp->if_input) (ifp, top);
|
||||
sc->top = 0;
|
||||
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
outw(BASE + EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
|
||||
while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
EP_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
|
||||
return;
|
||||
|
||||
out:
|
||||
outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
|
||||
EP_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
|
||||
if (sc->top) {
|
||||
m_freem(sc->top);
|
||||
sc->top = 0;
|
||||
@ -820,8 +818,8 @@ epread(struct ep_softc *sc)
|
||||
#endif
|
||||
}
|
||||
EP_FSET(sc, F_RX_FIRST);
|
||||
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
outw(BASE + EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
|
||||
while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
EP_WRITE_2(sc, EP_COMMAND, SET_RX_EARLY_THRESH | RX_INIT_EARLY_THRESH);
|
||||
}
|
||||
|
||||
static int
|
||||
@ -831,9 +829,9 @@ ep_ifmedia_upd(struct ifnet *ifp)
|
||||
int i = 0, j;
|
||||
|
||||
GO_WINDOW(0);
|
||||
outw(BASE + EP_COMMAND, STOP_TRANSCEIVER);
|
||||
EP_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
|
||||
GO_WINDOW(4);
|
||||
outw(BASE + EP_W4_MEDIA_TYPE, DISABLE_UTP);
|
||||
EP_WRITE_2(sc, EP_W4_MEDIA_TYPE, DISABLE_UTP);
|
||||
GO_WINDOW(0);
|
||||
|
||||
switch (IFM_SUBTYPE(sc->ifmedia.ifm_media)) {
|
||||
@ -841,13 +839,13 @@ ep_ifmedia_upd(struct ifnet *ifp)
|
||||
if (sc->ep_connectors & UTP) {
|
||||
i = ACF_CONNECTOR_UTP;
|
||||
GO_WINDOW(4);
|
||||
outw(BASE + EP_W4_MEDIA_TYPE, ENABLE_UTP);
|
||||
EP_WRITE_2(sc, EP_W4_MEDIA_TYPE, ENABLE_UTP);
|
||||
}
|
||||
break;
|
||||
case IFM_10_2:
|
||||
if (sc->ep_connectors & BNC) {
|
||||
i = ACF_CONNECTOR_BNC;
|
||||
outw(BASE + EP_COMMAND, START_TRANSCEIVER);
|
||||
EP_WRITE_2(sc, EP_COMMAND, START_TRANSCEIVER);
|
||||
DELAY(DELAY_MULTIPLE * 1000);
|
||||
}
|
||||
break;
|
||||
@ -862,8 +860,8 @@ ep_ifmedia_upd(struct ifnet *ifp)
|
||||
}
|
||||
|
||||
GO_WINDOW(0);
|
||||
j = inw(BASE + EP_W0_ADDRESS_CFG) & 0x3fff;
|
||||
outw(BASE + EP_W0_ADDRESS_CFG, j | (i << ACF_CONNECTOR_BITS));
|
||||
j = EP_READ_2(sc, EP_W0_ADDRESS_CFG) & 0x3fff;
|
||||
EP_WRITE_2(sc, EP_W0_ADDRESS_CFG, j | (i << ACF_CONNECTOR_BITS));
|
||||
|
||||
return (0);
|
||||
}
|
||||
@ -953,21 +951,21 @@ epstop(struct ep_softc *sc)
|
||||
{
|
||||
if (sc->gone)
|
||||
return;
|
||||
outw(BASE + EP_COMMAND, RX_DISABLE);
|
||||
outw(BASE + EP_COMMAND, RX_DISCARD_TOP_PACK);
|
||||
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
EP_WRITE_2(sc, EP_COMMAND, RX_DISABLE);
|
||||
EP_WRITE_2(sc, EP_COMMAND, RX_DISCARD_TOP_PACK);
|
||||
while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
|
||||
outw(BASE + EP_COMMAND, TX_DISABLE);
|
||||
outw(BASE + EP_COMMAND, STOP_TRANSCEIVER);
|
||||
EP_WRITE_2(sc, EP_COMMAND, TX_DISABLE);
|
||||
EP_WRITE_2(sc, EP_COMMAND, STOP_TRANSCEIVER);
|
||||
DELAY(800);
|
||||
|
||||
outw(BASE + EP_COMMAND, RX_RESET);
|
||||
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
outw(BASE + EP_COMMAND, TX_RESET);
|
||||
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
EP_WRITE_2(sc, EP_COMMAND, RX_RESET);
|
||||
while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
EP_WRITE_2(sc, EP_COMMAND, TX_RESET);
|
||||
while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
|
||||
outw(BASE + EP_COMMAND, C_INTR_LATCH);
|
||||
outw(BASE + EP_COMMAND, SET_RD_0_MASK);
|
||||
outw(BASE + EP_COMMAND, SET_INTR_MASK);
|
||||
outw(BASE + EP_COMMAND, SET_RX_FILTER);
|
||||
EP_WRITE_2(sc, EP_COMMAND, C_INTR_LATCH);
|
||||
EP_WRITE_2(sc, EP_COMMAND, SET_RD_0_MASK);
|
||||
EP_WRITE_2(sc, EP_COMMAND, SET_INTR_MASK);
|
||||
EP_WRITE_2(sc, EP_COMMAND, SET_RX_FILTER);
|
||||
}
|
||||
|
@ -332,7 +332,7 @@ ep_isa_attach(device_t dev)
|
||||
ep_get_media(sc);
|
||||
|
||||
GO_WINDOW(0);
|
||||
SET_IRQ(BASE, rman_get_start(sc->irq));
|
||||
SET_IRQ(sc, rman_get_start(sc->irq));
|
||||
|
||||
if ((error = ep_attach(sc))) {
|
||||
device_printf(dev, "ep_attach() failed! (%d)\n", error);
|
||||
|
@ -81,6 +81,12 @@ ep_pccard_probe(device_t dev)
|
||||
if (error)
|
||||
return (error);
|
||||
|
||||
/*
|
||||
* It appears that the eeprom comes in two sizes. There's
|
||||
* a 512 byte eeprom and a 2k eeprom. Bit 13 of the eeprom
|
||||
* command register is supposed to contain the size of the
|
||||
* eeprom.
|
||||
*/
|
||||
/*
|
||||
* XXX - Certain (newer?) 3Com cards need epb->cmd_off ==
|
||||
* 2. Sadly, you need to have a correct cmd_off in order to
|
||||
@ -151,15 +157,15 @@ ep_pccard_card_attach(struct ep_board * epb)
|
||||
{
|
||||
/* Determine device type and associated MII capabilities */
|
||||
switch (epb->prod_id) {
|
||||
case 0x6055: /* 3C556 */
|
||||
case 0x2b57: /* 3C572BT */
|
||||
case 0x4057: /* 3C574 */
|
||||
case 0x4b57: /* 3C574B */
|
||||
case 0x0010: /* 3C1 */
|
||||
case 0x6055: /* 3C556 */
|
||||
case 0x2b57: /* 3C572BT */
|
||||
case 0x4057: /* 3C574 */
|
||||
case 0x4b57: /* 3C574B */
|
||||
epb->mii_trans = 1;
|
||||
return (1);
|
||||
case 0x2056: /* 3C562D/3C563D */
|
||||
case 0x9058: /* 3C589 */
|
||||
case 0x0010: /* 3C1 */
|
||||
epb->mii_trans = 0;
|
||||
return (1);
|
||||
default:
|
||||
@ -201,26 +207,26 @@ ep_pccard_attach(device_t dev)
|
||||
|
||||
/* ROM size = 0, ROM base = 0 */
|
||||
/* For now, ignore AUTO SELECT feature of 3C589B and later. */
|
||||
outw(BASE + EP_W0_ADDRESS_CFG, result & 0xc000);
|
||||
EP_WRITE_2(sc, EP_W0_ADDRESS_CFG, result & 0xc000);
|
||||
|
||||
/* Fake IRQ must be 3 */
|
||||
outw(BASE + EP_W0_RESOURCE_CFG, (sc->epb.res_cfg & 0x0fff) | 0x3000);
|
||||
EP_WRITE_2(sc, EP_W0_RESOURCE_CFG, (sc->epb.res_cfg & 0x0fff) | 0x3000);
|
||||
|
||||
outw(BASE + EP_W0_PRODUCT_ID, sc->epb.prod_id);
|
||||
EP_WRITE_2(sc, EP_W0_PRODUCT_ID, sc->epb.prod_id);
|
||||
|
||||
if (sc->epb.mii_trans) {
|
||||
/*
|
||||
* turn on the MII transciever
|
||||
*/
|
||||
GO_WINDOW(3);
|
||||
outw(BASE + EP_W3_OPTIONS, 0x8040);
|
||||
EP_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
|
||||
DELAY(1000);
|
||||
outw(BASE + EP_W3_OPTIONS, 0xc040);
|
||||
outw(BASE + EP_COMMAND, RX_RESET);
|
||||
outw(BASE + EP_COMMAND, TX_RESET);
|
||||
while (inw(BASE + EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
EP_WRITE_2(sc, EP_W3_OPTIONS, 0xc040);
|
||||
EP_WRITE_2(sc, EP_COMMAND, RX_RESET);
|
||||
EP_WRITE_2(sc, EP_COMMAND, TX_RESET);
|
||||
while (EP_READ_2(sc, EP_STATUS) & S_COMMAND_IN_PROGRESS);
|
||||
DELAY(1000);
|
||||
outw(BASE + EP_W3_OPTIONS, 0x8040);
|
||||
EP_WRITE_2(sc, EP_W3_OPTIONS, 0x8040);
|
||||
} else
|
||||
ep_get_media(sc);
|
||||
|
||||
|
@ -59,11 +59,6 @@
|
||||
#define EP_ID_PORT 0x110
|
||||
#define EP_IOSIZE 16 /* 16 bytes of I/O space used. */
|
||||
|
||||
/*
|
||||
* some macros to acces long named fields
|
||||
*/
|
||||
#define BASE (sc->ep_io_addr)
|
||||
|
||||
/*
|
||||
* Commands to read/write EEPROM trough EEPROM command register (Window 0,
|
||||
* Offset 0xa)
|
||||
@ -79,8 +74,8 @@
|
||||
/*
|
||||
* Some short functions, worth to let them be a macro
|
||||
*/
|
||||
#define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
|
||||
#define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
|
||||
#define is_eeprom_busy(sc) (EP_READ_2(sc, EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
|
||||
#define GO_WINDOW(x) EP_WRITE_2(sc, EP_COMMAND, WINDOW_SELECT|(x))
|
||||
|
||||
/**************************************************************************
|
||||
* *
|
||||
@ -343,8 +338,8 @@
|
||||
*
|
||||
*/
|
||||
|
||||
#define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \
|
||||
((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
|
||||
#define SET_IRQ(sc, irq) EP_WRITE_2((sc), EP_W0_RESOURCE_CFG, \
|
||||
((EP_READ_2((sc), EP_W0_RESOURCE_CFG) & 0x0fff) | \
|
||||
((u_short)(irq)<<12)) ) /* set IRQ i */
|
||||
|
||||
/*
|
||||
|
@ -41,12 +41,10 @@ struct ep_softc {
|
||||
struct resource *iobase;
|
||||
struct resource *irq;
|
||||
|
||||
bus_space_handle_t ep_bhandle;
|
||||
bus_space_tag_t ep_btag;
|
||||
bus_space_handle_t bst;
|
||||
bus_space_tag_t bsh;
|
||||
void *ep_intrhand;
|
||||
|
||||
int ep_io_addr; /* i/o bus address */
|
||||
|
||||
u_short ep_connectors; /* Connectors on this card. */
|
||||
u_char ep_connector; /* Configured connector. */
|
||||
|
||||
@ -82,3 +80,22 @@ int ep_attach(struct ep_softc *);
|
||||
void ep_intr(void *);
|
||||
int get_e(struct ep_softc *, u_int16_t, u_int16_t *);
|
||||
int ep_get_macaddr(struct ep_softc *, u_char *);
|
||||
|
||||
#define EP_READ_1(sc, off) (bus_space_read_1((sc)->bsh, (sc)->bst, off))
|
||||
#define EP_READ_2(sc, off) (bus_space_read_2((sc)->bsh, (sc)->bst, off))
|
||||
#define EP_WRITE_1(sc, off, val) \
|
||||
bus_space_write_1(sc->bsh, sc->bst, off, val)
|
||||
#define EP_WRITE_2(sc, off, val) \
|
||||
bus_space_write_2(sc->bsh, sc->bst, off, val)
|
||||
#define EP_WRITE_MULTI_1(sc, off, addr, count) \
|
||||
bus_space_write_multi_1(sc->bsh, sc->bst, off, addr, count)
|
||||
#define EP_WRITE_MULTI_2(sc, off, addr, count) \
|
||||
bus_space_write_multi_2(sc->bsh, sc->bst, off, addr, count)
|
||||
#define EP_WRITE_MULTI_4(sc, off, addr, count) \
|
||||
bus_space_write_multi_4(sc->bsh, sc->bst, off, addr, count)
|
||||
#define EP_READ_MULTI_1(sc, off, addr, count) \
|
||||
bus_space_read_multi_1(sc->bsh, sc->bst, off, addr, count)
|
||||
#define EP_READ_MULTI_2(sc, off, addr, count) \
|
||||
bus_space_read_multi_2(sc->bsh, sc->bst, off, addr, count)
|
||||
#define EP_READ_MULTI_4(sc, off, addr, count) \
|
||||
bus_space_read_multi_4(sc->bsh, sc->bst, off, addr, count)
|
||||
|
Loading…
Reference in New Issue
Block a user