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Remove adv(4) and adw(4)

Browse Source 
Remove the advanssy drivers (both adv and adw). They were tagged as
gone in 12 a while qgo. The nycbug dmesg database shows this was last
seen in 6 and there were only a few adv sightings then (none for adw).

Relnotes: yes
This commit is contained in:
Warner Losh 2018-10-22 02:34:47 +00:00
parent c24bd33d41
commit 43b16da804
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=339567
24 changed files with 2 additions and 10717 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
share/man/man4/Makefile
View File

@ -23,8 +23,6 @@ MAN= aac.4 \
${_acpi_wmi.4} \
ada.4 \
adm6996fc.4 \
adv.4 \
adw.4 \
ae.4 \
${_aesni.4} \
age.4 \

225
share/man/man4/adv.4
View File

@ -1,225 +0,0 @@
.\"
.\" Copyright (c) 1998, 2000
.\" Justin T. Gibbs. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. The name of the author may not be used to endorse or promote products
.\" derived from this software without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd August 8, 2004
.Dt ADV 4
.Os
.Sh NAME
.Nm adv
.Nd Advansys ISA/VL/PCI Narrow 8bit SCSI Host adapter driver
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device scbus"
.Cd "device adv"
.Pp
For one or more VL/ISA cards:
.Cd "device isa"
.Pp
In
.Pa /boot/device.hints :
.Cd hint.adv.0.at="isa"
.Pp
For one or more PCI cards:
.Cd "device pci"
.Ed
.Sh DESCRIPTION
This driver provides access to the narrow 8bit
.Tn SCSI
bus connected to the Advanced Systems Products, Inc.
.Tn ASC900 ,
.Tn ASC1000 ,
.Tn ASC1090 ,
.Tn ASC1200 ,
.Tn ASC3030 ,
.Tn ASC3050 ,
and
.Tn ASC3150
host adapter chips.
The following tables list the AdvanSys products using these chips,
their bus attachment type, maximum sync rate, and the maximum number of
commands that can be handled by the adapter concurrently.
.Bd -ragged -offset indent
Connectivity Products:
.Bl -column "ABP510/5150 " "ISA PnP " "Floppy " "MaxSync " "Commands " "Footnotes "
.Em "Adapter" Ta Em "Bus" Ta Em "Floppy" Ta Em "MaxSync" Ta Em "Commands" Ta Em "Footnotes"
.It "ABP510/5150" Ta "ISA" Ta "\&No" Ta "10MHz" Ta "240" Ta "1"
.It "ABP5140" Ta "ISA PnP" Ta "\&No" Ta "10MHz" Ta "16" Ta "1, 3"
.It "ABP5142" Ta "ISA PnP" Ta "Yes" Ta "10MHz" Ta "16" Ta "4"
.It "ABP[3]902" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta ""
.It "ABP3905" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta ""
.It "ABP915" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta ""
.It "ABP920" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta ""
.It "ABP3922" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta ""
.It "ABP3925" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta ""
.It "ABP930" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta "5"
.It "ABP930U" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "16" Ta ""
.It "ABP930UA" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "16" Ta ""
.It "ABP960" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "16" Ta "2"
.It "ABP960U" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "16" Ta "2"
.El
.Pp
Footnotes:
.Bl -enum -compact
.It
This board has been shipped by HP with the 4020i CD-R drive.
The board has no BIOS so it cannot control a boot device, but
it can control any secondary SCSI device.
.It
This board has been sold by Iomega as a Jaz Jet PCI adapter.
.It
This board has been sold by SIIG as the i540 SpeedMaster.
.It
This board has been sold by SIIG as the i542 SpeedMaster.
.It
This board has been sold by SIIG as the Fast SCSI Pro PCI.
.El
.Ed
.Bd -ragged -offset indent
Single Channel Products:
.Bl -column "ABPX3X940UA " "PCI " "Floppy " "MaxSync " "Commands"
.Em "Adapter" Ta Em "Bus" Ta Em "Floppy" Ta Em "MaxSync" Ta Em "Commands"
.It "ABP542" Ta "ISA" Ta "Yes" Ta "10MHz" Ta "240"
.It "ABP842" Ta "VL" Ta "Yes" Ta "10MHz" Ta "240"
.It "ABP940" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "240"
.It "ABP[3]940UA" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "240"
.It "ABP940U" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "240"
.It "ABP3960UA" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "240"
.It "ABP970" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "240"
.It "ABP970U" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "240"
.El
.Ed
.Bd -ragged -offset indent
Multi Channel Products (Commands are per-channel):
.Bl -column "ABPX3X980UA " "PCI " "Floppy " "MaxSync " "Commands " "Channels"
.Em "Adapter" Ta Em "Bus" Ta Em "Floppy" Ta Em "MaxSync" Ta Em "Commands" Ta Em "Channels"
.It "ABP852" Ta "VL" Ta "Yes" Ta "10MHz" Ta "240" Ta "2"
.It "ABP950" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "240" Ta "2"
.It "ABP980" Ta "PCI" Ta "\&No" Ta "10MHz" Ta "240" Ta "4"
.It "ABP980U" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "240" Ta "4"
.It "ABP[3]980UA" Ta "PCI" Ta "\&No" Ta "20MHz" Ta "16" Ta "4"
.El
.Ed
.Pp
For ISA or Vesa Local Bus adapters, one kernel hints entry is required
for every card to be attached by the system.
Specific values for the port address, irq and drq may be specified.
If unspecified, the driver will query the device for its current
settings and use those.
If the port address is unspecified, the driver will search for it at
one of the possible addresses.
Cards configured for ISA PNP addresses are found automatically.
The possible port addresses for these card are 0x110, 0x130,
0x150, 0x190, 0x210, 0x230, 0x250, and 0x330.
.Pp
Per target configuration performed in the
.Tn AdvanceWare
menu, which is accessible at boot,
is honored by this driver.
This includes synchronous/asynchronous transfers,
maximum synchronous negotiation rate, disconnection, tagged queueing,
and the host adapter's SCSI ID.
The global setting for the maximum number of tagged transactions allowed
per target is not honored as the CAM SCSI system will automatically determine
the maximum number of tags a device can receive as well as guarantee fair
resource allocation among devices.
.Sh HARDWARE
The
.Nm
driver supports the following SCSI controllers:
.Pp
.Bl -bullet -compact
.It
AdvanSys ABP510/5150
.It
AdvanSys ABP5140
.It
AdvanSys ABP5142
.It
AdvanSys ABP902/3902
.It
AdvanSys ABP3905
.It
AdvanSys ABP915
.It
AdvanSys ABP920
.It
AdvanSys ABP3922
.It
AdvanSys ABP3925
.It
AdvanSys ABP930, ABP930U, ABP930UA
.It
AdvanSys ABP960, ABP960U
.It
AdvanSys ABP542
.It
AdvanSys ABP842
.It
AdvanSys ABP940
.It
AdvanSys ABP940UA/3940UA
.It
AdvanSys ABP940U
.It
AdvanSys ABP3960UA
.It
AdvanSys ABP970, ABP970U
.It
AdvanSys ABP852
.It
AdvanSys ABP950
.It
AdvanSys ABP980, ABP980U
.It
AdvanSys ABP980UA/3980UA
.El
.Sh SEE ALSO
.Xr adw 4 ,
.Xr ahc 4 ,
.Xr cd 4 ,
.Xr da 4 ,
.Xr sa 4 ,
.Xr scsi 4
.Sh HISTORY
The
.Nm
driver appeared in
.Fx 3.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was ported by
.An Justin T. Gibbs
from the Linux driver
written by
.An Bob Frey
of Advanced System Products, Inc.
Many thanks to AdvanSys for providing the original driver under a suitable
license for use in
.Fx .

104
share/man/man4/adw.4
View File

@ -1,104 +0,0 @@
.\"
.\" Copyright (c) 1998, 2000
.\" Justin T. Gibbs. All rights reserved.
.\"
.\" Redistribution and use in source and binary forms, with or without
.\" modification, are permitted provided that the following conditions
.\" are met:
.\" 1. Redistributions of source code must retain the above copyright
.\" notice, this list of conditions and the following disclaimer.
.\" 2. The name of the author may not be used to endorse or promote products
.\" derived from this software without specific prior written permission.
.\"
.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
.\" IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
.\" OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
.\" IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
.\" INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
.\" NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
.\" DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
.\" THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
.\" (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
.\" THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
.\"
.\" $FreeBSD$
.\"
.Dd July 14, 2004
.Dt ADW 4
.Os
.Sh NAME
.Nm adw
.Nd Advansys PCI 16bit SCSI Host adapter driver
.Sh SYNOPSIS
To compile this driver into the kernel,
place the following lines in your
kernel configuration file:
.Bd -ragged -offset indent
.Cd "device pci"
.Cd "device scbus"
.Cd "device adw"
.Ed
.Sh DESCRIPTION
This driver provides access to the 16bit
.Tn SCSI
bus connected to the Advanced Systems Products, Inc.
.Tn ASC3550 Ultra ,
and
.Tn ASC38C0800 Ultra2 ,
SCSI Host Adapter chips.
Both chips support, synchronous transfers
(20MHz and 40MHz max respectively),
16bit transfers, tagged queueing,
and up to 253 concurrent SCSI transactions.
.Pp
Per target configuration performed in the
.Tn AdvanceWare
menu, which is accessible at boot,
is honored by this driver.
This includes synchronous/asynchronous transfers,
maximum synchronous negotiation rate, wide transfers, disconnection,
tagged queueing, and the host adapter's SCSI ID.
The global setting for the maximum number of tagged transactions allowed
per target is not honored as the CAM SCSI system will automatically determine
the maximum number of tags a device can receive as well as guarantee fair
resource allocation among devices.
.Sh HARDWARE
The
.Nm
driver supports SCSI controllers including:
.Pp
.Bl -bullet -compact
.It
AdvanSys ABP940UW/ABP3940UW
.It
AdvanSys ABP950UW
.It
AdvanSys ABP970UW
.It
AdvanSys ABP3940U2W
.It
AdvanSys ABP3950U2W
.El
.Sh SEE ALSO
.Xr adv 4 ,
.Xr cd 4 ,
.Xr da 4 ,
.Xr sa 4 ,
.Xr scsi 4
.Sh HISTORY
The
.Nm
driver appeared in
.Fx 3.0 .
.Sh AUTHORS
.An -nosplit
The
.Nm
driver was ported by
.An Justin T. Gibbs
from the Linux driver written by
.An Bob Frey
of Advanced System Products, Inc.
Many thanks to AdvanSys for providing the original driver
under a suitable license for use in
.Fx .

9
sys/conf/NOTES
View File

@ -1548,8 +1548,6 @@ options TERMINAL_KERN_ATTR=(FG_LIGHTRED|BG_BLACK)
#
# SCSI host adapters:
#
# adv: All Narrow SCSI bus AdvanSys controllers.
# adw: Second Generation AdvanSys controllers including the ADV940UW.
# ahc: Adaptec 274x/284x/2910/293x/294x/394x/3950x/3960x/398X/4944/
# 19160x/29160x, aic7770/aic78xx
# ahd: Adaptec 29320/39320 Controllers.
@ -1581,9 +1579,6 @@ options TERMINAL_KERN_ATTR=(FG_LIGHTRED|BG_BLACK)
device bt
hint.bt.0.at="isa"
hint.bt.0.port="0x330"
device adv
hint.adv.0.at="isa"
device adw
device ahc
device ahd
device esp
@ -1644,10 +1639,6 @@ options AHD_REG_PRETTY_PRINT
# Bitmap of units to enable targetmode operations.
options AHD_TMODE_ENABLE
# The adw driver will attempt to use memory mapped I/O for all PCI
# controllers that have it configured only if this option is set.
options ADW_ALLOW_MEMIO
# Options used in dev/iscsi (Software iSCSI stack)
#
options ISCSI_INITIATOR_DEBUG=9

1
sys/conf/WITHOUT_SOURCELESS_UCODE
View File

@ -4,7 +4,6 @@
#
# $FreeBSD$
nodevice adw
nodevice bce
nodevice fxp
nodevice ispfw

8
sys/conf/files
View File

@ -755,14 +755,6 @@ dev/acpica/acpi_throttle.c optional acpi
dev/acpica/acpi_video.c optional acpi_video acpi
dev/acpica/acpi_dock.c optional acpi_dock acpi
dev/adlink/adlink.c optional adlink
dev/advansys/adv_pci.c optional adv pci
dev/advansys/advansys.c optional adv
dev/advansys/advlib.c optional adv
dev/advansys/advmcode.c optional adv
dev/advansys/adw_pci.c optional adw pci
dev/advansys/adwcam.c optional adw
dev/advansys/adwlib.c optional adw
dev/advansys/adwmcode.c optional adw
dev/ae/if_ae.c optional ae pci
dev/age/if_age.c optional age pci
dev/agp/agp.c optional agp pci

1
sys/conf/files.i386
View File

@ -151,7 +151,6 @@ dev/acpica/acpi_pci_link.c optional acpi pci
dev/acpica/acpi_pcib.c optional acpi pci
dev/acpica/acpi_pcib_acpi.c optional acpi pci
dev/acpica/acpi_pcib_pci.c optional acpi pci
dev/advansys/adv_isa.c optional adv isa
dev/agp/agp_ali.c optional agp
dev/agp/agp_amd.c optional agp
dev/agp/agp_amd64.c optional agp

1
sys/conf/options
View File

@ -42,7 +42,6 @@ AHD_DEBUG opt_aic79xx.h
AHD_DEBUG_OPTS opt_aic79xx.h
AHD_TMODE_ENABLE opt_aic79xx.h
AHD_REG_PRETTY_PRINT opt_aic79xx.h
ADW_ALLOW_MEMIO opt_adw.h
TWA_DEBUG opt_twa.h

436
sys/dev/advansys/adv_isa.c
View File

@ -1,436 +0,0 @@
/*-
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* Connectivity Products:
* ABP510/5150 - Bus-Master ISA (240 CDB) *
* ABP5140 - Bus-Master ISA PnP (16 CDB) * **
* ABP5142 - Bus-Master ISA PnP with floppy (16 CDB) ***
*
* Single Channel Products:
* ABP542 - Bus-Master ISA with floppy (240 CDB)
* ABP842 - Bus-Master VL (240 CDB)
*
* Dual Channel Products:
* ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
*
* * This board has been shipped by HP with the 4020i CD-R drive.
* The board has no BIOS so it cannot control a boot device, but
* it can control any secondary SCSI device.
* ** This board has been sold by SIIG as the i540 SpeedMaster.
* *** This board has been sold by SIIG as the i542 SpeedMaster.
*
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 1996, 1997 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <isa/isavar.h>
#include <dev/advansys/advansys.h>
#include <cam/scsi/scsi_all.h>
#define ADV_ISA_MAX_DMA_ADDR (0x00FFFFFFL)
#define ADV_ISA_MAX_DMA_COUNT (0x00FFFFFFL)
#define ADV_VL_MAX_DMA_ADDR (0x07FFFFFFL)
#define ADV_VL_MAX_DMA_COUNT (0x07FFFFFFL)
/*
* The overrun buffer shared amongst all ISA/VL adapters.
*/
static u_int8_t* overrun_buf;
static bus_dma_tag_t overrun_dmat;
static bus_dmamap_t overrun_dmamap;
static bus_addr_t overrun_physbase;
/* Possible port addresses an ISA or VL adapter can live at */
static u_int16_t adv_isa_ioports[] =
{
0x100,
0x110, /* First selection in BIOS setup */
0x120,
0x130, /* Second selection in BIOS setup */
0x140,
0x150, /* Third selection in BIOS setup */
0x190, /* Fourth selection in BIOS setup */
0x210, /* Fifth selection in BIOS setup */
0x230, /* Sixth selection in BIOS setup */
0x250, /* Seventh selection in BIOS setup */
0x330 /* Eighth and default selection in BIOS setup */
};
#define MAX_ISA_IOPORT_INDEX (nitems(adv_isa_ioports) - 1)
static int adv_isa_probe(device_t dev);
static int adv_isa_attach(device_t dev);
static void adv_set_isapnp_wait_for_key(void);
static int adv_get_isa_dma_channel(struct adv_softc *adv);
static int adv_set_isa_dma_settings(struct adv_softc *adv);
static int
adv_isa_probe(device_t dev)
{
int port_index;
int max_port_index;
rman_res_t iobase, iocount, irq;
int user_iobase = 0;
int rid = 0;
void *ih;
struct resource *iores, *irqres;
/*
* We don't know of any PnP ID's for these cards.
*/
if (isa_get_logicalid(dev) != 0)
return (ENXIO);
/*
* Default to scanning all possible device locations.
*/
port_index = 0;
max_port_index = MAX_ISA_IOPORT_INDEX;
if (bus_get_resource(dev, SYS_RES_IOPORT, 0, &iobase, &iocount) == 0) {
user_iobase = 1;
for (;port_index <= max_port_index; port_index++)
if (iobase <= adv_isa_ioports[port_index])
break;
if ((port_index > max_port_index)
|| (iobase != adv_isa_ioports[port_index])) {
if (bootverbose)
device_printf(dev,
"Invalid baseport of 0x%jx specified. "
"Nearest valid baseport is 0x%x. Failing "
"probe.\n", iobase,
(port_index <= max_port_index) ?
adv_isa_ioports[port_index] :
adv_isa_ioports[max_port_index]);
return ENXIO;
}
max_port_index = port_index;
}
/* Perform the actual probing */
adv_set_isapnp_wait_for_key();
for (;port_index <= max_port_index; port_index++) {
u_int16_t port_addr = adv_isa_ioports[port_index];
bus_size_t maxsegsz;
bus_size_t maxsize;
bus_addr_t lowaddr;
int error;
struct adv_softc *adv;
if (port_addr == 0)
/* Already been attached */
continue;
if (bus_set_resource(dev, SYS_RES_IOPORT, 0, port_addr, 1))
continue;
/* XXX what is the real portsize? */
iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
RF_ACTIVE);
if (iores == NULL)
continue;
if (adv_find_signature(iores) == 0) {
bus_release_resource(dev, SYS_RES_IOPORT, 0, iores);
continue;
}
/*
* Got one. Now allocate our softc
* and see if we can initialize the card.
*/
adv = adv_alloc(dev, iores, 0);
if (adv == NULL) {
bus_release_resource(dev, SYS_RES_IOPORT, 0, iores);
break;
}
/*
* Stop the chip.
*/
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
/*
* Determine the chip version.
*/
adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
if ((adv->chip_version >= ADV_CHIP_MIN_VER_VL)
&& (adv->chip_version <= ADV_CHIP_MAX_VER_VL)) {
adv->type = ADV_VL;
maxsegsz = ADV_VL_MAX_DMA_COUNT;
maxsize = BUS_SPACE_MAXSIZE_32BIT;
lowaddr = ADV_VL_MAX_DMA_ADDR;
bus_delete_resource(dev, SYS_RES_DRQ, 0);
} else if ((adv->chip_version >= ADV_CHIP_MIN_VER_ISA)
&& (adv->chip_version <= ADV_CHIP_MAX_VER_ISA)) {
if (adv->chip_version >= ADV_CHIP_MIN_VER_ISA_PNP) {
adv->type = ADV_ISAPNP;
ADV_OUTB(adv, ADV_REG_IFC,
ADV_IFC_INIT_DEFAULT);
} else {
adv->type = ADV_ISA;
}
maxsegsz = ADV_ISA_MAX_DMA_COUNT;
maxsize = BUS_SPACE_MAXSIZE_24BIT;
lowaddr = ADV_ISA_MAX_DMA_ADDR;
adv->isa_dma_speed = ADV_DEF_ISA_DMA_SPEED;
adv->isa_dma_channel = adv_get_isa_dma_channel(adv);
bus_set_resource(dev, SYS_RES_DRQ, 0,
adv->isa_dma_channel, 1);
} else {
panic("advisaprobe: Unknown card revision\n");
}
/*
* Allocate a parent dmatag for all tags created
* by the MI portions of the advansys driver
*/
error = bus_dma_tag_create(
/* parent */ bus_get_dma_tag(dev),
/* alignemnt */ 1,
/* boundary */ 0,
/* lowaddr */ lowaddr,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ maxsize,
/* nsegments */ ~0,
/* maxsegsz */ maxsegsz,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&adv->parent_dmat);
if (error != 0) {
device_printf(dev,
"Could not allocate DMA tag - error %d\n", error);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, 0, iores);
break;
}
adv->init_level += 2;
if (overrun_buf == NULL) {
/* Need to allocate our overrun buffer */
if (bus_dma_tag_create(
/* parent */ adv->parent_dmat,
/* alignment */ 8,
/* boundary */ 0,
/* lowaddr */ ADV_ISA_MAX_DMA_ADDR,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ ADV_OVERRUN_BSIZE,
/* nsegments */ 1,
/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&overrun_dmat) != 0) {
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, 0,
iores);
break;
}
if (bus_dmamem_alloc(overrun_dmat,
(void **)&overrun_buf,
BUS_DMA_NOWAIT,
&overrun_dmamap) != 0) {
bus_dma_tag_destroy(overrun_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, 0,
iores);
break;
}
/* And permanently map it in */
bus_dmamap_load(overrun_dmat, overrun_dmamap,
overrun_buf, ADV_OVERRUN_BSIZE,
adv_map, &overrun_physbase,
/*flags*/0);
}
adv->overrun_physbase = overrun_physbase;
if (adv_init(adv) != 0) {
bus_dmamap_unload(overrun_dmat, overrun_dmamap);
bus_dmamem_free(overrun_dmat, overrun_buf,
overrun_dmamap);
bus_dma_tag_destroy(overrun_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, 0, iores);
break;
}
switch (adv->type) {
case ADV_ISAPNP:
if (adv->chip_version == ADV_CHIP_VER_ASYN_BUG) {
adv->bug_fix_control
|= ADV_BUG_FIX_ASYN_USE_SYN;
adv->fix_asyn_xfer = ~0;
}
/* Fall Through */
case ADV_ISA:
adv->max_dma_count = ADV_ISA_MAX_DMA_COUNT;
adv->max_dma_addr = ADV_ISA_MAX_DMA_ADDR;
adv_set_isa_dma_settings(adv);
break;
case ADV_VL:
adv->max_dma_count = ADV_VL_MAX_DMA_COUNT;
adv->max_dma_addr = ADV_VL_MAX_DMA_ADDR;
break;
default:
panic("advisaprobe: Invalid card type\n");
}
/* Determine our IRQ */
if (bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, NULL))
bus_set_resource(dev, SYS_RES_IRQ, 0,
adv_get_chip_irq(adv), 1);
else
adv_set_chip_irq(adv, irq);
irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (irqres == NULL ||
bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|
INTR_MPSAFE, NULL, adv_intr, adv, &ih) != 0) {
if (irqres != NULL)
bus_release_resource(dev, SYS_RES_IRQ, rid,
irqres);
bus_dmamap_unload(overrun_dmat, overrun_dmamap);
bus_dmamem_free(overrun_dmat, overrun_buf,
overrun_dmamap);
bus_dma_tag_destroy(overrun_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, 0, iores);
break;
}
/* Mark as probed */
adv_isa_ioports[port_index] = 0;
return 0;
}
if (user_iobase)
bus_set_resource(dev, SYS_RES_IOPORT, 0, iobase, iocount);
else
bus_delete_resource(dev, SYS_RES_IOPORT, 0);
return ENXIO;
}
static int
adv_isa_attach(device_t dev)
{
struct adv_softc *adv = device_get_softc(dev);
return (adv_attach(adv));
}
static int
adv_get_isa_dma_channel(struct adv_softc *adv)
{
int channel;
channel = ADV_INW(adv, ADV_CONFIG_LSW) & ADV_CFG_LSW_ISA_DMA_CHANNEL;
if (channel == 0x03)
return (0);
else if (channel == 0x00)
return (7);
return (channel + 4);
}
static int
adv_set_isa_dma_settings(struct adv_softc *adv)
{
u_int16_t cfg_lsw;
u_int8_t value;
if ((adv->isa_dma_channel >= 5) && (adv->isa_dma_channel <= 7)) {
if (adv->isa_dma_channel == 7)
value = 0x00;
else
value = adv->isa_dma_channel - 4;
cfg_lsw = ADV_INW(adv, ADV_CONFIG_LSW)
& ~ADV_CFG_LSW_ISA_DMA_CHANNEL;
cfg_lsw |= value;
ADV_OUTW(adv, ADV_CONFIG_LSW, cfg_lsw);
adv->isa_dma_speed &= 0x07;
adv_set_bank(adv, 1);
ADV_OUTB(adv, ADV_DMA_SPEED, adv->isa_dma_speed);
adv_set_bank(adv, 0);
isa_dmacascade(adv->isa_dma_channel);
}
return (0);
}
static void
adv_set_isapnp_wait_for_key(void)
{
static int isapnp_wait_set = 0;
if (isapnp_wait_set == 0) {
outb(ADV_ISA_PNP_PORT_ADDR, 0x02);
outb(ADV_ISA_PNP_PORT_WRITE, 0x02);
isapnp_wait_set++;
}
}
static device_method_t adv_isa_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, adv_isa_probe),
DEVMETHOD(device_attach, adv_isa_attach),
{ 0, 0 }
};
static driver_t adv_isa_driver = {
"adv", adv_isa_methods, sizeof(struct adv_softc)
};
static devclass_t adv_isa_devclass;
DRIVER_MODULE(adv, isa, adv_isa_driver, adv_isa_devclass, 0, 0);
MODULE_DEPEND(adv, isa, 1, 1, 1);

332
sys/dev/advansys/adv_pci.c
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@ -1,332 +0,0 @@
/*-
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* Connectivity Products:
* ABP902/3902 - Bus-Master PCI (16 CDB)
* ABP3905 - Bus-Master PCI (16 CDB)
* ABP915 - Bus-Master PCI (16 CDB)
* ABP920 - Bus-Master PCI (16 CDB)
* ABP3922 - Bus-Master PCI (16 CDB)
* ABP3925 - Bus-Master PCI (16 CDB)
* ABP930 - Bus-Master PCI (16 CDB) *
* ABP930U - Bus-Master PCI Ultra (16 CDB)
* ABP930UA - Bus-Master PCI Ultra (16 CDB)
* ABP960 - Bus-Master PCI MAC/PC (16 CDB) **
* ABP960U - Bus-Master PCI MAC/PC (16 CDB) **
*
* Single Channel Products:
* ABP940 - Bus-Master PCI (240 CDB)
* ABP940U - Bus-Master PCI Ultra (240 CDB)
* ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
* ABP3960UA - Bus-Master PCI MAC/PC (240 CDB)
* ABP970 - Bus-Master PCI MAC/PC (240 CDB)
* ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
*
* Dual Channel Products:
* ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
* ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
* ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
* ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
*
* Footnotes:
* * This board has been sold by SIIG as the Fast SCSI Pro PCI.
* ** This board has been sold by Iomega as a Jaz Jet PCI adapter.
*
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 1997 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <dev/advansys/advansys.h>
#define PCI_BASEADR0 PCIR_BAR(0) /* I/O Address */
#define PCI_BASEADR1 PCIR_BAR(1) /* Mem I/O Address */
#define PCI_DEVICE_ID_ADVANSYS_1200A 0x110010CD
#define PCI_DEVICE_ID_ADVANSYS_1200B 0x120010CD
#define PCI_DEVICE_ID_ADVANSYS_3000 0x130010CD
#define PCI_DEVICE_REV_ADVANSYS_3150 0x02
#define PCI_DEVICE_REV_ADVANSYS_3050 0x03
#define ADV_PCI_MAX_DMA_ADDR (0xFFFFFFFFL)
#define ADV_PCI_MAX_DMA_COUNT (0xFFFFFFFFL)
static int adv_pci_probe(device_t);
static int adv_pci_attach(device_t);
/*
* The overrun buffer shared amongst all PCI adapters.
*/
static void* overrun_buf;
static bus_dma_tag_t overrun_dmat;
static bus_dmamap_t overrun_dmamap;
static bus_addr_t overrun_physbase;
static int
adv_pci_probe(device_t dev)
{
int rev = pci_get_revid(dev);
switch (pci_get_devid(dev)) {
case PCI_DEVICE_ID_ADVANSYS_1200A:
device_set_desc(dev, "AdvanSys ASC1200A SCSI controller");
return BUS_PROBE_DEFAULT;
case PCI_DEVICE_ID_ADVANSYS_1200B:
device_set_desc(dev, "AdvanSys ASC1200B SCSI controller");
return BUS_PROBE_DEFAULT;
case PCI_DEVICE_ID_ADVANSYS_3000:
if (rev == PCI_DEVICE_REV_ADVANSYS_3150) {
device_set_desc(dev,
"AdvanSys ASC3150 SCSI controller");
return BUS_PROBE_DEFAULT;
} else if (rev == PCI_DEVICE_REV_ADVANSYS_3050) {
device_set_desc(dev,
"AdvanSys ASC3030/50 SCSI controller");
return BUS_PROBE_DEFAULT;
} else if (rev >= PCI_DEVICE_REV_ADVANSYS_3150) {
device_set_desc(dev, "Unknown AdvanSys controller");
return BUS_PROBE_DEFAULT;
}
break;
default:
break;
}
return ENXIO;
}
static int
adv_pci_attach(device_t dev)
{
struct adv_softc *adv;
u_int32_t id;
int error, rid, irqrid;
void *ih;
struct resource *iores, *irqres;
/*
* Determine the chip version.
*/
id = pci_get_devid(dev);
pci_enable_busmaster(dev);
/*
* Early chips can't handle non-zero latency timer settings.
*/
if (id == PCI_DEVICE_ID_ADVANSYS_1200A
|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
pci_write_config(dev, PCIR_LATTIMER, /*value*/0, /*bytes*/1);
}
rid = PCI_BASEADR0;
iores = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
RF_ACTIVE);
if (iores == NULL)
return ENXIO;
if (adv_find_signature(iores) == 0) {
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
adv = adv_alloc(dev, iores, 0);
if (adv == NULL) {
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
/* Allocate a dmatag for our transfer DMA maps */
error = bus_dma_tag_create(
/* parent */ bus_get_dma_tag(dev),
/* alignment */ 1,
/* boundary */ 0,
/* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
/* nsegments */ ~0,
/* maxsegsz */ ADV_PCI_MAX_DMA_COUNT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&adv->parent_dmat);
if (error != 0) {
device_printf(dev, "Could not allocate DMA tag - error %d\n",
error);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
adv->init_level++;
if (overrun_buf == NULL) {
/* Need to allocate our overrun buffer */
if (bus_dma_tag_create(
/* parent */ adv->parent_dmat,
/* alignment */ 8,
/* boundary */ 0,
/* lowaddr */ ADV_PCI_MAX_DMA_ADDR,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ ADV_OVERRUN_BSIZE,
/* nsegments */ 1,
/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&overrun_dmat) != 0) {
bus_dma_tag_destroy(adv->parent_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
if (bus_dmamem_alloc(overrun_dmat,
&overrun_buf,
BUS_DMA_NOWAIT,
&overrun_dmamap) != 0) {
bus_dma_tag_destroy(overrun_dmat);
bus_dma_tag_destroy(adv->parent_dmat);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
/* And permanently map it in */
bus_dmamap_load(overrun_dmat, overrun_dmamap,
overrun_buf, ADV_OVERRUN_BSIZE,
adv_map, &overrun_physbase,
/*flags*/0);
}
adv->overrun_physbase = overrun_physbase;
/*
* Stop the chip.
*/
ADV_OUTB(adv, ADV_CHIP_CTRL, ADV_CC_HALT);
ADV_OUTW(adv, ADV_CHIP_STATUS, 0);
adv->chip_version = ADV_INB(adv, ADV_NONEISA_CHIP_REVISION);
adv->type = ADV_PCI;
/*
* Setup active negation and signal filtering.
*/
{
u_int8_t extra_cfg;
if (adv->chip_version >= ADV_CHIP_VER_PCI_ULTRA_3150)
adv->type |= ADV_ULTRA;
if (adv->chip_version == ADV_CHIP_VER_PCI_ULTRA_3050)
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_WR_EN_FILTER;
else
extra_cfg = ADV_IFC_ACT_NEG | ADV_IFC_SLEW_RATE;
ADV_OUTB(adv, ADV_REG_IFC, extra_cfg);
}
if (adv_init(adv) != 0) {
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
adv->max_dma_count = ADV_PCI_MAX_DMA_COUNT;
adv->max_dma_addr = ADV_PCI_MAX_DMA_ADDR;
#if defined(CC_DISABLE_PCI_PARITY_INT) && CC_DISABLE_PCI_PARITY_INT
{
u_int16_t config_msw;
config_msw = ADV_INW(adv, ADV_CONFIG_MSW);
config_msw &= 0xFFC0;
ADV_OUTW(adv, ADV_CONFIG_MSW, config_msw);
}
#endif
if (id == PCI_DEVICE_ID_ADVANSYS_1200A
|| id == PCI_DEVICE_ID_ADVANSYS_1200B) {
adv->bug_fix_control |= ADV_BUG_FIX_IF_NOT_DWB;
adv->bug_fix_control |= ADV_BUG_FIX_ASYN_USE_SYN;
adv->fix_asyn_xfer = ~0;
}
irqrid = 0;
irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &irqrid,
RF_SHAREABLE | RF_ACTIVE);
if (irqres == NULL ||
bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE,
NULL, adv_intr, adv, &ih) != 0) {
if (irqres != NULL)
bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
if (adv_attach(adv) != 0) {
bus_teardown_intr(dev, irqres, ih);
bus_release_resource(dev, SYS_RES_IRQ, irqrid, irqres);
adv_free(adv);
bus_release_resource(dev, SYS_RES_IOPORT, rid, iores);
return ENXIO;
}
return 0;
}
static device_method_t adv_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, adv_pci_probe),
DEVMETHOD(device_attach, adv_pci_attach),
{ 0, 0 }
};
static driver_t adv_pci_driver = {
"adv", adv_pci_methods, sizeof(struct adv_softc)
};
static devclass_t adv_pci_devclass;
DRIVER_MODULE(adv, pci, adv_pci_driver, adv_pci_devclass, 0, 0);
MODULE_DEPEND(adv, pci, 1, 1, 1);

1406
sys/dev/advansys/advansys.c
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55
sys/dev/advansys/advansys.h
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@ -1,55 +0,0 @@
/*-
* Generic driver definitions and exported functions for the Advanced
* Systems Inc. SCSI controllers
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1996-1997 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* All rights reserved.
*
* $FreeBSD$
*/
#ifndef _ADVANSYS_H_
#define _ADVANSYS_H_
#include <dev/advansys/advlib.h>
struct adv_softc * adv_alloc(device_t dev, struct resource *res, long offset);
void adv_map(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
void adv_free(struct adv_softc *adv);
int adv_init(struct adv_softc *adv);
void adv_intr(void *arg);
int adv_attach(struct adv_softc *adv);
void adv_done(struct adv_softc *adv, union ccb* ccb,
u_int done_stat, u_int host_stat,
u_int scsi_stat, u_int q_no);
void adv_timeout(void *arg);
#endif /* _ADVANSYS_H_ */

2096
sys/dev/advansys/advlib.c
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876
sys/dev/advansys/advlib.h
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@ -1,876 +0,0 @@
/*-
* Definitions for low level routines and data structures
* for the Advanced Systems Inc. SCSI controllers chips.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1996-1997, 1999-2000 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*-
* Ported from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1996 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#ifndef _ADVLIB_H_
#define _ADVLIB_H_
#include <sys/queue.h>
struct cam_path;
union ccb;
typedef u_int8_t target_bit_vector;
#define TARGET_BIT_VECTOR_SET -1
#define ADV_SCSI_ID_BITS 3
#define ADV_MAX_TID 7
#define ADV_MAX_LUN 7
#define ADV_MAXPHYS (128 * 1024)
/* Enumeration of board types */
typedef enum {
ADV_NONE = 0x000,
ADV_ISA = 0x001,
ADV_ISAPNP = 0x003,
ADV_VL = 0x004,
ADV_PCI = 0x010,
ADV_PCMCIA = 0x040,
ADV_ULTRA = 0x100,
ADV_WIDE = 0x200,
ADV_WIDE32 = 0x400
} adv_btype;
typedef enum {
ADV_STATE_NONE = 0x00,
ADV_RESOURCE_SHORTAGE = 0x01,
ADV_IN_TIMEOUT = 0x02,
ADV_BUSDMA_BLOCK = 0x04,
ADV_BUSDMA_BLOCK_CLEARED = 0x08
} adv_state;
typedef enum {
ACCB_FREE = 0x00,
ACCB_ACTIVE = 0x01,
ACCB_ABORT_QUEUED = 0x02,
ACCB_RECOVERY_CCB = 0x04
} adv_ccb_state;
struct adv_ccb_info {
adv_ccb_state state;
bus_dmamap_t dmamap;
struct callout timer;
union ccb* ccb;
SLIST_ENTRY(adv_ccb_info) links;
};
#define ccb_cinfo_ptr spriv_ptr0
#define ADV_SYN_XFER_NO 8
#define ADV_SYN_MAX_OFFSET 0x0F
#define ADV_DEF_SDTR_OFFSET 0x0F
#define ADV_DEF_SDTR_INDEX 0x00
#define ADV_OVERRUN_BSIZE 0x00000040
#define ADV_MAX_CDB_LEN 12
#define ADV_MAX_SENSE_LEN 32
#define ADV_MIN_SENSE_LEN 14
#define ADV_TIDLUN_TO_IX(tid, lun) ((tid) | ((lun) << ADV_SCSI_ID_BITS) )
#define ADV_TID_TO_TARGET_MASK(tid) (0x01 << (tid))
#define ADV_TIX_TO_TARGET_MASK(tix) (0x01 << ((tix) & ADV_MAX_TID))
#define ADV_TIX_TO_TID(tix) ((tix) & ADV_MAX_TID)
#define ADV_TID_TO_TIX(tid) ((tid) & ADV_MAX_TID)
#define ADV_TIX_TO_LUN(tix) (((tix) >> ADV_SCSI_ID_BITS) & ADV_MAX_LUN )
/*
* XXX
* PnP port addresses
* I believe that these are standard PnP address and should be replaced
* by the values in a central ISA PnP header file when we get one.
*/
#define ADV_ISA_PNP_PORT_ADDR (0x279)
#define ADV_ISA_PNP_PORT_WRITE (ADV_ISA_PNP_PORT_ADDR+0x800)
/*
* Board Signatures
*/
#define ADV_SIGNATURE_WORD 0x0000
#define ADV_1000_ID0W 0x04C1
#define ADV_1000_ID0W_FIX 0x00C1
#define ADV_SIGNATURE_BYTE 0x0001
#define ADV_1000_ID1B 0x25
#define ADV_REG_IH 0x0002
#define ADV_INS_HALTINT 0x6281
#define ADV_INS_HALT 0x6280
#define ADV_INS_SINT 0x6200
#define ADV_INS_RFLAG_WTM 0x7380
#define ADV_CONFIG_LSW 0x0002
#define ADV_CFG_LSW_ISA_DMA_CHANNEL 0x0003
#define ADV_CFG_LSW_HOST_INT_ON 0x0020
#define ADV_CFG_LSW_BIOS_ON 0x0040
#define ADV_CFG_LSW_VERA_BURST_ON 0x0080
#define ADV_CFG_LSW_SCSI_PARITY_ON 0x0800
#define ADV_CFG_LSW_SCSIID 0x0700
#define ADV_CFG_LSW_SCSIID_SHIFT 8
#define ADV_CONFIG_SCSIID(cfg) ((cfg >> ADV_CFG_LSW_SCSIID_SHIFT) & ADV_MAX_TID)
/*
* Chip Revision Number
*/
#define ADV_NONEISA_CHIP_REVISION 0x0003
#define ADV_CHIP_MIN_VER_VL 0x01
#define ADV_CHIP_MAX_VER_VL 0x07
#define ADV_CHIP_MIN_VER_PCI 0x09
#define ADV_CHIP_MAX_VER_PCI 0x0F
#define ADV_CHIP_VER_PCI_BIT 0x08
#define ADV_CHIP_VER_PCI_ULTRA_3150 (ADV_CHIP_VER_PCI_BIT | 0x02)
#define ADV_CHIP_VER_PCI_ULTRA_3050 (ADV_CHIP_VER_PCI_BIT | 0x03)
#define ADV_CHIP_MIN_VER_ISA 0x11
#define ADV_CHIP_MIN_VER_ISA_PNP 0x21
#define ADV_CHIP_MAX_VER_ISA 0x27
#define ADV_CHIP_VER_ISA_BIT 0x30
#define ADV_CHIP_VER_ISAPNP_BIT 0x20
#define ADV_CHIP_VER_ASYN_BUG 0x21
#define ADV_CONFIG_MSW 0x0004
#define ADV_CFG_MSW_SCSI_TARGET_ON 0x0080
#define ADV_CFG_MSW_LRAM_8BITS_ON 0x0800
#define ADV_CFG_MSW_CLR_MASK 0x30C0
#define ADV_EEPROM_DATA 0x0006
#define ADV_EEPROM_CMD 0x0007
#define ADV_EEPROM_CMD_READ 0x80
#define ADV_EEPROM_CMD_WRITE 0x40
#define ADV_EEPROM_CMD_WRITE_ENABLE 0x30
#define ADV_EEPROM_CMD_WRITE_DISABLE 0x00
#define ADV_DMA_SPEED 0x0007
#define ADV_DEF_ISA_DMA_SPEED 4
#define ADV_REG_FLAG 0x0007
#define ADV_LRAM_DATA 0x0008
#define ADV_LRAM_ADDR 0x000A
#define ADV_SYN_OFFSET 0x000B
#define ADV_REG_PROG_COUNTER 0x000C
#define ADV_MCODE_START_ADDR 0x0080
#define ADV_REG_IFC 0x000D
#define ADV_IFC_REG_LOCK 0x00
#define ADV_IFC_REG_UNLOCK 0x09
#define ADV_IFC_WR_EN_FILTER 0x10
#define ADV_IFC_RD_NO_EEPROM 0x10
#define ADV_IFC_SLEW_RATE 0x20
#define ADV_IFC_ACT_NEG 0x40
#define ADV_IFC_INP_FILTER 0x80
#define ADV_IFC_INIT_DEFAULT (ADV_IFC_ACT_NEG | ADV_IFC_REG_UNLOCK)
#define ADV_CHIP_STATUS 0x000E
#define ADV_CSW_TEST1 0x8000
#define ADV_CSW_AUTO_CONFIG 0x4000
#define ADV_CSW_RESERVED1 0x2000
#define ADV_CSW_IRQ_WRITTEN 0x1000
#define ADV_CSW_33MHZ_SELECTED 0x0800
#define ADV_CSW_TEST2 0x0400
#define ADV_CSW_TEST3 0x0200
#define ADV_CSW_RESERVED2 0x0100
#define ADV_CSW_DMA_DONE 0x0080
#define ADV_CSW_FIFO_RDY 0x0040
#define ADV_CSW_EEP_READ_DONE 0x0020
#define ADV_CSW_HALTED 0x0010
#define ADV_CSW_SCSI_RESET_ACTIVE 0x0008
#define ADV_CSW_PARITY_ERR 0x0004
#define ADV_CSW_SCSI_RESET_LATCH 0x0002
#define ADV_CSW_INT_PENDING 0x0001
/*
* XXX I don't understand the relevance of the naming
* convention change here. What does CIW stand for?
* Perhaps this is to differentiate read and write
* values?
*/
#define ADV_CIW_INT_ACK 0x0100
#define ADV_CIW_TEST1 0x0200
#define ADV_CIW_TEST2 0x0400
#define ADV_CIW_SEL_33MHZ 0x0800
#define ADV_CIW_IRQ_ACT 0x1000
#define ADV_CIW_CLR_SCSI_RESET_INT 0x1000
#define ADV_CHIP_CTRL 0x000F
#define ADV_CC_CHIP_RESET 0x80
#define ADV_CC_SCSI_RESET 0x40
#define ADV_CC_HALT 0x20
#define ADV_CC_SINGLE_STEP 0x10
#define ADV_CC_DMA_ENABLE 0x08
#define ADV_CC_TEST 0x04
#define ADV_CC_BANK_ONE 0x02
#define ADV_CC_DIAG 0x01
#define ADV_HALTCODE_W 0x0040
#define ADV_STOP_CODE_B 0x0034
#define ADV_STOP_REQ_RISC_STOP 0x01
#define ADV_STOP_ACK_RISC_STOP 0x03
#define ADV_STOP_CLEAN_UP_BUSY_Q 0x10
#define ADV_STOP_CLEAN_UP_DISC_Q 0x20
#define ADV_STOP_HOST_REQ_RISC_HALT 0x40
/*
* EEPROM routine constants
* XXX What about wide controllers?
* Surely they have space for 8 more targets.
*/
#define ADV_EEPROM_CFG_BEG_VL 2
#define ADV_EEPROM_MAX_ADDR_VL 15
#define ADV_EEPROM_CFG_BEG 32
#define ADV_EEPROM_MAX_ADDR 45
#define ADV_EEPROM_MAX_RETRY 20
struct adv_eeprom_config {
u_int16_t cfg_lsw;
u_int16_t cfg_msw;
u_int8_t init_sdtr;
u_int8_t disc_enable;
u_int8_t use_cmd_qng;
u_int8_t start_motor;
u_int8_t max_total_qng;
u_int8_t max_tag_qng;
u_int8_t bios_scan;
u_int8_t power_up_wait;
u_int8_t no_scam;
u_int8_t scsi_id_dma_speed;
#define EEPROM_SCSI_ID_MASK 0x0F
#define EEPROM_DMA_SPEED_MASK 0xF0
#define EEPROM_DMA_SPEED(ep) \
(((ep).scsi_id_dma_speed & EEPROM_DMA_SPEED_MASK) >> 4)
#define EEPROM_SET_DMA_SPEED(ep, speed) \
(ep).scsi_id_dma_speed &= ~EEPROM_DMA_SPEED_MASK; \
(ep).scsi_id_dma_speed |= \
(((speed) << 4) & EEPROM_DMA_SPEED_MASK)
#define EEPROM_SCSIID(ep) ((ep).scsi_id_dma_speed & EEPROM_SCSI_ID_MASK)
#define EEPROM_SET_SCSIID(ep, id) \
(ep).scsi_id_dma_speed &= ~EEPROM_SCSI_ID_MASK; \
(ep).scsi_id_dma_speed |= ((id) & EEPROM_SCSI_ID_MASK)
u_int8_t sdtr_data[8];
u_int8_t adapter_info[6];
u_int16_t cntl;
u_int16_t chksum;
};
/* Bank 1 */
#define ADV_SEQ_ACCUM 0x0000
#define ADV_QUEUE_ELEMENT_INDEX 0x0001
#define ADV_SEQ_INSTRUCTION_HOLD 0x0002
#define ADV_QUEUE_ELEMENT_POINTER 0x0003
#define ADV_HOST_DATA_FIFO_L 0x0004
#define ADV_HOST_SCSIID 0x0005
#define ADV_HOST_DATA_FIFO_H 0x0006
#define ADV_SCSI_CONTROL 0x0009
#define SC_SEL 0x80
#define SC_BSY 0x40
#define SC_ACK 0x20
#define SC_REQ 0x10
#define SC_ATN 0x08
#define SC_IO 0x04
#define SC_CD 0x02
#define SC_MSG 0x01
#define ADV_SCSIDATL 0x000B
#define ADV_DMA_TRANSFER_CNT 0x000C
#define ADV_DMA_TRANSFER_CNT1 0x000E
/*
* Instruction data and code segment addresses,
* and transaction address translation (queues).
* All addresses refer to on board LRAM.
*/
#define ADV_DATA_SEC_BEG 0x0080
#define ADV_DATA_SEC_END 0x0080
#define ADV_CODE_SEC_BEG 0x0080
#define ADV_CODE_SEC_END 0x0080
#define ADV_QADR_BEG 0x4000
#define ADV_QADR_END 0x7FFF
#define ADV_QLAST_ADR 0x7FC0
#define ADV_QBLK_SIZE 0x40
#define ADV_BIOS_DATA_QBEG 0xF8
#define ADV_MAX_QNO 0xF8
#define ADV_QADR_USED (ADV_MAX_QNO * 64)
#define ADV_QNO_TO_QADDR(q_no) ((ADV_QADR_BEG) + ((u_int16_t)(q_no) << 6))
#define ADV_MIN_ACTIVE_QNO 0x01
#define ADV_QLINK_END 0xFF
#define ADV_MAX_SG_QUEUE 5
#define ADV_SG_LIST_PER_Q 7
#define ADV_MAX_SG_LIST (1 + ((ADV_SG_LIST_PER_Q) * (ADV_MAX_SG_QUEUE)))
#define ADV_MIN_REMAIN_Q 0x02
#define ADV_DEF_MAX_TOTAL_QNG 0xF0
#define ADV_MIN_TAG_Q_PER_DVC 0x04
#define ADV_DEF_TAG_Q_PER_DVC 0x04
#define ADV_MIN_FREE_Q ADV_MIN_REMAIN_Q
#define ADV_MIN_TOTAL_QNG ((ADV_MAX_SG_QUEUE)+(ADV_MIN_FREE_Q))
#define ADV_MAX_TOTAL_QNG 240
#define ADV_MAX_INRAM_TAG_QNG 16
#define ADV_MAX_PCI_INRAM_TOTAL_QNG 20
#define ADV_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
#define ADV_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
#define ADV_DEF_IRQ_NO 10
#define ADV_MAX_IRQ_NO 15
#define ADV_MIN_IRQ_NO 10
#define ADV_SCSIQ_CPY_BEG 4
#define ADV_SCSIQ_SGHD_CPY_BEG 2
/* SCSIQ Microcode representation offsets */
#define ADV_SCSIQ_B_FWD 0
#define ADV_SCSIQ_B_BWD 1
#define ADV_SCSIQ_B_STATUS 2
#define ADV_SCSIQ_B_QNO 3
#define ADV_SCSIQ_B_CNTL 4
#define ADV_SCSIQ_B_SG_QUEUE_CNT 5
#define ADV_SCSIQ_B_LIST_CNT 6
#define ADV_SCSIQ_B_CUR_LIST_CNT 7
#define ADV_SCSIQ_D_DATA_ADDR 8
#define ADV_SCSIQ_D_DATA_CNT 12
#define ADV_SCSIQ_B_SENSE_LEN 20
#define ADV_SCSIQ_DONE_INFO_BEG 22
#define ADV_SCSIQ_D_CINFO_IDX 22
#define ADV_SCSIQ_B_TARGET_IX 26
#define ADV_SCSIQ_B_CDB_LEN 28
#define ADV_SCSIQ_B_TAG_CODE 29
#define ADV_SCSIQ_W_VM_ID 30
#define ADV_SCSIQ_DONE_STATUS 32
#define ADV_SCSIQ_HOST_STATUS 33
#define ADV_SCSIQ_SCSI_STATUS 34
#define ADV_SCSIQ_CDB_BEG 36
#define ADV_SCSIQ_B_FIRST_SG_QK_QP 48
#define ADV_SCSIQ_B_SG_WK_QP 49
#define ADV_SCSIQ_B_SG_WK_IX 50
#define ADV_SCSIQ_W_ALT_DC1 52
#define ADV_SCSIQ_DW_REMAIN_XFER_ADDR 56
#define ADV_SCSIQ_DW_REMAIN_XFER_CNT 60
/* LRAM Offsets */
#define ADVV_MSGOUT_BEG 0x0000
#define ADVV_MSGOUT_SDTR_PERIOD (ADVV_MSGOUT_BEG+3)
#define ADVV_MSGOUT_SDTR_OFFSET (ADVV_MSGOUT_BEG+4)
#define ADVV_BREAK_SAVED_CODE 0x0006
#define ADVV_MSGIN_BEG (ADVV_MSGOUT_BEG+8)
#define ADVV_MSGIN_SDTR_PERIOD (ADVV_MSGIN_BEG+3)
#define ADVV_MSGIN_SDTR_OFFSET (ADVV_MSGIN_BEG+4)
#define ADVV_SDTR_DATA_BEG (ADVV_MSGIN_BEG+8)
#define ADVV_SDTR_DONE_BEG (ADVV_SDTR_DATA_BEG+8)
#define ADVV_MAX_DVC_QNG_BEG 0x0020
#define ADVV_BREAK_ADDR 0x0028
#define ADVV_BREAK_NOTIFY_COUNT 0x002A
#define ADVV_BREAK_CONTROL 0x002C
#define ADVV_BREAK_HIT_COUNT 0x002E
#define ADVV_ASCDVC_ERR_CODE_W 0x0030
#define ADVV_MCODE_CHKSUM_W 0x0032
#define ADVV_MCODE_SIZE_W 0x0034
#define ADVV_STOP_CODE_B 0x0036
#define ADVV_DVC_ERR_CODE_B 0x0037
#define ADVV_OVERRUN_PADDR_D 0x0038
#define ADVV_OVERRUN_BSIZE_D 0x003C
#define ADVV_HALTCODE_W 0x0040
#define ADV_HALT_EXTMSG_IN 0x8000
#define ADV_HALT_CHK_CONDITION 0x8100
#define ADV_HALT_SS_QUEUE_FULL 0x8200
#define ADV_HALT_DISABLE_ASYN_USE_SYN_FIX 0x8300
#define ADV_HALT_ENABLE_ASYN_USE_SYN_FIX 0x8400
#define ADV_HALT_SDTR_REJECTED 0x4000
#define ADV_HALT_HOST_COPY_SG_LIST_TO_RISC 0x2000
#define ADVV_CHKSUM_W 0x0042
#define ADVV_MC_DATE_W 0x0044
#define ADVV_MC_VER_W 0x0046
#define ADVV_NEXTRDY_B 0x0048
#define ADVV_DONENEXT_B 0x0049
#define ADVV_USE_TAGGED_QNG_B 0x004A
#define ADVV_SCSIBUSY_B 0x004B
#define ADVV_Q_DONE_IN_PROGRESS_B 0x004C
#define ADVV_CURCDB_B 0x004D
#define ADVV_RCLUN_B 0x004E
#define ADVV_BUSY_QHEAD_B 0x004F
#define ADVV_DISC1_QHEAD_B 0x0050
#define ADVV_DISC_ENABLE_B 0x0052
#define ADVV_CAN_TAGGED_QNG_B 0x0053
#define ADVV_HOSTSCSI_ID_B 0x0055
#define ADVV_MCODE_CNTL_B 0x0056
#define ADVV_NULL_TARGET_B 0x0057
#define ADVV_FREE_Q_HEAD_W 0x0058
#define ADVV_DONE_Q_TAIL_W 0x005A
#define ADVV_FREE_Q_HEAD_B (ADVV_FREE_Q_HEAD_W+1)
#define ADVV_DONE_Q_TAIL_B (ADVV_DONE_Q_TAIL_W+1)
#define ADVV_HOST_FLAG_B 0x005D
#define ADV_HOST_FLAG_IN_ISR 0x01
#define ADV_HOST_FLAG_ACK_INT 0x02
#define ADVV_TOTAL_READY_Q_B 0x0064
#define ADVV_VER_SERIAL_B 0x0065
#define ADVV_HALTCODE_SAVED_W 0x0066
#define ADVV_WTM_FLAG_B 0x0068
#define ADVV_RISC_FLAG_B 0x006A
#define ADV_RISC_FLAG_GEN_INT 0x01
#define ADV_RISC_FLAG_REQ_SG_LIST 0x02
#define ADVV_REQ_SG_LIST_QP 0x006B
#define ADV_TRANS_CUR 0x01 /* Modify current neogtiation status */
#define ADV_TRANS_ACTIVE 0x03 /* Assume this is the active target */
#define ADV_TRANS_GOAL 0x04 /* Modify negotiation goal */
#define ADV_TRANS_USER 0x08 /* Modify user negotiation settings */
struct adv_transinfo {
u_int8_t period;
u_int8_t offset;
};
struct adv_target_transinfo {
struct adv_transinfo current;
struct adv_transinfo goal;
struct adv_transinfo user;
};
struct adv_softc {
device_t dev;
struct resource *res;
long reg_off;
struct cam_sim *sim;
LIST_HEAD(, ccb_hdr) pending_ccbs;
struct adv_ccb_info *ccb_infos;
SLIST_HEAD(, adv_ccb_info) free_ccb_infos;
bus_dma_tag_t parent_dmat;
bus_dma_tag_t buffer_dmat;
bus_dma_tag_t sense_dmat;
bus_dmamap_t sense_dmamap;
struct scsi_sense_data *sense_buffers;
bus_addr_t sense_physbase;
bus_addr_t overrun_physbase;
adv_btype type;
struct adv_target_transinfo tinfo[8];
target_bit_vector fix_asyn_xfer;
target_bit_vector fix_asyn_xfer_always;
target_bit_vector disc_enable;
target_bit_vector user_disc_enable;
target_bit_vector cmd_qng_enabled;
target_bit_vector user_cmd_qng_enabled;
u_int16_t control;
#define ADV_CNTL_INITIATOR 0x0001
#define ADV_CNTL_BIOS_GT_1GB 0x0002
#define ADV_CNTL_BIOS_GT_2_DISK 0x0004
#define ADV_CNTL_BIOS_REMOVABLE 0x0008
#define ADV_CNTL_NO_SCAM 0x0010
#define ADV_CNTL_INT_MULTI_Q 0x0080
#define ADV_CNTL_NO_LUN_SUPPORT 0x0040
#define ADV_CNTL_NO_VERIFY_COPY 0x0100
#define ADV_CNTL_RESET_SCSI 0x0200
#define ADV_CNTL_INIT_INQUIRY 0x0400
#define ADV_CNTL_INIT_VERBOSE 0x0800
#define ADV_CNTL_SCSI_PARITY 0x1000
#define ADV_CNTL_BURST_MODE 0x2000
#define ADV_CNTL_SDTR_ENABLE_ULTRA 0x4000
u_int16_t bug_fix_control;
#define ADV_BUG_FIX_IF_NOT_DWB 0x0001
#define ADV_BUG_FIX_ASYN_USE_SYN 0x0002
adv_state state;
struct cam_path *path;
int init_level;
u_int32_t max_dma_addr;
u_int32_t max_dma_count;
u_int8_t isa_dma_speed;
u_int8_t isa_dma_channel;
u_int8_t scsi_id;
u_int8_t chip_version;
u_int8_t max_tags_per_target;
u_int8_t max_openings;
u_int8_t cur_active;
u_int8_t openings_needed;
u_int8_t ccb_infos_allocated;
u_int8_t *sdtr_period_tbl;
u_int8_t sdtr_period_tbl_size;
struct mtx lock;
};
/*
* Structures for talking to the RISC engine.
*/
struct adv_scsiq_1 {
u_int8_t status;
#define QS_FREE 0x00
#define QS_READY 0x01
#define QS_DISC1 0x02
#define QS_DISC2 0x04
#define QS_BUSY 0x08
#define QS_ABORTED 0x40
#define QS_DONE 0x80
u_int8_t q_no; /*
* Queue ID of the first queue
* used in this transaction.
*/
u_int8_t cntl;
#define QC_NO_CALLBACK 0x01
#define QC_SG_SWAP_QUEUE 0x02
#define QC_SG_HEAD 0x04
#define QC_DATA_IN 0x08
#define QC_DATA_OUT 0x10
#define QC_URGENT 0x20
#define QC_MSG_OUT 0x40
#define QC_REQ_SENSE 0x80
u_int8_t sg_queue_cnt; /* Number of SG entries */
u_int8_t target_id; /* target id as a bit vector */
u_int8_t target_lun; /* LUN - taken from our xs */
u_int32_t data_addr; /*
* physical address of first
* (possibly only) segment
* to transfer.
*/
u_int32_t data_cnt; /*
* byte count of the first
* (possibly only) segment
* to transfer.
*/
u_int32_t sense_addr; /*
* physical address of the sense
* buffer.
*/
u_int8_t sense_len; /* length of sense buffer */
u_int8_t extra_bytes;
};
struct adv_scsiq_2 {
u_int32_t ccb_index; /* Index to our CCB Info */
u_int8_t target_ix; /* Combined TID and LUN */
u_int8_t flag;
u_int8_t cdb_len; /*
* Number of bytes in the SCSI
* command to execute.
*/
u_int8_t tag_code; /*
* Tag type for this transaction
* (SIMPLE, ORDERED, HEAD )
*/
#define ADV_TAG_FLAG_EXTRA_BYTES 0x10
#define ADV_TAG_FLAG_DISABLE_DISCONNECT 0x04
#define ADV_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
#define ADV_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
u_int16_t vm_id;
};
struct adv_scsiq_3 {
u_int8_t done_stat;
#define QD_IN_PROGRESS 0x00
#define QD_NO_ERROR 0x01
#define QD_ABORTED_BY_HOST 0x02
#define QD_WITH_ERROR 0x04
#define QD_INVALID_REQUEST 0x80
#define QD_INVALID_HOST_NUM 0x81
#define QD_INVALID_DEVICE 0x82
#define QD_ERR_INTERNAL 0xFF
u_int8_t host_stat;
#define QHSTA_NO_ERROR 0x00
#define QHSTA_M_SEL_TIMEOUT 0x11
#define QHSTA_M_DATA_OVER_RUN 0x12
#define QHSTA_M_DATA_UNDER_RUN 0x12
#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
#define QHSTA_D_HOST_ABORT_FAILED 0x23
#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
#define QHSTA_M_WTM_TIMEOUT 0x41
#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
#define QHSTA_M_TARGET_STATUS_BUSY 0x45
#define QHSTA_M_BAD_TAG_CODE 0x46
#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
#define QHSTA_D_LRAM_CMP_ERROR 0x81
#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
u_int8_t scsi_stat;
u_int8_t scsi_msg;
};
struct adv_scsiq_4 {
u_int8_t cdb[ADV_MAX_CDB_LEN];
u_int8_t y_first_sg_list_qp;
u_int8_t y_working_sg_qp;
u_int8_t y_working_sg_ix;
u_int8_t y_res;
u_int16_t x_req_count;
u_int16_t x_reconnect_rtn;
u_int32_t x_saved_data_addr;
u_int32_t x_saved_data_cnt;
};
struct adv_q_done_info {
struct adv_scsiq_2 d2;
struct adv_scsiq_3 d3;
u_int8_t q_status;
u_int8_t q_no;
u_int8_t cntl;
u_int8_t sense_len;
u_int8_t extra_bytes;
u_int8_t res;
u_int32_t remain_bytes;
};
struct adv_sg_entry {
u_int32_t addr;
u_int32_t bytes;
};
struct adv_sg_head {
u_int16_t entry_cnt; /*
* Number of SG entries
* in this list
*/
u_int16_t queue_cnt; /*
* Number of queues required
* to store entry_cnt
* SG entries.
*/
u_int16_t entry_to_copy; /*
* Number of SG entries to
* copy to the board.
*/
u_int16_t res;
struct adv_sg_entry *sg_list;
};
#define QCX_SORT (0x0001)
#define QCX_COALEASE (0x0002)
struct adv_scsi_q {
struct adv_scsiq_1 q1;
struct adv_scsiq_2 q2;
u_int8_t *cdbptr; /*
* Pointer to the SCSI command
* to execute.
*/
struct adv_sg_head *sg_head; /*
* Pointer to possible SG list
*/
};
struct adv_scsi_req_q {
struct adv_scsiq_1 r1;
struct adv_scsiq_2 r2;
u_int8_t *cdbptr;
struct adv_sg_head *sg_head;
u_int8_t *sense_ptr;
struct adv_scsiq_3 r3;
u_int8_t cdb[ADV_MAX_CDB_LEN];
u_int8_t sense[ADV_MIN_SENSE_LEN];
};
struct adv_risc_q {
u_int8_t fwd;
u_int8_t bwd;
struct adv_scsiq_1 i1;
struct adv_scsiq_2 i2;
struct adv_scsiq_3 i3;
struct adv_scsiq_4 i4;
};
struct adv_sg_list_q {
u_int8_t seq_no;
u_int8_t q_no;
u_int8_t cntl;
#define QCSG_SG_XFER_LIST 0x02
#define QCSG_SG_XFER_MORE 0x04
#define QCSG_SG_XFER_END 0x08
u_int8_t sg_head_qp;
u_int8_t sg_list_cnt;
u_int8_t sg_cur_list_cnt;
};
#define ADV_SGQ_B_SG_CNTL 4
#define ADV_SGQ_B_SG_HEAD_QP 5
#define ADV_SGQ_B_SG_LIST_CNT 6
#define ADV_SGQ_B_SG_CUR_LIST_CNT 7
#define ADV_SGQ_LIST_BEG 8
struct asc_risc_sg_list_q {
u_int8_t fwd;
u_int8_t bwd;
struct adv_sg_list_q sg;
struct adv_sg_entry sg_list[ADV_SG_LIST_PER_Q];
};
/* Chip Register functions */
void adv_set_bank(struct adv_softc *adv, u_int8_t bank);
/* LRAM routines */
u_int8_t adv_read_lram_8(struct adv_softc *adv, u_int16_t addr);
void adv_write_lram_8(struct adv_softc *adv, u_int16_t addr,
u_int8_t value);
u_int16_t adv_read_lram_16(struct adv_softc *adv, u_int16_t addr);
void adv_write_lram_16(struct adv_softc *adv, u_int16_t addr,
u_int16_t value);
/* Initialization */
int adv_find_signature(struct resource *res);
void adv_lib_init(struct adv_softc *adv);
u_int16_t adv_get_eeprom_config(struct adv_softc *adv,
struct adv_eeprom_config *eeprom_config);
int adv_set_eeprom_config(struct adv_softc *adv,
struct adv_eeprom_config *eeprom_config);
int adv_reset_chip(struct adv_softc *adv, int reset_bus);
int adv_test_external_lram(struct adv_softc* adv);
int adv_init_lram_and_mcode(struct adv_softc *adv);
u_int8_t adv_get_chip_irq(struct adv_softc *adv);
u_int8_t adv_set_chip_irq(struct adv_softc *adv, u_int8_t irq_no);
void adv_set_chip_scsiid(struct adv_softc *adv, int new_id);
/* Queue handling and execution */
int adv_execute_scsi_queue(struct adv_softc *adv,
struct adv_scsi_q *scsiq,
u_int32_t datalen);
u_int8_t adv_copy_lram_doneq(struct adv_softc *adv, u_int16_t q_addr,
struct adv_q_done_info *scsiq, u_int32_t max_dma_count);
/* Chip Control */
int adv_start_chip(struct adv_softc *adv);
void adv_start_execution(struct adv_softc *adv);
int adv_stop_execution(struct adv_softc *adv);
int adv_stop_chip(struct adv_softc *adv);
int adv_is_chip_halted(struct adv_softc *adv);
/* Interrupt processing */
void adv_ack_interrupt(struct adv_softc *adv);
void adv_isr_chip_halted(struct adv_softc *adv);
/* SDTR Conversion */
void adv_set_syncrate(struct adv_softc *adv, struct cam_path *path,
u_int target_id, u_int period, u_int offset,
u_int type);
void adv_sdtr_to_period_offset(struct adv_softc *adv,
u_int8_t sync_data, u_int8_t *period,
u_int8_t *offset, int tid);
u_int8_t adv_period_offset_to_sdtr(struct adv_softc *adv, u_int *period,
u_int *offset, int tid);
/* Error recovery */
union ccb;
int adv_abort_ccb(struct adv_softc *adv, int target, int lun,
union ccb *ccb, u_int32_t status, int queued_only);
int adv_reset_bus(struct adv_softc *adv, int initiate_reset);
/* Async event callback */
void advasync(void *callback_arg, u_int32_t code,
struct cam_path *path, void *arg);
#define ADV_INB(adv, offset) \
bus_read_1((adv)->res, (adv)->reg_off + offset)
#define ADV_INW(adv, offset) \
bus_read_2((adv)->res, (adv)->reg_off + offset)
#define ADV_INSB(adv, offset, valp, count) \
bus_read_multi_1((adv)->res, (adv)->reg_off + offset, valp, count)
/* These controllers seem to have problems with PIO on some fast processors */
static __inline void ADV_INSW(struct adv_softc *, u_int, u_int16_t *, u_int);
static __inline void
ADV_INSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
{
while (count--)
*valp++ = bus_read_2(adv->res, adv->reg_off + offset);
}
#define ADV_OUTB(adv, offset, val) \
bus_write_1((adv)->res, (adv)->reg_off + offset, val)
#define ADV_OUTW(adv, offset, val) \
bus_write_2((adv)->res, (adv)->reg_off + offset, val)
/* These controllers seem to have problems with PIO on some fast processors */
static __inline void ADV_OUTSW(struct adv_softc *, u_int, u_int16_t *, u_int);
static __inline void
ADV_OUTSW(struct adv_softc *adv, u_int offset, u_int16_t *valp, u_int count)
{
while (count--)
bus_write_2(adv->res, adv->reg_off + offset, *valp++);
}
#endif /* _ADVLIB_H_ */

283
sys/dev/advansys/advmcode.c
View File

@ -1,283 +0,0 @@
/*-
* Downloadable microcode for Advanced Systems Inc. SCSI controllers
*
*
* Obtained from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1999 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
u_int8_t adv_mcode[] =
{
0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F,
0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05,
0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF,
0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00,
0x00, 0x00, 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00,
0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12,
0xDA, 0x00, 0xA2, 0xC2, 0x00, 0x92, 0x80, 0x1E, 0x98,
0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36,
0x60, 0xB6, 0x00, 0x92, 0x80, 0x4F, 0x00, 0xF5, 0x00,
0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92,
0x80, 0x80, 0x62, 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE,
0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, 0xCD, 0x04, 0x4D,
0x00, 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23,
0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1, 0x80,
0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01,
0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88, 0x80, 0x73, 0x80,
0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00,
0x84, 0x97, 0x07, 0xA6, 0x08, 0x01, 0x00, 0x33, 0x03,
0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88,
0xCE, 0x00, 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A,
0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2,
0x00, 0x07, 0xA6, 0x34, 0x01, 0x00, 0x33, 0x04, 0x00,
0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D,
0x23, 0x68, 0x98, 0x4D, 0x04, 0x04, 0x85, 0x05, 0xD8,
0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8,
0x88, 0xFB, 0x23, 0x02, 0x61, 0x82, 0x01, 0x80, 0x63,
0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, 0x00, 0x33, 0x0A,
0x00, 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01,
0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04, 0x36,
0x2D, 0x00, 0x33, 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04,
0x88, 0x81, 0x06, 0xAB, 0x82, 0x01, 0x88, 0x81, 0x4E,
0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3,
0x3C, 0x01, 0x00, 0x05, 0x7C, 0x81, 0x46, 0x97, 0x02,
0x01, 0x05, 0xC6, 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23,
0xA1, 0x01, 0xBE, 0x81, 0xFD, 0x23, 0x02, 0x61, 0x82,
0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00,
0x33, 0x1B, 0x00, 0xC2, 0x88, 0x06, 0x23, 0x68, 0x98,
0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4,
0x01, 0x57, 0x60, 0x00, 0xA0, 0xDA, 0x01, 0xE6, 0x84,
0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B,
0x00, 0x06, 0x61, 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01,
0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, 0x4F, 0x00, 0x84,
0x97, 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01,
0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80, 0xF0,
0x97, 0x00, 0x46, 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23,
0xE8, 0x00, 0x81, 0x73, 0x06, 0x29, 0x03, 0x42, 0x06,
0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88,
0x04, 0x98, 0xF0, 0x80, 0x80, 0x73, 0x80, 0x77, 0x07,
0xA4, 0x2A, 0x02, 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02,
0x03, 0xA6, 0x4C, 0x04, 0x46, 0x82, 0x04, 0x01, 0x03,
0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02,
0xA6, 0x6C, 0x02, 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6,
0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, 0xC2, 0x88, 0x7C,
0x95, 0x48, 0x82, 0x60, 0x96, 0x48, 0x82, 0x04, 0x23,
0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04,
0x01, 0x0C, 0xDC, 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00,
0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, 0x6F, 0x00, 0xA5,
0x01, 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01,
0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02, 0x07,
0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6,
0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02, 0x00, 0xA6, 0xB4,
0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E,
0x80, 0x63, 0x00, 0x43, 0x00, 0xA0, 0x8C, 0x02, 0x4D,
0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61,
0x84, 0x01, 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC,
0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04,
0x01, 0xA2, 0xC8, 0x00, 0x33, 0x1F, 0x00, 0xC2, 0x88,
0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E,
0x98, 0xB6, 0x2D, 0x01, 0xA6, 0x14, 0x03, 0x00, 0xA6,
0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10,
0x03, 0x03, 0xA6, 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02,
0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xEE,
0x82, 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42,
0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8, 0x31,
0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43,
0x87, 0x01, 0x05, 0x05, 0x86, 0x98, 0x7E, 0x98, 0x00,
0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6,
0x3C, 0x04, 0x06, 0xA6, 0x50, 0x03, 0x01, 0xA6, 0x16,
0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95,
0x32, 0x83, 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10,
0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00,
0x01, 0x05, 0x05, 0xFF, 0xA2, 0x7A, 0x03, 0xB1, 0x01,
0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15,
0x01, 0x00, 0xA2, 0x9A, 0x03, 0xEC, 0x00, 0x6E, 0x00,
0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01,
0xA6, 0x96, 0x03, 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84,
0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, 0xA4, 0x03, 0x00,
0xA6, 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42,
0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03, 0xD4,
0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00,
0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42, 0x00, 0xA6, 0xBC,
0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95,
0xC0, 0x83, 0x00, 0x33, 0x26, 0x00, 0xC2, 0x88, 0x38,
0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01,
0x12, 0x23, 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06,
0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07,
0xA6, 0x06, 0x04, 0x06, 0xA6, 0x0A, 0x04, 0x00, 0x33,
0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xF4, 0x83, 0x60,
0x96, 0xF4, 0x83, 0x20, 0x84, 0x07, 0xF0, 0x06, 0xA4,
0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83,
0x03, 0x80, 0x63, 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04,
0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, 0x38, 0x04, 0x00,
0x33, 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84,
0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC, 0x00,
0x33, 0x00, 0x84, 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00,
0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63, 0x07, 0xA6, 0x5A,
0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03,
0x80, 0x63, 0xA3, 0x01, 0x07, 0xA4, 0x64, 0x04, 0x23,
0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04,
0xE0, 0x00, 0x00, 0x33, 0x1D, 0x00, 0xC2, 0x88, 0x0B,
0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22,
0xA3, 0xE6, 0x04, 0x08, 0x23, 0x22, 0xA3, 0xA2, 0x04,
0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22,
0xA3, 0xC4, 0x04, 0x42, 0x23, 0xF8, 0x88, 0x4A, 0x00,
0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8,
0x88, 0x04, 0x98, 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98,
0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, 0x81, 0x62, 0xE8,
0x81, 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE,
0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81, 0xC0,
0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02,
0x43, 0x23, 0xF8, 0x88, 0x04, 0x23, 0xA0, 0x01, 0x44,
0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3,
0xF4, 0x04, 0x00, 0x33, 0x27, 0x00, 0xC2, 0x88, 0x04,
0x01, 0x04, 0xDC, 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23,
0xA0, 0x01, 0x04, 0x98, 0x26, 0x95, 0x4B, 0x00, 0xF6,
0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C,
0x05, 0x0A, 0x85, 0x46, 0x97, 0xCD, 0x04, 0x24, 0x85,
0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80,
0x23, 0x82, 0x01, 0x34, 0x85, 0x02, 0x23, 0xA0, 0x01,
0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D,
0x01, 0x04, 0xD6, 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60,
0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x49, 0x00, 0x81,
0x01, 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01,
0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01, 0xC9,
0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05,
0x77, 0x04, 0x01, 0x23, 0xEA, 0x00, 0x5D, 0x00, 0xFE,
0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63,
0x07, 0xA4, 0xF8, 0x05, 0x03, 0x03, 0x02, 0xA0, 0x8E,
0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88,
0x04, 0xA0, 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF,
0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82,
0x01, 0x50, 0x00, 0x62, 0x97, 0x04, 0x85, 0x04, 0x23,
0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE,
0x05, 0xF4, 0x85, 0x03, 0xA0, 0xC4, 0x05, 0xF4, 0x85,
0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC,
0x86, 0x07, 0xA0, 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B,
0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, 0x80, 0x67, 0x80,
0x63, 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23,
0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23, 0x80,
0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23,
0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00, 0x06, 0x61, 0x00,
0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23,
0x07, 0x41, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x1C,
0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01,
0x01, 0xD6, 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80,
0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06,
0x41, 0xCB, 0x00, 0x52, 0x00, 0x06, 0x61, 0x00, 0xA2,
0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07,
0x41, 0x00, 0x63, 0x1D, 0x01, 0x04, 0xCC, 0x00, 0x33,
0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07,
0x41, 0x00, 0x63, 0x80, 0x67, 0x08, 0x23, 0x83, 0x03,
0x80, 0x63, 0x00, 0x63, 0x01, 0x23, 0xDF, 0x00, 0x06,
0xA6, 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67,
0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20, 0x81,
0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03,
0x80, 0x63, 0x06, 0xA6, 0x94, 0x06, 0x07, 0xA6, 0x7C,
0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B,
0x40, 0x0E, 0x80, 0x63, 0x01, 0x00, 0x06, 0xA6, 0xAA,
0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63,
0x00, 0x43, 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC,
0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF,
0x00, 0x00, 0x63, 0x07, 0xA6, 0xD6, 0x06, 0x00, 0x33,
0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89,
0x00, 0x0A, 0x2B, 0x07, 0xA6, 0xE8, 0x06, 0x00, 0x33,
0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4,
0x06, 0xC0, 0x0E, 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E,
0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, 0x81, 0x62, 0x04,
0x01, 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B,
0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33, 0x2C,
0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95,
0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x2C, 0x07, 0x07,
0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88,
0x00, 0x00, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x0C,
0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23,
0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0,
0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81,
0x01, 0x70, 0x04, 0x80, 0x05, 0x81, 0x05, 0x00, 0x63,
0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1,
0x00, 0x70, 0x00, 0x81, 0x01, 0x70, 0x04, 0x71, 0x00,
0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70,
0x00, 0x80, 0x01, 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04,
0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, 0xF1, 0x00, 0x70,
0x00, 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01,
0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00, 0x81,
0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01,
0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01, 0xA1, 0x01, 0x01,
0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1,
0xC4, 0x07, 0x00, 0x33, 0x07, 0x00, 0xC2, 0x88, 0x80,
0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00,
0xB0, 0x01, 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05,
0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF,
0x23, 0x80, 0x01, 0x05, 0x05, 0x00, 0x63, 0xF7, 0x04,
0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80,
0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63,
0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00,
0x02, 0x00, 0xA0, 0x14, 0x08, 0x16, 0x88, 0x00, 0x43,
0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, 0xF3,
0x04, 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43,
0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08, 0x74,
0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01,
0x01, 0xA1, 0x24, 0x08, 0x04, 0x98, 0x26, 0x95, 0x24,
0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04,
0x5A, 0x88, 0x02, 0x01, 0x04, 0xD8, 0x46, 0x97, 0x04,
0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3,
0x64, 0x08, 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00,
0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83,
0x03, 0x80, 0x63, 0x00, 0x63, 0x38, 0x2B, 0x9C, 0x88,
0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92,
0x98, 0x05, 0x05, 0xB2, 0x09, 0x00, 0x63, 0x00, 0x32,
0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80,
0x32, 0x80, 0x36, 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D,
0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, 0x40, 0x36, 0x40,
0x3A, 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40,
0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3, 0x00,
0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00,
0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73, 0x13, 0x23, 0xF8,
0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01,
0xA1, 0x23, 0xA1, 0x01, 0x81, 0x62, 0xE2, 0x88, 0x80,
0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00,
0x03, 0xC2, 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11,
0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84
};
u_int16_t adv_mcode_size = sizeof(adv_mcode);
u_int32_t adv_mcode_chksum = 0x012C453F;

19
sys/dev/advansys/advmcode.h
View File

@ -1,19 +0,0 @@
/*-
* Exported interface to downloadable microcode for AdvanSys SCSI Adapters
*
* $FreeBSD$
*
* Obtained from:
*
* Copyright (c) 1995-1999 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
extern u_int8_t adv_mcode[];
extern u_int16_t adv_mcode_size;
extern u_int32_t adv_mcode_chksum;

395
sys/dev/advansys/adw_pci.c
View File

@ -1,395 +0,0 @@
/*-
* Device probe and attach routines for the following
* Advanced Systems Inc. SCSI controllers:
*
* ABP[3]940UW - Bus-Master PCI Ultra-Wide (253 CDB)
* ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB/Channel)
* ABP970UW - Bus-Master PCI Ultra-Wide (253 CDB)
* ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
* ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
*
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/bus.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <dev/pci/pcireg.h>
#include <dev/pci/pcivar.h>
#include <cam/cam.h>
#include <cam/scsi/scsi_all.h>
#include <dev/advansys/adwvar.h>
#include <dev/advansys/adwlib.h>
#include <dev/advansys/adwmcode.h>
#define ADW_PCI_IOBASE PCIR_BAR(0) /* I/O Address */
#define ADW_PCI_MEMBASE PCIR_BAR(1) /* Mem I/O Address */
#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
struct adw_pci_identity;
typedef int (adw_device_setup_t)(device_t, struct adw_pci_identity *,
struct adw_softc *adw);
struct adw_pci_identity {
u_int64_t full_id;
u_int64_t id_mask;
char *name;
adw_device_setup_t *setup;
const struct adw_mcode *mcode_data;
const struct adw_eeprom *default_eeprom;
};
static adw_device_setup_t adw_asc3550_setup;
static adw_device_setup_t adw_asc38C0800_setup;
#ifdef NOTYET
static adw_device_setup_t adw_asc38C1600_setup;
#endif
struct adw_pci_identity adw_pci_ident_table[] =
{
/* asc3550 based controllers */
{
PCI_ID_ADVANSYS_3550,
PCI_ID_DEV_VENDOR_MASK,
"AdvanSys 3550 Ultra SCSI Adapter",
adw_asc3550_setup,
&adw_asc3550_mcode_data,
&adw_asc3550_default_eeprom
},
/* asc38C0800 based controllers */
{
PCI_ID_ADVANSYS_38C0800_REV1,
PCI_ID_DEV_VENDOR_MASK,
"AdvanSys 38C0800 Ultra2 SCSI Adapter",
adw_asc38C0800_setup,
&adw_asc38C0800_mcode_data,
&adw_asc38C0800_default_eeprom
},
#ifdef NOTYET
/* XXX Disabled until I have hardware to test with */
/* asc38C1600 based controllers */
{
PCI_ID_ADVANSYS_38C1600_REV1,
PCI_ID_DEV_VENDOR_MASK,
"AdvanSys 38C1600 Ultra160 SCSI Adapter",
adw_asc38C1600_setup,
NULL, /* None provided by vendor thus far */
NULL /* None provided by vendor thus far */
}
#endif
};
#define ADW_PCI_MAX_DMA_ADDR (0xFFFFFFFFUL)
#define ADW_PCI_MAX_DMA_COUNT (0xFFFFFFFFUL)
static int adw_pci_probe(device_t dev);
static int adw_pci_attach(device_t dev);
static device_method_t adw_pci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, adw_pci_probe),
DEVMETHOD(device_attach, adw_pci_attach),
{ 0, 0 }
};
static driver_t adw_pci_driver = {
"adw",
adw_pci_methods,
sizeof(struct adw_softc)
};
static devclass_t adw_devclass;
DRIVER_MODULE(adw, pci, adw_pci_driver, adw_devclass, 0, 0);
MODULE_DEPEND(adw, pci, 1, 1, 1);
static __inline u_int64_t
adw_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
{
u_int64_t id;
id = subvendor
| (subdevice << 16)
| ((u_int64_t)vendor << 32)
| ((u_int64_t)device << 48);
return (id);
}
static struct adw_pci_identity *
adw_find_pci_device(device_t dev)
{
u_int64_t full_id;
struct adw_pci_identity *entry;
u_int i;
full_id = adw_compose_id(pci_get_device(dev),
pci_get_vendor(dev),
pci_get_subdevice(dev),
pci_get_subvendor(dev));
for (i = 0; i < nitems(adw_pci_ident_table); i++) {
entry = &adw_pci_ident_table[i];
if (entry->full_id == (full_id & entry->id_mask))
return (entry);
}
return (NULL);
}
static int
adw_pci_probe(device_t dev)
{
struct adw_pci_identity *entry;
entry = adw_find_pci_device(dev);
if (entry != NULL) {
device_set_desc(dev, entry->name);
return (BUS_PROBE_DEFAULT);
}
return (ENXIO);
}
static int
adw_pci_attach(device_t dev)
{
struct adw_softc *adw;
struct adw_pci_identity *entry;
u_int16_t command;
struct resource *regs;
int regs_type;
int regs_id;
int error;
int zero;
entry = adw_find_pci_device(dev);
if (entry == NULL)
return (ENXIO);
regs = NULL;
regs_type = 0;
regs_id = 0;
#ifdef ADW_ALLOW_MEMIO
regs_type = SYS_RES_MEMORY;
regs_id = ADW_PCI_MEMBASE;
regs = bus_alloc_resource_any(dev, regs_type, &regs_id, RF_ACTIVE);
#endif
if (regs == NULL) {
regs_type = SYS_RES_IOPORT;
regs_id = ADW_PCI_IOBASE;
regs = bus_alloc_resource_any(dev, regs_type,
&regs_id, RF_ACTIVE);
}
if (regs == NULL) {
device_printf(dev, "can't allocate register resources\n");
return (ENOMEM);
}
adw = adw_alloc(dev, regs, regs_type, regs_id);
if (adw == NULL)
return(ENOMEM);
/*
* Now that we have access to our registers, just verify that
* this really is an AdvanSys device.
*/
if (adw_find_signature(adw) == 0) {
adw_free(adw);
return (ENXIO);
}
adw_reset_chip(adw);
error = entry->setup(dev, entry, adw);
if (error != 0)
return (error);
/* Ensure busmastering is enabled */
pci_enable_busmaster(dev);
/* Allocate a dmatag for our transfer DMA maps */
error = bus_dma_tag_create(
/* parent */ bus_get_dma_tag(dev),
/* alignment */ 1,
/* boundary */ 0,
/* lowaddr */ ADW_PCI_MAX_DMA_ADDR,
/* highaddr */ BUS_SPACE_MAXADDR,
/* filter */ NULL,
/* filterarg */ NULL,
/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
/* nsegments */ ~0,
/* maxsegsz */ ADW_PCI_MAX_DMA_COUNT,
/* flags */ 0,
/* lockfunc */ NULL,
/* lockarg */ NULL,
&adw->parent_dmat);
adw->init_level++;
if (error != 0) {
device_printf(dev, "Could not allocate DMA tag - error %d\n",
error);
adw_free(adw);
return (error);
}
adw->init_level++;
error = adw_init(adw);
if (error != 0) {
adw_free(adw);
return (error);
}
/*
* If the PCI Configuration Command Register "Parity Error Response
* Control" Bit was clear (0), then set the microcode variable
* 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
* to ignore DMA parity errors.
*/
command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/2);
if ((command & PCIM_CMD_PERRESPEN) == 0)
adw_lram_write_16(adw, ADW_MC_CONTROL_FLAG,
adw_lram_read_16(adw, ADW_MC_CONTROL_FLAG)
| ADW_MC_CONTROL_IGN_PERR);
zero = 0;
adw->irq_res_type = SYS_RES_IRQ;
adw->irq = bus_alloc_resource_any(dev, adw->irq_res_type, &zero,
RF_ACTIVE | RF_SHAREABLE);
if (adw->irq == NULL) {
adw_free(adw);
return (ENOMEM);
}
error = adw_attach(adw);
if (error != 0)
adw_free(adw);
return (error);
}
static int
adw_generic_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
adw->channel = pci_get_function(dev) == 1 ? 'B' : 'A';
adw->chip = ADW_CHIP_NONE;
adw->features = ADW_FENONE;
adw->flags = ADW_FNONE;
adw->mcode_data = entry->mcode_data;
adw->default_eeprom = entry->default_eeprom;
return (0);
}
static int
adw_asc3550_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
int error;
error = adw_generic_setup(dev, entry, adw);
if (error != 0)
return (error);
adw->chip = ADW_CHIP_ASC3550;
adw->features = ADW_ASC3550_FE;
adw->memsize = ADW_3550_MEMSIZE;
/*
* For ASC-3550, setting the START_CTL_EMFU [3:2] bits
* sets a FIFO threshold of 128 bytes. This register is
* only accessible to the host.
*/
adw_outb(adw, ADW_DMA_CFG0,
ADW_DMA_CFG0_START_CTL_EM_FU|ADW_DMA_CFG0_READ_CMD_MRM);
adw_outb(adw, ADW_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_8KB);
return (0);
}
static int
adw_asc38C0800_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
int error;
error = adw_generic_setup(dev, entry, adw);
if (error != 0)
return (error);
/*
* For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and
* START_CTL_TH [3:2] bits for the default FIFO threshold.
*
* Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
*
* For DMA Errata #4 set the BC_THRESH_ENB bit.
*/
adw_outb(adw, ADW_DMA_CFG0,
ADW_DMA_CFG0_BC_THRESH_ENB|ADW_DMA_CFG0_FIFO_THRESH_80B
|ADW_DMA_CFG0_START_CTL_TH|ADW_DMA_CFG0_READ_CMD_MRM);
adw_outb(adw, ADW_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) | ADW_MEM_CFG_RAM_SZ_16KB);
adw->chip = ADW_CHIP_ASC38C0800;
adw->features = ADW_ASC38C0800_FE;
adw->memsize = ADW_38C0800_MEMSIZE;
return (error);
}
#ifdef NOTYET
static int
adw_asc38C1600_setup(device_t dev, struct adw_pci_identity *entry,
struct adw_softc *adw)
{
int error;
error = adw_generic_setup(dev, entry, adw);
if (error != 0)
return (error);
adw->chip = ADW_CHIP_ASC38C1600;
adw->features = ADW_ASC38C1600_FE;
adw->memsize = ADW_38C1600_MEMSIZE;
return (error);
}
#endif

1507
sys/dev/advansys/adwcam.c
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File diff suppressed because it is too large Load Diff

899
sys/dev/advansys/adwlib.c
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@ -1,899 +0,0 @@
/*-
* Low level routines for Second Generation
* Advanced Systems Inc. SCSI controllers chips
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*-
* Ported from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/conf.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <machine/bus.h>
#include <cam/cam.h>
#include <cam/cam_ccb.h>
#include <cam/cam_sim.h>
#include <cam/cam_xpt_sim.h>
#include <cam/scsi/scsi_all.h>
#include <dev/advansys/adwlib.h>
const struct adw_eeprom adw_asc3550_default_eeprom =
{
ADW_EEPROM_BIOS_ENABLE, /* cfg_lsw */
0x0000, /* cfg_msw */
0xFFFF, /* disc_enable */
0xFFFF, /* wdtr_able */
{ 0xFFFF }, /* sdtr_able */
0xFFFF, /* start_motor */
0xFFFF, /* tagqng_able */
0xFFFF, /* bios_scan */
0, /* scam_tolerant */
7, /* adapter_scsi_id */
0, /* bios_boot_delay */
3, /* scsi_reset_delay */
0, /* bios_id_lun */
0, /* termination */
0, /* reserved1 */
0xFFE7, /* bios_ctrl */
{ 0xFFFF }, /* ultra_able */
{ 0 }, /* reserved2 */
ADW_DEF_MAX_HOST_QNG, /* max_host_qng */
ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
0, /* dvc_cntl */
{ 0 }, /* bug_fix */
{ 0, 0, 0 }, /* serial_number */
0, /* check_sum */
{ /* oem_name[16] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
},
0, /* dvc_err_code */
0, /* adv_err_code */
0, /* adv_err_addr */
0, /* saved_dvc_err_code */
0, /* saved_adv_err_code */
0 /* saved_adv_err_addr */
};
const struct adw_eeprom adw_asc38C0800_default_eeprom =
{
ADW_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
0x0000, /* 01 cfg_msw */
0xFFFF, /* 02 disc_enable */
0xFFFF, /* 03 wdtr_able */
{ 0x4444 }, /* 04 sdtr_speed1 */
0xFFFF, /* 05 start_motor */
0xFFFF, /* 06 tagqng_able */
0xFFFF, /* 07 bios_scan */
0, /* 08 scam_tolerant */
7, /* 09 adapter_scsi_id */
0, /* bios_boot_delay */
3, /* 10 scsi_reset_delay */
0, /* bios_id_lun */
0, /* 11 termination_se */
0, /* termination_lvd */
0xFFE7, /* 12 bios_ctrl */
{ 0x4444 }, /* 13 sdtr_speed2 */
{ 0x4444 }, /* 14 sdtr_speed3 */
ADW_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
ADW_DEF_MAX_DVC_QNG, /* max_dvc_qng */
0, /* 16 dvc_cntl */
{ 0x4444 } , /* 17 sdtr_speed4 */
{ 0, 0, 0 }, /* 18-20 serial_number */
0, /* 21 check_sum */
{ /* 22-29 oem_name[16] */
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0
},
0, /* 30 dvc_err_code */
0, /* 31 adv_err_code */
0, /* 32 adv_err_addr */
0, /* 33 saved_dvc_err_code */
0, /* 34 saved_adv_err_code */
0, /* 35 saved_adv_err_addr */
{ /* 36 - 55 reserved */
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
},
0, /* 56 cisptr_lsw */
0, /* 57 cisprt_msw */
/* 58-59 sub-id */
(PCI_ID_ADVANSYS_38C0800_REV1 & PCI_ID_DEV_VENDOR_MASK) >> 32,
};
#define ADW_MC_SDTR_OFFSET_ULTRA2_DT 0
#define ADW_MC_SDTR_OFFSET_ULTRA2 1
#define ADW_MC_SDTR_OFFSET_ULTRA 2
const struct adw_syncrate adw_syncrates[] =
{
/* mc_sdtr period rate */
{ ADW_MC_SDTR_80, 9, "80.0" },
{ ADW_MC_SDTR_40, 10, "40.0" },
{ ADW_MC_SDTR_20, 12, "20.0" },
{ ADW_MC_SDTR_10, 25, "10.0" },
{ ADW_MC_SDTR_5, 50, "5.0" },
{ ADW_MC_SDTR_ASYNC, 0, "async" }
};
static u_int16_t adw_eeprom_read_16(struct adw_softc *adw, int addr);
static void adw_eeprom_write_16(struct adw_softc *adw, int addr,
u_int data);
static void adw_eeprom_wait(struct adw_softc *adw);
int
adw_find_signature(struct adw_softc *adw)
{
if (adw_inb(adw, ADW_SIGNATURE_BYTE) == ADW_CHIP_ID_BYTE
&& adw_inw(adw, ADW_SIGNATURE_WORD) == ADW_CHIP_ID_WORD)
return (1);
return (0);
}
/*
* Reset Chip.
*/
void
adw_reset_chip(struct adw_softc *adw)
{
adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_RESET);
DELAY(1000 * 100);
adw_outw(adw, ADW_CTRL_REG, ADW_CTRL_REG_CMD_WR_IO_REG);
/*
* Initialize Chip registers.
*/
adw_outw(adw, ADW_SCSI_CFG1,
adw_inw(adw, ADW_SCSI_CFG1) & ~ADW_SCSI_CFG1_BIG_ENDIAN);
}
/*
* Reset the SCSI bus.
*/
int
adw_reset_bus(struct adw_softc *adw)
{
adw_idle_cmd_status_t status;
if (!dumping)
mtx_assert(&adw->lock, MA_OWNED);
status =
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_START, /*param*/0);
if (status != ADW_IDLE_CMD_SUCCESS) {
xpt_print_path(adw->path);
printf("Bus Reset start attempt failed\n");
return (1);
}
DELAY(ADW_BUS_RESET_HOLD_DELAY_US);
status =
adw_idle_cmd_send(adw, ADW_IDLE_CMD_SCSI_RESET_END, /*param*/0);
if (status != ADW_IDLE_CMD_SUCCESS) {
xpt_print_path(adw->path);
printf("Bus Reset end attempt failed\n");
return (1);
}
return (0);
}
/*
* Read the specified EEPROM location
*/
static u_int16_t
adw_eeprom_read_16(struct adw_softc *adw, int addr)
{
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_READ | addr);
adw_eeprom_wait(adw);
return (adw_inw(adw, ADW_EEP_DATA));
}
static void
adw_eeprom_write_16(struct adw_softc *adw, int addr, u_int data)
{
adw_outw(adw, ADW_EEP_DATA, data);
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE | addr);
adw_eeprom_wait(adw);
}
/*
* Wait for and EEPROM command to complete
*/
static void
adw_eeprom_wait(struct adw_softc *adw)
{
int i;
for (i = 0; i < ADW_EEP_DELAY_MS; i++) {
if ((adw_inw(adw, ADW_EEP_CMD) & ADW_EEP_CMD_DONE) != 0)
break;
DELAY(1000);
}
if (i == ADW_EEP_DELAY_MS)
panic("%s: Timedout Reading EEPROM",
device_get_nameunit(adw->device));
}
/*
* Read EEPROM configuration into the specified buffer.
*
* Return a checksum based on the EEPROM configuration read.
*/
u_int16_t
adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *eep_buf)
{
u_int16_t *wbuf;
u_int16_t wval;
u_int16_t chksum;
int eep_addr;
wbuf = (u_int16_t *)eep_buf;
chksum = 0;
for (eep_addr = ADW_EEP_DVC_CFG_BEGIN;
eep_addr < ADW_EEP_DVC_CFG_END;
eep_addr++, wbuf++) {
wval = adw_eeprom_read_16(adw, eep_addr);
chksum += wval;
*wbuf = wval;
}
/* checksum field is not counted in the checksum */
*wbuf = adw_eeprom_read_16(adw, eep_addr);
wbuf++;
/* Driver seeprom variables are not included in the checksum */
for (eep_addr = ADW_EEP_DVC_CTL_BEGIN;
eep_addr < ADW_EEP_MAX_WORD_ADDR;
eep_addr++, wbuf++)
*wbuf = adw_eeprom_read_16(adw, eep_addr);
return (chksum);
}
void
adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *eep_buf)
{
u_int16_t *wbuf;
u_int16_t addr;
u_int16_t chksum;
wbuf = (u_int16_t *)eep_buf;
chksum = 0;
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_ABLE);
adw_eeprom_wait(adw);
/*
* Write EEPROM until checksum.
*/
for (addr = ADW_EEP_DVC_CFG_BEGIN;
addr < ADW_EEP_DVC_CFG_END; addr++, wbuf++) {
chksum += *wbuf;
adw_eeprom_write_16(adw, addr, *wbuf);
}
/*
* Write calculated EEPROM checksum
*/
adw_eeprom_write_16(adw, addr, chksum);
/* skip over buffer's checksum */
wbuf++;
/*
* Write the rest.
*/
for (addr = ADW_EEP_DVC_CTL_BEGIN;
addr < ADW_EEP_MAX_WORD_ADDR; addr++, wbuf++)
adw_eeprom_write_16(adw, addr, *wbuf);
adw_outw(adw, ADW_EEP_CMD, ADW_EEP_CMD_WRITE_DISABLE);
adw_eeprom_wait(adw);
}
int
adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1)
{
u_int8_t biosmem[ADW_MC_BIOSLEN];
const u_int16_t *word_table;
const u_int8_t *byte_codes;
const u_int8_t *byte_codes_end;
u_int bios_sig;
u_int bytes_downloaded;
u_int addr;
u_int end_addr;
u_int checksum;
u_int scsicfg1;
u_int tid;
/*
* Save the RISC memory BIOS region before writing the microcode.
* The BIOS may already be loaded and using its RISC LRAM region
* so its region must be saved and restored.
*/
for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
biosmem[addr] = adw_lram_read_8(adw, ADW_MC_BIOSMEM + addr);
/*
* Save current per TID negotiated values if the BIOS has been
* loaded (BIOS signature is present). These will be used if
* we cannot get information from the EEPROM.
*/
addr = ADW_MC_BIOS_SIGNATURE - ADW_MC_BIOSMEM;
bios_sig = biosmem[addr]
| (biosmem[addr + 1] << 8);
if (bios_sig == 0x55AA
&& (adw->flags & ADW_EEPROM_FAILED) != 0) {
u_int major_ver;
u_int minor_ver;
u_int sdtr_able;
addr = ADW_MC_BIOS_VERSION - ADW_MC_BIOSMEM;
minor_ver = biosmem[addr + 1] & 0xF;
major_ver = (biosmem[addr + 1] >> 4) & 0xF;
if ((adw->chip == ADW_CHIP_ASC3550)
&& (major_ver <= 3
|| (major_ver == 3 && minor_ver <= 1))) {
/*
* BIOS 3.1 and earlier location of
* 'wdtr_able' variable.
*/
adw->user_wdtr =
adw_lram_read_16(adw, ADW_MC_WDTR_ABLE_BIOS_31);
} else {
adw->user_wdtr =
adw_lram_read_16(adw, ADW_MC_WDTR_ABLE);
}
sdtr_able = adw_lram_read_16(adw, ADW_MC_SDTR_ABLE);
for (tid = 0; tid < ADW_MAX_TID; tid++) {
u_int tid_mask;
u_int mc_sdtr;
tid_mask = 0x1 << tid;
if ((sdtr_able & tid_mask) == 0)
mc_sdtr = ADW_MC_SDTR_ASYNC;
else if ((adw->features & ADW_DT) != 0)
mc_sdtr = ADW_MC_SDTR_80;
else if ((adw->features & ADW_ULTRA2) != 0)
mc_sdtr = ADW_MC_SDTR_40;
else
mc_sdtr = ADW_MC_SDTR_20;
adw_set_user_sdtr(adw, tid, mc_sdtr);
}
adw->user_tagenb = adw_lram_read_16(adw, ADW_MC_TAGQNG_ABLE);
}
/*
* Load the Microcode.
*
* Assume the following compressed format of the microcode buffer:
*
* 253 word (506 byte) table indexed by byte code followed
* by the following byte codes:
*
* 1-Byte Code:
* 00: Emit word 0 in table.
* 01: Emit word 1 in table.
* .
* FD: Emit word 253 in table.
*
* Multi-Byte Code:
* FD RESEVED
*
* FE WW WW: (3 byte code)
* Word to emit is the next word WW WW.
* FF BB WW WW: (4 byte code)
* Emit BB count times next word WW WW.
*
*/
bytes_downloaded = 0;
word_table = (const u_int16_t *)adw->mcode_data->mcode_buf;
byte_codes = (const u_int8_t *)&word_table[253];
byte_codes_end = adw->mcode_data->mcode_buf
+ adw->mcode_data->mcode_size;
adw_outw(adw, ADW_RAM_ADDR, 0);
while (byte_codes < byte_codes_end) {
if (*byte_codes == 0xFF) {
u_int16_t value;
value = byte_codes[2]
| byte_codes[3] << 8;
adw_set_multi_2(adw, ADW_RAM_DATA,
value, byte_codes[1]);
bytes_downloaded += byte_codes[1];
byte_codes += 4;
} else if (*byte_codes == 0xFE) {
u_int16_t value;
value = byte_codes[1]
| byte_codes[2] << 8;
adw_outw(adw, ADW_RAM_DATA, value);
bytes_downloaded++;
byte_codes += 3;
} else {
adw_outw(adw, ADW_RAM_DATA, word_table[*byte_codes]);
bytes_downloaded++;
byte_codes++;
}
}
/* Convert from words to bytes */
bytes_downloaded *= 2;
/*
* Clear the rest of LRAM.
*/
for (addr = bytes_downloaded; addr < adw->memsize; addr += 2)
adw_outw(adw, ADW_RAM_DATA, 0);
/*
* Verify the microcode checksum.
*/
checksum = 0;
adw_outw(adw, ADW_RAM_ADDR, 0);
for (addr = 0; addr < bytes_downloaded; addr += 2)
checksum += adw_inw(adw, ADW_RAM_DATA);
if (checksum != adw->mcode_data->mcode_chksum) {
device_printf(adw->device, "Firmware load failed!\n");
return (EIO);
}
/*
* Restore the RISC memory BIOS region.
*/
for (addr = 0; addr < ADW_MC_BIOSLEN; addr++)
adw_lram_write_8(adw, addr + ADW_MC_BIOSLEN, biosmem[addr]);
/*
* Calculate and write the microcode code checksum to
* the microcode code checksum location.
*/
addr = adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR);
end_addr = adw_lram_read_16(adw, ADW_MC_CODE_END_ADDR);
checksum = 0;
adw_outw(adw, ADW_RAM_ADDR, addr);
for (; addr < end_addr; addr += 2)
checksum += adw_inw(adw, ADW_RAM_DATA);
adw_lram_write_16(adw, ADW_MC_CODE_CHK_SUM, checksum);
/*
* Tell the microcode what kind of chip it's running on.
*/
adw_lram_write_16(adw, ADW_MC_CHIP_TYPE, adw->chip);
/*
* Leave WDTR and SDTR negotiation disabled until the XPT has
* informed us of device capabilities, but do set the desired
* user rates in case we receive an SDTR request from the target
* before we negotiate. We turn on tagged queuing at the microcode
* level for all devices, and modulate this on a per command basis.
*/
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED1, adw->user_sdtr[0]);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED2, adw->user_sdtr[1]);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED3, adw->user_sdtr[2]);
adw_lram_write_16(adw, ADW_MC_SDTR_SPEED4, adw->user_sdtr[3]);
adw_lram_write_16(adw, ADW_MC_DISC_ENABLE, adw->user_discenb);
for (tid = 0; tid < ADW_MAX_TID; tid++) {
/* Cam limits the maximum number of commands for us */
adw_lram_write_8(adw, ADW_MC_NUMBER_OF_MAX_CMD + tid,
adw->max_acbs);
}
adw_lram_write_16(adw, ADW_MC_TAGQNG_ABLE, ~0);
/*
* Set SCSI_CFG0 Microcode Default Value.
*
* The microcode will set the SCSI_CFG0 register using this value
* after it is started.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG0,
ADW_SCSI_CFG0_PARITY_EN|ADW_SCSI_CFG0_SEL_TMO_LONG|
ADW_SCSI_CFG0_OUR_ID_EN|adw->initiator_id);
/*
* Tell the MC about the memory size that
* was setup by the probe code.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_MEM_CFG,
adw_inb(adw, ADW_MEM_CFG) & ADW_MEM_CFG_RAM_SZ_MASK);
/*
* Determine SCSI_CFG1 Microcode Default Value.
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
scsicfg1 = adw_inw(adw, ADW_SCSI_CFG1);
/*
* If the internal narrow cable is reversed all of the SCSI_CTRL
* register signals will be set. Check for and return an error if
* this condition is found.
*/
if ((adw_inw(adw, ADW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
device_printf(adw->device, "Illegal Cable Config!\n");
device_printf(adw->device, "Internal cable is reversed!\n");
return (EIO);
}
/*
* If this is a differential board and a single-ended device
* is attached to one of the connectors, return an error.
*/
if ((adw->features & ADW_ULTRA) != 0) {
if ((scsicfg1 & ADW_SCSI_CFG1_DIFF_MODE) != 0
&& (scsicfg1 & ADW_SCSI_CFG1_DIFF_SENSE) == 0) {
device_printf(adw->device, "A Single Ended Device is "
"attached to our differential bus!\n");
return (EIO);
}
} else {
if ((scsicfg1 & ADW2_SCSI_CFG1_DEV_DETECT_HVD) != 0) {
device_printf(adw->device,
"A High Voltage Differential Device "
"is attached to this controller.\n");
device_printf(adw->device,
"HVD devices are not supported.\n");
return (EIO);
}
}
/*
* Perform automatic termination control if desired.
*/
if ((adw->features & ADW_ULTRA2) != 0) {
u_int cable_det;
/*
* Ultra2 Chips require termination disabled to
* detect cable presence.
*/
adw_outw(adw, ADW_SCSI_CFG1,
scsicfg1 | ADW2_SCSI_CFG1_DIS_TERM_DRV);
cable_det = adw_inw(adw, ADW_SCSI_CFG1);
adw_outw(adw, ADW_SCSI_CFG1, scsicfg1);
/* SE Termination first if auto-term has been specified */
if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
/*
* For all SE cable configurations, high byte
* termination is enabled.
*/
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
if ((cable_det & ADW_SCSI_CFG1_INT8_MASK) != 0
|| (cable_det & ADW_SCSI_CFG1_INT16_MASK) != 0) {
/*
* If either cable is not present, the
* low byte must be terminated as well.
*/
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_L;
}
}
/* LVD auto-term */
if ((term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) == 0
&& (term_scsicfg1 & ADW2_SCSI_CFG1_DIS_TERM_DRV) == 0) {
/*
* If both cables are installed, termination
* is disabled. Otherwise it is enabled.
*/
if ((cable_det & ADW2_SCSI_CFG1_EXTLVD_MASK) != 0
|| (cable_det & ADW2_SCSI_CFG1_INTLVD_MASK) != 0) {
term_scsicfg1 |= ADW2_SCSI_CFG1_TERM_CTL_LVD;
}
}
term_scsicfg1 &= ~ADW2_SCSI_CFG1_DIS_TERM_DRV;
} else {
/* Ultra Controller Termination */
if ((term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) == 0) {
int cable_count;
int wide_cable_count;
cable_count = 0;
wide_cable_count = 0;
if ((scsicfg1 & ADW_SCSI_CFG1_INT16_MASK) == 0) {
cable_count++;
wide_cable_count++;
}
if ((scsicfg1 & ADW_SCSI_CFG1_INT8_MASK) == 0)
cable_count++;
/* There is only one external port */
if ((scsicfg1 & ADW_SCSI_CFG1_EXT16_MASK) == 0) {
cable_count++;
wide_cable_count++;
} else if ((scsicfg1 & ADW_SCSI_CFG1_EXT8_MASK) == 0)
cable_count++;
if (cable_count == 3) {
device_printf(adw->device,
"Illegal Cable Config!\n");
device_printf(adw->device,
"Only Two Ports may be used at a time!\n");
} else if (cable_count <= 1) {
/*
* At least two out of three cables missing.
* Terminate both bytes.
*/
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H
| ADW_SCSI_CFG1_TERM_CTL_L;
} else if (wide_cable_count <= 1) {
/* No two 16bit cables present. High on. */
term_scsicfg1 |= ADW_SCSI_CFG1_TERM_CTL_H;
}
}
}
/* Tell the user about our decission */
switch (term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK) {
case ADW_SCSI_CFG1_TERM_CTL_MASK:
printf("High & Low SE Term Enabled, ");
break;
case ADW_SCSI_CFG1_TERM_CTL_H:
printf("High SE Termination Enabled, ");
break;
case ADW_SCSI_CFG1_TERM_CTL_L:
printf("Low SE Term Enabled, ");
break;
default:
break;
}
if ((adw->features & ADW_ULTRA2) != 0
&& (term_scsicfg1 & ADW2_SCSI_CFG1_TERM_CTL_LVD) != 0)
printf("LVD Term Enabled, ");
/*
* Invert the TERM_CTL_H and TERM_CTL_L bits and then
* set 'scsicfg1'. The TERM_POL bit does not need to be
* referenced, because the hardware internally inverts
* the Termination High and Low bits if TERM_POL is set.
*/
if ((adw->features & ADW_ULTRA2) != 0) {
term_scsicfg1 = ~term_scsicfg1;
term_scsicfg1 &= ADW_SCSI_CFG1_TERM_CTL_MASK
| ADW2_SCSI_CFG1_TERM_CTL_LVD;
scsicfg1 &= ~(ADW_SCSI_CFG1_TERM_CTL_MASK
|ADW2_SCSI_CFG1_TERM_CTL_LVD
|ADW_SCSI_CFG1_BIG_ENDIAN
|ADW_SCSI_CFG1_TERM_POL
|ADW2_SCSI_CFG1_DEV_DETECT);
scsicfg1 |= term_scsicfg1;
} else {
term_scsicfg1 = ~term_scsicfg1 & ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 &= ~ADW_SCSI_CFG1_TERM_CTL_MASK;
scsicfg1 |= term_scsicfg1 | ADW_SCSI_CFG1_TERM_CTL_MANUAL;
scsicfg1 |= ADW_SCSI_CFG1_FLTR_DISABLE;
}
/*
* Set SCSI_CFG1 Microcode Default Value
*
* The microcode will set the SCSI_CFG1 register using this value
* after it is started below.
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SCSI_CFG1, scsicfg1);
/*
* Only accept selections on our initiator target id.
* This may change in target mode scenarios...
*/
adw_lram_write_16(adw, ADW_MC_DEFAULT_SEL_MASK,
(0x01 << adw->initiator_id));
/*
* Tell the microcode where it can find our
* Initiator Command Queue (ICQ). It is
* currently empty hence the "stopper" address.
*/
adw->commandq = adw->free_carriers;
adw->free_carriers = carrierbotov(adw, adw->commandq->next_ba);
adw->commandq->next_ba = ADW_CQ_STOPPER;
adw_lram_write_32(adw, ADW_MC_ICQ, adw->commandq->carr_ba);
/*
* Tell the microcode where it can find our
* Initiator Response Queue (IRQ). It too
* is currently empty.
*/
adw->responseq = adw->free_carriers;
adw->free_carriers = carrierbotov(adw, adw->responseq->next_ba);
adw->responseq->next_ba = ADW_CQ_STOPPER;
adw_lram_write_32(adw, ADW_MC_IRQ, adw->responseq->carr_ba);
adw_outb(adw, ADW_INTR_ENABLES,
ADW_INTR_ENABLE_HOST_INTR|ADW_INTR_ENABLE_GLOBAL_INTR);
adw_outw(adw, ADW_PC, adw_lram_read_16(adw, ADW_MC_CODE_BEGIN_ADDR));
return (0);
}
void
adw_set_user_sdtr(struct adw_softc *adw, u_int tid, u_int mc_sdtr)
{
adw->user_sdtr[ADW_TARGET_GROUP(tid)] &= ~ADW_TARGET_GROUP_MASK(tid);
adw->user_sdtr[ADW_TARGET_GROUP(tid)] |=
mc_sdtr << ADW_TARGET_GROUP_SHIFT(tid);
}
u_int
adw_get_user_sdtr(struct adw_softc *adw, u_int tid)
{
u_int mc_sdtr;
mc_sdtr = adw->user_sdtr[ADW_TARGET_GROUP(tid)];
mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
return (mc_sdtr);
}
void
adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr)
{
u_int mc_sdtr_offset;
u_int mc_sdtr;
mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
mc_sdtr &= ~ADW_TARGET_GROUP_MASK(tid);
mc_sdtr |= sdtr << ADW_TARGET_GROUP_SHIFT(tid);
adw_lram_write_16(adw, mc_sdtr_offset, mc_sdtr);
}
u_int
adw_get_chip_sdtr(struct adw_softc *adw, u_int tid)
{
u_int mc_sdtr_offset;
u_int mc_sdtr;
mc_sdtr_offset = ADW_MC_SDTR_SPEED1;
mc_sdtr_offset += ADW_TARGET_GROUP(tid) * 2;
mc_sdtr = adw_lram_read_16(adw, mc_sdtr_offset);
mc_sdtr &= ADW_TARGET_GROUP_MASK(tid);
mc_sdtr >>= ADW_TARGET_GROUP_SHIFT(tid);
return (mc_sdtr);
}
u_int
adw_find_sdtr(struct adw_softc *adw, u_int period)
{
int i;
i = 0;
if ((adw->features & ADW_DT) == 0)
i = ADW_MC_SDTR_OFFSET_ULTRA2;
if ((adw->features & ADW_ULTRA2) == 0)
i = ADW_MC_SDTR_OFFSET_ULTRA;
if (period == 0)
return ADW_MC_SDTR_ASYNC;
for (; i < nitems(adw_syncrates); i++) {
if (period <= adw_syncrates[i].period)
return (adw_syncrates[i].mc_sdtr);
}
return ADW_MC_SDTR_ASYNC;
}
u_int
adw_find_period(struct adw_softc *adw, u_int mc_sdtr)
{
int i;
for (i = 0; i < nitems(adw_syncrates); i++) {
if (mc_sdtr == adw_syncrates[i].mc_sdtr)
break;
}
return (adw_syncrates[i].period);
}
u_int
adw_hshk_cfg_period_factor(u_int tinfo)
{
tinfo &= ADW_HSHK_CFG_RATE_MASK;
tinfo >>= ADW_HSHK_CFG_RATE_SHIFT;
if (tinfo == 0x11)
/* 80MHz/DT */
return (9);
else if (tinfo == 0x10)
/* 40MHz */
return (10);
else
return (((tinfo * 25) + 50) / 4);
}
/*
* Send an idle command to the chip and wait for completion.
*/
adw_idle_cmd_status_t
adw_idle_cmd_send(struct adw_softc *adw, adw_idle_cmd_t cmd, u_int parameter)
{
u_int timeout;
adw_idle_cmd_status_t status;
if (!dumping)
mtx_assert(&adw->lock, MA_OWNED);
/*
* Clear the idle command status which is set by the microcode
* to a non-zero value to indicate when the command is completed.
*/
adw_lram_write_16(adw, ADW_MC_IDLE_CMD_STATUS, 0);
/*
* Write the idle command value after the idle command parameter
* has been written to avoid a race condition. If the order is not
* followed, the microcode may process the idle command before the
* parameters have been written to LRAM.
*/
adw_lram_write_32(adw, ADW_MC_IDLE_CMD_PARAMETER, parameter);
adw_lram_write_16(adw, ADW_MC_IDLE_CMD, cmd);
/*
* Tickle the RISC to tell it to process the idle command.
*/
adw_tickle_risc(adw, ADW_TICKLE_B);
/* Wait for up to 10 seconds for the command to complete */
timeout = 5000000;
while (--timeout) {
status = adw_lram_read_16(adw, ADW_MC_IDLE_CMD_STATUS);
if (status != 0)
break;
DELAY(20);
}
if (timeout == 0)
panic("%s: Idle Command Timed Out!",
device_get_nameunit(adw->device));
return (status);
}

872
sys/dev/advansys/adwlib.h
View File

@ -1,872 +0,0 @@
/*-
* Definitions for low level routines and data structures
* for the Advanced Systems Inc. SCSI controllers chips.
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1998, 1999, 2000 Justin T. Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
/*-
* Ported from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1998 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#ifndef _ADWLIB_H_
#define _ADWLIB_H_
#include "opt_adw.h"
#include <dev/advansys/adwmcode.h>
#define ADW_DEF_MAX_HOST_QNG 253
#define ADW_DEF_MIN_HOST_QNG 16
#define ADW_DEF_MAX_DVC_QNG 63
#define ADW_DEF_MIN_DVC_QNG 4
#define ADW_MAX_TID 15
#define ADW_MAX_LUN 7
#define ADW_ALL_TARGETS 0xFFFF
#define ADW_TARGET_GROUP(tid) ((tid) & ~0x3)
#define ADW_TARGET_GROUP_SHIFT(tid) (((tid) & 0x3) * 4)
#define ADW_TARGET_GROUP_MASK(tid) (0xF << ADW_TARGET_GROUP_SHIFT(tid))
/*
* Board Register offsets.
*/
#define ADW_INTR_STATUS_REG 0x0000
#define ADW_INTR_STATUS_INTRA 0x01
#define ADW_INTR_STATUS_INTRB 0x02
#define ADW_INTR_STATUS_INTRC 0x04
#define ADW_INTR_STATUS_INTRALL 0x07
#define ADW_SIGNATURE_WORD 0x0000
#define ADW_CHIP_ID_WORD 0x04C1
#define ADW_SIGNATURE_BYTE 0x0001
#define ADW_CHIP_ID_BYTE 0x25
#define ADW_INTR_ENABLES 0x0002 /*8 bit */
#define ADW_INTR_ENABLE_HOST_INTR 0x01
#define ADW_INTR_ENABLE_SEL_INTR 0x02
#define ADW_INTR_ENABLE_DPR_INTR 0x04
#define ADW_INTR_ENABLE_RTA_INTR 0x08
#define ADW_INTR_ENABLE_RMA_INTR 0x10
#define ADW_INTR_ENABLE_RST_INTR 0x20
#define ADW_INTR_ENABLE_DPE_INTR 0x40
#define ADW_INTR_ENABLE_GLOBAL_INTR 0x80
#define ADW_CTRL_REG 0x0002 /*16 bit*/
#define ADW_CTRL_REG_HOST_INTR 0x0100
#define ADW_CTRL_REG_SEL_INTR 0x0200
#define ADW_CTRL_REG_DPR_INTR 0x0400
#define ADW_CTRL_REG_RTA_INTR 0x0800
#define ADW_CTRL_REG_RMA_INTR 0x1000
#define ADW_CTRL_REG_RES_BIT14 0x2000
#define ADW_CTRL_REG_DPE_INTR 0x4000
#define ADW_CTRL_REG_POWER_DONE 0x8000
#define ADW_CTRL_REG_ANY_INTR 0xFF00
#define ADW_CTRL_REG_CMD_RESET 0x00C6
#define ADW_CTRL_REG_CMD_WR_IO_REG 0x00C5
#define ADW_CTRL_REG_CMD_RD_IO_REG 0x00C4
#define ADW_CTRL_REG_CMD_WR_PCI_CFG 0x00C3
#define ADW_CTRL_REG_CMD_RD_PCI_CFG 0x00C2
#define ADW_RAM_ADDR 0x0004
#define ADW_RAM_DATA 0x0006
#define ADW_RISC_CSR 0x000A
#define ADW_RISC_CSR_STOP 0x0000
#define ADW_RISC_TEST_COND 0x2000
#define ADW_RISC_CSR_RUN 0x4000
#define ADW_RISC_CSR_SINGLE_STEP 0x8000
#define ADW_SCSI_CFG0 0x000C
#define ADW_SCSI_CFG0_TIMER_MODEAB 0xC000 /*
* Watchdog, Second,
* and Selto timer CFG
*/
#define ADW_SCSI_CFG0_PARITY_EN 0x2000
#define ADW_SCSI_CFG0_EVEN_PARITY 0x1000
#define ADW_SCSI_CFG0_WD_LONG 0x0800 /*
* Watchdog Interval,
* 1: 57 min, 0: 13 sec
*/
#define ADW_SCSI_CFG0_QUEUE_128 0x0400 /*
* Queue Size,
* 1: 128 byte,
* 0: 64 byte
*/
#define ADW_SCSI_CFG0_PRIM_MODE 0x0100
#define ADW_SCSI_CFG0_SCAM_EN 0x0080
#define ADW_SCSI_CFG0_SEL_TMO_LONG 0x0040 /*
* Sel/Resel Timeout,
* 1: 400 ms,
* 0: 1.6 ms
*/
#define ADW_SCSI_CFG0_CFRM_ID 0x0020 /* SCAM id sel. */
#define ADW_SCSI_CFG0_OUR_ID_EN 0x0010
#define ADW_SCSI_CFG0_OUR_ID 0x000F
#define ADW_SCSI_CFG1 0x000E
#define ADW_SCSI_CFG1_BIG_ENDIAN 0x8000
#define ADW_SCSI_CFG1_TERM_POL 0x2000
#define ADW_SCSI_CFG1_SLEW_RATE 0x1000
#define ADW_SCSI_CFG1_FILTER_MASK 0x0C00
#define ADW_SCSI_CFG1_FLTR_DISABLE 0x0000
#define ADW_SCSI_CFG1_FLTR_11_TO_20NS 0x0800
#define ADW_SCSI_CFG1_FLTR_21_TO_39NS 0x0C00
#define ADW_SCSI_CFG1_DIS_ACTIVE_NEG 0x0200
#define ADW_SCSI_CFG1_DIFF_MODE 0x0100
#define ADW_SCSI_CFG1_DIFF_SENSE 0x0080
#define ADW_SCSI_CFG1_TERM_CTL_MANUAL 0x0040 /* Global Term Switch */
#define ADW_SCSI_CFG1_TERM_CTL_MASK 0x0030
#define ADW_SCSI_CFG1_TERM_CTL_H 0x0020 /* Enable SCSI-H */
#define ADW_SCSI_CFG1_TERM_CTL_L 0x0010 /* Enable SCSI-L */
#define ADW_SCSI_CFG1_CABLE_DETECT 0x000F
#define ADW_SCSI_CFG1_EXT16_MASK 0x0008 /* Ext16 cable pres */
#define ADW_SCSI_CFG1_EXT8_MASK 0x0004 /* Ext8 cable pres */
#define ADW_SCSI_CFG1_INT8_MASK 0x0002 /* Int8 cable pres */
#define ADW_SCSI_CFG1_INT16_MASK 0x0001 /* Int16 cable pres */
#define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_A_MASK \
(ADW_SCSI_CFG1_EXT16_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
#define ADW_SCSI_CFG1_ILLEGAL_CABLE_CONF_B_MASK \
(ADW_SCSI_CFG1_EXT8_MASK|ADW_SCSI_CFG1_INT8_MASK|ADW_SCSI_CFG1_INT16_MASK)
/*
* Addendum for ASC-38C0800 Chip
*/
#define ADW2_SCSI_CFG1_DIS_TERM_DRV 0x4000 /*
* The Terminators
* must be disabled
* in order to detect
* cable presence
*/
#define ADW2_SCSI_CFG1_DEV_DETECT 0x1C00
#define ADW2_SCSI_CFG1_DEV_DETECT_HVD 0x1000
#define ADW2_SCSI_CFG1_DEV_DETECT_LVD 0x0800
#define ADW2_SCSI_CFG1_DEV_DETECT_SE 0x0400
#define ADW2_SCSI_CFG1_TERM_CTL_LVD 0x00C0 /* Ultra2 Only */
#define ADW2_SCSI_CFG1_TERM_LVD_HI 0x0080
#define ADW2_SCSI_CFG1_TERM_LVD_LO 0x0040
#define ADW2_SCSI_CFG1_EXTLVD_MASK 0x0008 /* ExtLVD cable pres */
#define ADW2_SCSI_CFG1_INTLVD_MASK 0x0004 /* IntLVD cable pres */
#define ADW_MEM_CFG 0x0010
#define ADW_MEM_CFG_BIOS_EN 0x40
#define ADW_MEM_CFG_FAST_EE_CLK 0x20 /* Diagnostic Bit */
#define ADW_MEM_CFG_RAM_SZ_MASK 0x1C /* RISC RAM Size */
#define ADW_MEM_CFG_RAM_SZ_2KB 0x00
#define ADW_MEM_CFG_RAM_SZ_4KB 0x04
#define ADW_MEM_CFG_RAM_SZ_8KB 0x08
#define ADW_MEM_CFG_RAM_SZ_16KB 0x0C
#define ADW_MEM_CFG_RAM_SZ_32KB 0x10
#define ADW_MEM_CFG_RAM_SZ_64KB 0x14
#define ADW_GPIO_CNTL 0x0011
#define ADW_GPIO_DATA 0x0012
#define ADW_COMMA 0x0014
#define ADW_COMMB 0x0018
#define ADW_EEP_CMD 0x001A
#define ADW_EEP_CMD_READ 0x0080 /* or in address */
#define ADW_EEP_CMD_WRITE 0x0040 /* or in address */
#define ADW_EEP_CMD_WRITE_ABLE 0x0030
#define ADW_EEP_CMD_WRITE_DISABLE 0x0000
#define ADW_EEP_CMD_DONE 0x0200
#define ADW_EEP_CMD_DONE_ERR 0x0001
#define ADW_EEP_DELAY_MS 100
#define ADW_EEP_DATA 0x001C
#define ADW_DMA_CFG0 0x0020
#define ADW_DMA_CFG0_BC_THRESH_ENB 0x80
#define ADW_DMA_CFG0_FIFO_THRESH 0x70
#define ADW_DMA_CFG0_FIFO_THRESH_16B 0x00
#define ADW_DMA_CFG0_FIFO_THRESH_32B 0x20
#define ADW_DMA_CFG0_FIFO_THRESH_48B 0x30
#define ADW_DMA_CFG0_FIFO_THRESH_64B 0x40
#define ADW_DMA_CFG0_FIFO_THRESH_80B 0x50
#define ADW_DMA_CFG0_FIFO_THRESH_96B 0x60
#define ADW_DMA_CFG0_FIFO_THRESH_112B 0x70
#define ADW_DMA_CFG0_START_CTL_MASK 0x0C
#define ADW_DMA_CFG0_START_CTL_TH 0x00 /* Start on thresh */
#define ADW_DMA_CFG0_START_CTL_IDLE 0x04 /* Start when idle */
#define ADW_DMA_CFG0_START_CTL_TH_IDLE 0x08 /* Either */
#define ADW_DMA_CFG0_START_CTL_EM_FU 0x0C /* Start on full/empty */
#define ADW_DMA_CFG0_READ_CMD_MASK 0x03
#define ADW_DMA_CFG0_READ_CMD_MR 0x00
#define ADW_DMA_CFG0_READ_CMD_MRL 0x02
#define ADW_DMA_CFG0_READ_CMD_MRM 0x03
#define ADW_TICKLE 0x0022
#define ADW_TICKLE_NOP 0x00
#define ADW_TICKLE_A 0x01
#define ADW_TICKLE_B 0x02
#define ADW_TICKLE_C 0x03
/* Program Counter */
#define ADW_PC 0x2A
#define ADW_SCSI_CTRL 0x0034
#define ADW_SCSI_CTRL_RSTOUT 0x2000
/*
* ASC-38C0800 RAM BIST Register bit definitions
*/
#define ADW_RAM_BIST 0x0038
#define ADW_RAM_BIST_RAM_TEST_MODE 0x80
#define ADW_RAM_BIST_PRE_TEST_MODE 0x40
#define ADW_RAM_BIST_NORMAL_MODE 0x00
#define ADW_RAM_BIST_RAM_TEST_DONE 0x10
#define ADW_RAM_BIST_RAM_TEST_STATUS 0x0F
#define ADW_RAM_BIST_RAM_TEST_HOST_ERR 0x08
#define ADW_RAM_BIST_RAM_TEST_RAM_ERR 0x04
#define ADW_RAM_BIST_RAM_TEST_RISC_ERR 0x02
#define ADW_RAM_BIST_RAM_TEST_SCSI_ERR 0x01
#define ADW_RAM_BIST_RAM_TEST_SUCCESS 0x00
#define ADW_RAM_BIST_PRE_TEST_VALUE 0x05
#define ADW_RAM_BIST_NORMAL_VALUE 0x00
#define ADW_PLL_TEST 0x0039
#define ADW_SCSI_RESET_HOLD_TIME_US 60
/* LRAM Constants */
#define ADW_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
#define ADW_3550_IOLEN 0x40 /* I/O Port Range in bytes */
#define ADW_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
#define ADW_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
#define ADW_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
#define ADW_38C1600_IOLEN 0x100 /* I/O Port Range in bytes */
#define ADW_38C1600_MEMLEN 0x1000 /* Memory Range 4KB */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define PCI_ID_ADVANSYS_3550 0x230010CD00000000ull
#define PCI_ID_ADVANSYS_38C0800_REV1 0x250010CD00000000ull
#define PCI_ID_ADVANSYS_38C1600_REV1 0x270010CD00000000ull
#define PCI_ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
#define PCI_ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
/* ====================== SCSI Request Structures =========================== */
#define ADW_NO_OF_SG_PER_BLOCK 15
/*
* Although the adapter can deal with S/G lists of indefinite size,
* we limit the list to 30 to conserve space as the kernel can only send
* us buffers of at most 64KB currently.
*/
#define ADW_SG_BLOCKCNT 2
#define ADW_SGSIZE (ADW_NO_OF_SG_PER_BLOCK * ADW_SG_BLOCKCNT)
struct adw_sg_elm {
u_int32_t sg_addr;
u_int32_t sg_count;
};
/* sg block structure used by the microcode */
struct adw_sg_block {
u_int8_t reserved1;
u_int8_t reserved2;
u_int8_t reserved3;
u_int8_t sg_cnt; /* Valid entries in this block */
u_int32_t sg_busaddr_next; /* link to the next sg block */
struct adw_sg_elm sg_list[ADW_NO_OF_SG_PER_BLOCK];
};
/* Structure representing a single allocation block of adw sg blocks */
struct sg_map_node {
bus_dmamap_t sg_dmamap;
bus_addr_t sg_physaddr;
struct adw_sg_block* sg_vaddr;
SLIST_ENTRY(sg_map_node) links;
};
typedef enum {
QHSTA_NO_ERROR = 0x00,
QHSTA_M_SEL_TIMEOUT = 0x11,
QHSTA_M_DATA_OVER_RUN = 0x12,
QHSTA_M_UNEXPECTED_BUS_FREE = 0x13,
QHSTA_M_QUEUE_ABORTED = 0x15,
QHSTA_M_SXFR_SDMA_ERR = 0x16, /* SCSI DMA Error */
QHSTA_M_SXFR_SXFR_PERR = 0x17, /* SCSI Bus Parity Error */
QHSTA_M_RDMA_PERR = 0x18, /* RISC PCI DMA parity error */
QHSTA_M_SXFR_OFF_UFLW = 0x19, /* Offset Underflow */
QHSTA_M_SXFR_OFF_OFLW = 0x20, /* Offset Overflow */
QHSTA_M_SXFR_WD_TMO = 0x21, /* Watchdog Timeout */
QHSTA_M_SXFR_DESELECTED = 0x22, /* Deselected */
QHSTA_M_SXFR_XFR_PH_ERR = 0x24, /* Transfer Phase Error */
QHSTA_M_SXFR_UNKNOWN_ERROR = 0x25, /* SXFR_STATUS Unknown Error */
QHSTA_M_SCSI_BUS_RESET = 0x30, /* Request aborted from SBR */
QHSTA_M_SCSI_BUS_RESET_UNSOL= 0x31, /* Request aborted from unsol. SBR*/
QHSTA_M_BUS_DEVICE_RESET = 0x32, /* Request aborted from BDR */
QHSTA_M_DIRECTION_ERR = 0x35, /* Data Phase mismatch */
QHSTA_M_DIRECTION_ERR_HUNG = 0x36, /* Data Phase mismatch - bus hang */
QHSTA_M_WTM_TIMEOUT = 0x41,
QHSTA_M_BAD_CMPL_STATUS_IN = 0x42,
QHSTA_M_NO_AUTO_REQ_SENSE = 0x43,
QHSTA_M_AUTO_REQ_SENSE_FAIL = 0x44,
QHSTA_M_INVALID_DEVICE = 0x45, /* Bad target ID */
QHSTA_M_FROZEN_TIDQ = 0x46, /* TID Queue frozen. */
QHSTA_M_SGBACKUP_ERROR = 0x47 /* Scatter-Gather backup error */
} host_status_t;
typedef enum {
QD_NO_STATUS = 0x00, /* Request not completed yet. */
QD_NO_ERROR = 0x01,
QD_ABORTED_BY_HOST = 0x02,
QD_WITH_ERROR = 0x04
} done_status_t;
/*
* Microcode request structure
*
* All fields in this structure are used by the microcode so their
* size and ordering cannot be changed.
*/
struct adw_scsi_req_q {
u_int8_t cntl; /* Ucode flags and state. */
u_int8_t target_cmd;
u_int8_t target_id; /* Device target identifier. */
u_int8_t target_lun; /* Device target logical unit number. */
u_int32_t data_addr; /* Data buffer physical address. */
u_int32_t data_cnt; /* Data count. Ucode sets to residual. */
u_int32_t sense_baddr; /* Sense buffer bus address. */
u_int32_t carrier_baddr; /* Carrier bus address. */
u_int8_t mflag; /* microcode flag field. */
u_int8_t sense_len; /* Auto-sense length. Residual on complete. */
u_int8_t cdb_len; /* SCSI CDB length. */
u_int8_t scsi_cntl; /* SCSI command control flags (tags, nego) */
#define ADW_QSC_NO_DISC 0x01
#define ADW_QSC_NO_TAGMSG 0x02
#define ADW_QSC_NO_SYNC 0x04
#define ADW_QSC_NO_WIDE 0x08
#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR */
#define ADW_QSC_SIMPLE_Q_TAG 0x00
#define ADW_QSC_HEAD_OF_Q_TAG 0x40
#define ADW_QSC_ORDERED_Q_TAG 0x80
u_int8_t done_status; /* Completion status. */
u_int8_t scsi_status; /* SCSI status byte. */
u_int8_t host_status; /* Ucode host status. */
u_int8_t sg_wk_ix; /* Microcode working SG index. */
u_int8_t cdb[12]; /* SCSI command block. */
u_int32_t sg_real_addr; /* SG list physical address. */
u_int32_t scsi_req_baddr; /* Bus address of this structure. */
u_int32_t sg_wk_data_cnt; /* Saved data count at disconnection. */
/*
* The 'tokens' placed in these two fields are
* used to identify the scsi request and the next
* carrier in the response queue, *not* physical
* addresses. This driver uses byte offsets for
* portability and speed of mapping back to either
* a virtual or physical address.
*/
u_int32_t scsi_req_bo; /* byte offset of this structure */
u_int32_t carrier_bo; /* byte offst of our carrier. */
};
typedef enum {
ACB_FREE = 0x00,
ACB_ACTIVE = 0x01,
ACB_RELEASE_SIMQ = 0x02,
ACB_RECOVERY_ACB = 0x04
} acb_state;
struct acb {
struct adw_scsi_req_q queue;
bus_dmamap_t dmamap;
acb_state state;
union ccb *ccb;
struct adw_sg_block* sg_blocks;
struct callout timer;
bus_addr_t sg_busaddr;
struct scsi_sense_data sense_data;
SLIST_ENTRY(acb) links;
};
/*
* EEPROM configuration format
*
* Field naming convention:
*
* *_enable indicates the field enables or disables the feature. The
* value is never reset.
*
* *_able indicates both whether a feature should be enabled or disabled
* and whether a device is capable of the feature. At initialization
* this field may be set, but later if a device is found to be incapable
* of the feature, the field is cleared.
*
* Default values are maintained in a_init.c in the structure
* Default_EEPROM_Config.
*/
struct adw_eeprom
{
u_int16_t cfg_lsw; /* 00 power up initialization */
#define ADW_EEPROM_BIG_ENDIAN 0x8000
#define ADW_EEPROM_BIOS_ENABLE 0x4000
#define ADW_EEPROM_TERM_POL 0x2000
#define ADW_EEPROM_CIS_LD 0x1000
/* bit 13 set - Term Polarity Control */
/* bit 14 set - BIOS Enable */
/* bit 15 set - Big Endian Mode */
u_int16_t cfg_msw; /* unused */
u_int16_t disc_enable;
u_int16_t wdtr_able;
union {
/*
* sync enable bits for UW cards,
* actual sync rate for TID 0-3
* on U2W and U160 cards.
*/
u_int16_t sync_enable;
u_int16_t sdtr1;
} sync1;
u_int16_t start_motor;
u_int16_t tagqng_able;
u_int16_t bios_scan;
u_int16_t scam_tolerant;
u_int8_t adapter_scsi_id;
u_int8_t bios_boot_delay;
u_int8_t scsi_reset_delay;
u_int8_t bios_id_lun; /* high nibble is lun */
/* low nibble is scsi id */
u_int8_t termination_se; /* 0 - automatic */
#define ADW_EEPROM_TERM_AUTO 0
#define ADW_EEPROM_TERM_OFF 1
#define ADW_EEPROM_TERM_HIGH_ON 2
#define ADW_EEPROM_TERM_BOTH_ON 3
u_int8_t termination_lvd;
u_int16_t bios_ctrl;
#define ADW_BIOS_INIT_DIS 0x0001 /* Don't act as initiator */
#define ADW_BIOS_EXT_TRANS 0x0002 /* > 1 GB support */
#define ADW_BIOS_MORE_2DISK 0x0004 /* > 1 GB support */
#define ADW_BIOS_NO_REMOVABLE 0x0008 /* don't support removable media */
#define ADW_BIOS_CD_BOOT 0x0010 /* support bootable CD */
#define ADW_BIOS_SCAN_EN 0x0020 /* BIOS SCAN enabled */
#define ADW_BIOS_MULTI_LUN 0x0040 /* probe luns */
#define ADW_BIOS_MESSAGE 0x0080 /* display BIOS message */
#define ADW_BIOS_RESET_BUS 0x0200 /* reset SCSI bus durint init */
#define ADW_BIOS_QUIET 0x0800 /* No verbose initialization */
#define ADW_BIOS_SCSI_PAR_EN 0x1000 /* SCSI parity enabled */
union {
/* 13
* ultra enable bits for UW cards,
* actual sync rate for TID 4-7
* on U2W and U160 cards.
*/
u_int16_t ultra_enable;
u_int16_t sdtr2;
} sync2;
union {
/* 14
* reserved for UW cards,
* actual sync rate for TID 8-11
* on U2W and U160 cards.
*/
u_int16_t reserved;
u_int16_t sdtr3;
} sync3;
u_int8_t max_host_qng; /* 15 maximum host queuing */
u_int8_t max_dvc_qng; /* maximum per device queuing */
u_int16_t dvc_cntl; /* 16 control bit for driver */
union {
/* 17
* reserved for UW cards,
* actual sync rate for TID 12-15
* on U2W and U160 cards.
*/
u_int16_t reserved;
u_int16_t sdtr4;
} sync4;
u_int16_t serial_number[3]; /* 18-20 */
u_int16_t checksum; /* 21 */
u_int8_t oem_name[16]; /* 22 - 29 */
u_int16_t dvc_err_code; /* 30 */
u_int16_t adv_err_code; /* 31 */
u_int16_t adv_err_addr; /* 32 */
u_int16_t saved_dvc_err_code; /* 33 */
u_int16_t saved_adv_err_code; /* 34 */
u_int16_t saved_adv_err_addr; /* 35 */
u_int16_t reserved[20]; /* 36 - 55 */
u_int16_t cisptr_lsw; /* 56 CIS data */
u_int16_t cisptr_msw; /* 57 CIS data */
u_int32_t subid; /* 58-59 SubSystem Vendor/Dev ID */
u_int16_t reserved2[4];
};
/* EEProm Addresses */
#define ADW_EEP_DVC_CFG_BEGIN 0x00
#define ADW_EEP_DVC_CFG_END (offsetof(struct adw_eeprom, checksum)/2)
#define ADW_EEP_DVC_CTL_BEGIN (offsetof(struct adw_eeprom, oem_name)/2)
#define ADW_EEP_MAX_WORD_ADDR (sizeof(struct adw_eeprom)/2)
#define ADW_BUS_RESET_HOLD_DELAY_US 100
typedef enum {
ADW_CHIP_NONE,
ADW_CHIP_ASC3550, /* Ultra-Wide IC */
ADW_CHIP_ASC38C0800, /* Ultra2-Wide/LVD IC */
ADW_CHIP_ASC38C1600 /* Ultra3-Wide/LVD2 IC */
} adw_chip;
typedef enum {
ADW_FENONE = 0x0000,
ADW_ULTRA = 0x0001, /* Supports 20MHz Transfers */
ADW_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
ADW_DT = 0x0004, /* Supports Double Transition REQ/ACK */
ADW_WIDE = 0x0008, /* Wide Channel */
ADW_ASC3550_FE = ADW_ULTRA,
ADW_ASC38C0800_FE = ADW_ULTRA2,
ADW_ASC38C1600_FE = ADW_ULTRA2|ADW_DT
} adw_feature;
typedef enum {
ADW_FNONE = 0x0000,
ADW_EEPROM_FAILED = 0x0001
} adw_flag;
typedef enum {
ADW_STATE_NORMAL = 0x00,
ADW_RESOURCE_SHORTAGE = 0x01
} adw_state;
typedef enum {
ADW_MC_SDTR_ASYNC,
ADW_MC_SDTR_5,
ADW_MC_SDTR_10,
ADW_MC_SDTR_20,
ADW_MC_SDTR_40,
ADW_MC_SDTR_80
} adw_mc_sdtr;
struct adw_syncrate
{
adw_mc_sdtr mc_sdtr;
u_int8_t period;
char *rate;
};
/* We have an input and output queue for our carrier structures */
#define ADW_OUTPUT_QUEUE 0 /* Offset into carriers member */
#define ADW_INPUT_QUEUE 1 /* Offset into carriers member */
#define ADW_NUM_CARRIER_QUEUES 2
struct adw_softc
{
struct resource *res;
adw_state state;
bus_dma_tag_t buffer_dmat;
struct acb *acbs;
struct adw_carrier *carriers;
struct adw_carrier *free_carriers;
struct adw_carrier *commandq;
struct adw_carrier *responseq;
LIST_HEAD(, ccb_hdr) pending_ccbs;
SLIST_HEAD(, acb) free_acb_list;
bus_dma_tag_t parent_dmat;
bus_dma_tag_t carrier_dmat; /* dmat for our acb carriers*/
bus_dmamap_t carrier_dmamap;
bus_dma_tag_t acb_dmat; /* dmat for our ccb array */
bus_dmamap_t acb_dmamap;
bus_dma_tag_t sg_dmat; /* dmat for our sg maps */
SLIST_HEAD(, sg_map_node) sg_maps;
bus_addr_t acb_busbase;
bus_addr_t carrier_busbase;
adw_chip chip;
adw_feature features;
adw_flag flags;
u_int memsize;
char channel;
struct mtx lock;
struct cam_path *path;
struct cam_sim *sim;
struct resource *regs;
struct resource *irq;
void *ih;
const struct adw_mcode *mcode_data;
const struct adw_eeprom *default_eeprom;
device_t device;
int regs_res_type;
int regs_res_id;
int irq_res_type;
u_int max_acbs;
u_int num_acbs;
u_int initiator_id;
u_int init_level;
cam_status last_reset; /* Last reset type */
u_int16_t bios_ctrl;
u_int16_t user_wdtr;
u_int16_t user_sdtr[4]; /* A nibble per-device */
u_int16_t user_tagenb;
u_int16_t tagenb;
u_int16_t user_discenb;
u_int16_t serial_number[3];
};
extern const struct adw_eeprom adw_asc3550_default_eeprom;
extern const struct adw_eeprom adw_asc38C0800_default_eeprom;
extern const struct adw_syncrate adw_syncrates[];
extern const int adw_num_syncrates;
#define adw_inb(adw, port) \
bus_read_1((adw)->res, port)
#define adw_inw(adw, port) \
bus_read_2((adw)->res, port)
#define adw_inl(adw, port) \
bus_read_4((adw)->res, port)
#define adw_outb(adw, port, value) \
bus_write_1((adw)->res, port, value)
#define adw_outw(adw, port, value) \
bus_write_2((adw)->res, port, value)
#define adw_outl(adw, port, value) \
bus_write_4((adw)->res, port, value)
#define adw_set_multi_2(adw, port, value, count) \
bus_set_multi_2((adw)->res, port, value, count)
static __inline u_int adw_lram_read_8(struct adw_softc *adw, u_int addr);
static __inline u_int adw_lram_read_16(struct adw_softc *adw, u_int addr);
static __inline u_int adw_lram_read_32(struct adw_softc *adw, u_int addr);
static __inline void adw_lram_write_8(struct adw_softc *adw, u_int addr,
u_int value);
static __inline void adw_lram_write_16(struct adw_softc *adw, u_int addr,
u_int value);
static __inline void adw_lram_write_32(struct adw_softc *adw, u_int addr,
u_int value);
static __inline u_int32_t acbvtobo(struct adw_softc *adw,
struct acb *acb);
static __inline u_int32_t acbvtob(struct adw_softc *adw,
struct acb *acb);
static __inline struct acb * acbbotov(struct adw_softc *adw,
u_int32_t busaddr);
static __inline struct acb * acbbtov(struct adw_softc *adw,
u_int32_t busaddr);
static __inline u_int32_t carriervtobo(struct adw_softc *adw,
struct adw_carrier *carrier);
static __inline u_int32_t carriervtob(struct adw_softc *adw,
struct adw_carrier *carrier);
static __inline struct adw_carrier *
carrierbotov(struct adw_softc *adw,
u_int32_t byte_offset);
static __inline struct adw_carrier *
carrierbtov(struct adw_softc *adw,
u_int32_t baddr);
static __inline u_int
adw_lram_read_8(struct adw_softc *adw, u_int addr)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
return (adw_inb(adw, ADW_RAM_DATA));
}
static __inline u_int
adw_lram_read_16(struct adw_softc *adw, u_int addr)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
return (adw_inw(adw, ADW_RAM_DATA));
}
static __inline u_int
adw_lram_read_32(struct adw_softc *adw, u_int addr)
{
u_int retval;
adw_outw(adw, ADW_RAM_ADDR, addr);
retval = adw_inw(adw, ADW_RAM_DATA);
retval |= (adw_inw(adw, ADW_RAM_DATA) << 16);
return (retval);
}
static __inline void
adw_lram_write_8(struct adw_softc *adw, u_int addr, u_int value)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
adw_outb(adw, ADW_RAM_DATA, value);
}
static __inline void
adw_lram_write_16(struct adw_softc *adw, u_int addr, u_int value)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
adw_outw(adw, ADW_RAM_DATA, value);
}
static __inline void
adw_lram_write_32(struct adw_softc *adw, u_int addr, u_int value)
{
adw_outw(adw, ADW_RAM_ADDR, addr);
adw_outw(adw, ADW_RAM_DATA, value);
adw_outw(adw, ADW_RAM_DATA, value >> 16);
}
static __inline u_int32_t
acbvtobo(struct adw_softc *adw, struct acb *acb)
{
return ((u_int32_t)((caddr_t)acb - (caddr_t)adw->acbs));
}
static __inline u_int32_t
acbvtob(struct adw_softc *adw, struct acb *acb)
{
return (adw->acb_busbase + acbvtobo(adw, acb));
}
static __inline struct acb *
acbbotov(struct adw_softc *adw, u_int32_t byteoffset)
{
return ((struct acb *)((caddr_t)adw->acbs + byteoffset));
}
static __inline struct acb *
acbbtov(struct adw_softc *adw, u_int32_t busaddr)
{
return (acbbotov(adw, busaddr - adw->acb_busbase));
}
/*
* Return the byte offset for a carrier relative to our array of carriers.
*/
static __inline u_int32_t
carriervtobo(struct adw_softc *adw, struct adw_carrier *carrier)
{
return ((u_int32_t)((caddr_t)carrier - (caddr_t)adw->carriers));
}
static __inline u_int32_t
carriervtob(struct adw_softc *adw, struct adw_carrier *carrier)
{
return (adw->carrier_busbase + carriervtobo(adw, carrier));
}
static __inline struct adw_carrier *
carrierbotov(struct adw_softc *adw, u_int32_t byte_offset)
{
return ((struct adw_carrier *)((caddr_t)adw->carriers + byte_offset));
}
static __inline struct adw_carrier *
carrierbtov(struct adw_softc *adw, u_int32_t baddr)
{
return (carrierbotov(adw, baddr - adw->carrier_busbase));
}
/* Initialization */
int adw_find_signature(struct adw_softc *adw);
void adw_reset_chip(struct adw_softc *adw);
int adw_reset_bus(struct adw_softc *adw);
u_int16_t adw_eeprom_read(struct adw_softc *adw, struct adw_eeprom *buf);
void adw_eeprom_write(struct adw_softc *adw, struct adw_eeprom *buf);
int adw_init_chip(struct adw_softc *adw, u_int term_scsicfg1);
void adw_set_user_sdtr(struct adw_softc *adw,
u_int tid, u_int mc_sdtr);
u_int adw_get_user_sdtr(struct adw_softc *adw, u_int tid);
void adw_set_chip_sdtr(struct adw_softc *adw, u_int tid, u_int sdtr);
u_int adw_get_chip_sdtr(struct adw_softc *adw, u_int tid);
u_int adw_find_sdtr(struct adw_softc *adw, u_int period);
u_int adw_find_period(struct adw_softc *adw, u_int mc_sdtr);
u_int adw_hshk_cfg_period_factor(u_int tinfo);
/* Idle Commands */
adw_idle_cmd_status_t adw_idle_cmd_send(struct adw_softc *adw, u_int cmd,
u_int parameter);
/* SCSI Transaction Processing */
static __inline void adw_send_acb(struct adw_softc *adw, struct acb *acb,
u_int32_t acb_baddr);
static __inline void adw_tickle_risc(struct adw_softc *adw, u_int value)
{
/*
* Tickle the RISC to tell it to read its Command Queue Head pointer.
*/
adw_outb(adw, ADW_TICKLE, value);
if (adw->chip == ADW_CHIP_ASC3550) {
/*
* Clear the tickle value. In the ASC-3550 the RISC flag
* command 'clr_tickle_a' does not work unless the host
* value is cleared.
*/
adw_outb(adw, ADW_TICKLE, ADW_TICKLE_NOP);
}
}
static __inline void
adw_send_acb(struct adw_softc *adw, struct acb *acb, u_int32_t acb_baddr)
{
struct adw_carrier *new_cq;
new_cq = adw->free_carriers;
adw->free_carriers = carrierbotov(adw, new_cq->next_ba);
new_cq->next_ba = ADW_CQ_STOPPER;
acb->queue.carrier_baddr = adw->commandq->carr_ba;
acb->queue.carrier_bo = adw->commandq->carr_offset;
adw->commandq->areq_ba = acbvtob(adw, acb);
adw->commandq->next_ba = new_cq->carr_ba;
#if 0
printf("EnQ 0x%x 0x%x 0x%x 0x%x\n",
adw->commandq->carr_offset,
adw->commandq->carr_ba,
adw->commandq->areq_ba,
adw->commandq->next_ba);
#endif
adw->commandq = new_cq;
adw_tickle_risc(adw, ADW_TICKLE_A);
}
#endif /* _ADWLIB_H_ */

995
sys/dev/advansys/adwmcode.c
View File

@ -1,995 +0,0 @@
/*-
* Downloadable microcode for Second Generation
* Advanced Systems Inc. SCSI controllers
*
*
* Obtained from:
* advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
*
* Copyright (c) 1995-1999 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <dev/advansys/adwmcode.h>
const u_int8_t adw_asc3550_mcode[] =
{
0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x00, 0xfc, 0x48,
0xe4, 0x01, 0x00, 0x18, 0xe4, 0x00, 0xf6, 0x01, 0xf6, 0x18, 0x80,
0x48, 0x19, 0x02, 0x00, 0xff, 0xff, 0x03, 0xf6, 0x00, 0xfa, 0xff,
0x00, 0x82, 0xe7, 0x01, 0xfa, 0x9e, 0xe7, 0x09, 0xe7, 0x3a, 0x0e,
0x00, 0xea, 0x01, 0xe6, 0x55, 0xf0, 0x03, 0x00, 0x08, 0x00, 0x18,
0xf4, 0x3e, 0x01, 0x3e, 0x57, 0x04, 0x00, 0x85, 0xf0, 0x00, 0xe6,
0x00, 0xec, 0x1e, 0xf0, 0x32, 0xf0, 0x34, 0x19, 0x86, 0xf0, 0xd0,
0x01, 0xd5, 0xf0, 0xde, 0x0c, 0x98, 0x57, 0xbc, 0x00, 0x0c, 0x1c,
0x0e, 0x13, 0x38, 0x54, 0xb1, 0xf0, 0xb4, 0x00, 0x01, 0xfc, 0x03,
0xfc, 0xd8, 0x0c, 0x00, 0x57, 0x01, 0xf0, 0x02, 0x13, 0x03, 0xe6,
0x10, 0x00, 0x18, 0x40, 0x3e, 0x1c, 0x6c, 0x01, 0x6e, 0x01, 0xbd,
0x00, 0xe0, 0x00, 0x02, 0x48, 0x02, 0x80, 0x08, 0x12, 0x30, 0xe4,
0x3c, 0x00, 0x4e, 0x01, 0x64, 0x12, 0x80, 0x00, 0x9c, 0x15, 0xbb,
0x00, 0x00, 0x4e, 0x01, 0x01, 0x01, 0xea, 0x04, 0x12, 0x9e, 0x0f,
0xb6, 0x00, 0xb9, 0x54, 0xe2, 0x0f, 0x00, 0x80, 0x06, 0xf7, 0x10,
0x44, 0x24, 0x01, 0x28, 0x01, 0x32, 0x00, 0x3c, 0x01, 0x3c, 0x56,
0x3e, 0x00, 0x4b, 0xe4, 0x4c, 0x1c, 0x68, 0x01, 0x6a, 0x01, 0x70,
0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0xe2, 0x0c,
0x00, 0x01, 0x02, 0xee, 0x02, 0xfc, 0x03, 0x58, 0x03, 0xf7, 0x04,
0x80, 0x05, 0xfc, 0x08, 0x44, 0x09, 0xf0, 0x0f, 0x00, 0x1b, 0x80,
0x20, 0x01, 0x38, 0x1c, 0x40, 0x00, 0x40, 0x15, 0x4b, 0xf4, 0x4e,
0x1c, 0x5b, 0xf0, 0x5d, 0xf0, 0xaa, 0x00, 0xbb, 0x55, 0xbe, 0x00,
0xc0, 0x00, 0xe0, 0x08, 0xe0, 0x14, 0xec, 0x0f, 0x00, 0x4c, 0x00,
0xdc, 0x02, 0x4a, 0x05, 0x00, 0x05, 0xf0, 0x05, 0xf8, 0x06, 0x13,
0x08, 0x13, 0x0c, 0x00, 0x0e, 0x47, 0x0e, 0xf7, 0x19, 0x00, 0x20,
0x00, 0x2a, 0x01, 0x30, 0x0e, 0x32, 0x1c, 0x36, 0x00, 0x45, 0x5a,
0x59, 0xf0, 0x62, 0x0a, 0x69, 0x08, 0x72, 0x0b, 0x83, 0x59, 0xb8,
0xf0, 0xbd, 0x56, 0xcc, 0x12, 0xec, 0x17, 0xee, 0x0f, 0xf0, 0x00,
0xf8, 0x17, 0x01, 0x48, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0x10, 0x04,
0xea, 0x04, 0xf6, 0x04, 0xfc, 0x05, 0x80, 0x05, 0xe6, 0x06, 0x00,
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0x28, 0x10, 0xb1, 0x06, 0xfe, 0x60, 0x13, 0x72, 0xfe, 0xc8, 0x00,
0x8f, 0xfe, 0xc6, 0x13, 0x0e, 0xfe, 0xc8, 0x00, 0x09, 0x55, 0x08,
0x06, 0xa8, 0x72, 0xfe, 0x90, 0x01, 0xed, 0xfe, 0xd2, 0x13, 0x95,
0xaa, 0xfe, 0x43, 0xf4, 0xad, 0xfe, 0x56, 0xf0, 0xfe, 0xe4, 0x13,
0xfe, 0x04, 0xf4, 0x63, 0xfe, 0x43, 0xf4, 0x88, 0xfe, 0xf3, 0x10,
0xb0, 0x01, 0xfe, 0xae, 0x12, 0x1b, 0x50, 0xd4, 0xfe, 0x00, 0x17,
0xfe, 0x4d, 0xe4, 0x6c, 0xed, 0xfe, 0x18, 0x14, 0xa3, 0x6c, 0xfe,
0x14, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x1a, 0xed, 0xfe,
0x18, 0x14, 0xa3, 0x1a, 0x9e, 0x57, 0x95, 0x08, 0x06, 0xfe, 0xb4,
0x56, 0xfe, 0xc3, 0x58, 0x03, 0x57, 0x08, 0x0c, 0x03, 0x14, 0x06,
0x01, 0x0b, 0x25, 0xec, 0x14, 0x0c, 0x01, 0x0b, 0x25, 0xec, 0x14,
0x19, 0x01, 0x0b, 0x25, 0xec, 0x73, 0xfe, 0x89, 0x49, 0x01, 0x0b,
0x03, 0x14, 0x06, 0x01, 0x0b, 0x25, 0xb7, 0x14, 0x19, 0x01, 0x0b,
0x25, 0xb7, 0x14, 0x06, 0x01, 0x0b, 0x25, 0xb7, 0xfe, 0x89, 0x49,
0x01, 0x0b, 0x25, 0xb7, 0x73, 0xfe, 0x89, 0x4a, 0x01, 0x0b, 0x03,
0x57, 0x03, 0x21, 0xe0, 0x05, 0x06, 0xfe, 0x44, 0x13, 0xaf, 0x16,
0xe0, 0xfe, 0x49, 0xf4, 0x00, 0x4b, 0x73, 0xc6, 0x5a, 0xfe, 0x01,
0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x0b, 0x3f, 0x05, 0xfe, 0xe3,
0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0xd6, 0x14, 0x2d, 0x16, 0xf3,
0x01, 0x4c, 0x21, 0xf3, 0x05, 0x06, 0x40, 0x0a, 0x41, 0x06, 0x38,
0x03, 0x0f, 0x54, 0x12, 0x8a, 0xfe, 0x43, 0x58, 0x01, 0x15, 0x05,
0x10, 0xfe, 0x1e, 0x12, 0x48, 0xe7, 0x8e, 0x01, 0x2c, 0xfe, 0x90,
0x4d, 0xde, 0x10, 0xfe, 0xc5, 0x59, 0x01, 0x2c, 0xfe, 0x8d, 0x56,
0xb6, 0x48, 0x03, 0x48, 0x31, 0x8a, 0x01, 0x15, 0x48, 0x8e, 0x01,
0x2c, 0xe2, 0x10, 0xde, 0x10, 0x31, 0x54, 0x72, 0x1c, 0x84, 0x0e,
0x56, 0x01, 0xab, 0x03, 0x0f, 0x54, 0x12, 0x8a, 0xfe, 0xc3, 0x58,
0x01, 0x15, 0x05, 0x10, 0xfe, 0x1a, 0x12, 0x48, 0xe7, 0x8e, 0x01,
0x2c, 0xe2, 0x10, 0xfe, 0x80, 0x4d, 0xfe, 0xc5, 0x59, 0x01, 0x2c,
0x48, 0x03, 0x48, 0x31, 0x54, 0x01, 0x15, 0x48, 0x8e, 0x01, 0x2c,
0xe2, 0x10, 0xde, 0x10, 0x31, 0x54, 0x72, 0x1c, 0x84, 0x0e, 0x56,
0x01, 0xab, 0x03, 0x0f, 0x54, 0x12, 0x8a, 0xfe, 0x43, 0x58, 0x01,
0x15, 0xfe, 0x42, 0x48, 0x8e, 0x01, 0x2c, 0xfe, 0xc0, 0x5a, 0xb0,
0xfe, 0x00, 0xcd, 0xfe, 0x01, 0xcc, 0xfe, 0x4a, 0x46, 0xdc, 0x93,
0x7d, 0x05, 0x10, 0xfe, 0x2e, 0x13, 0x69, 0x54, 0xfe, 0x4d, 0xf4,
0x1c, 0xfe, 0x1c, 0x13, 0x0e, 0x56, 0x01, 0x8b, 0xaa, 0xfe, 0x40,
0x4c, 0xfe, 0xc5, 0x58, 0x01, 0x2c, 0xfe, 0x00, 0x07, 0x7d, 0x05,
0x10, 0x84, 0x69, 0x8a, 0xfe, 0x05, 0x57, 0xfe, 0x08, 0x10, 0xfe,
0x45, 0x58, 0x01, 0x2c, 0xfe, 0x8d, 0x56, 0xb6, 0xfe, 0x80, 0x4c,
0xfe, 0x05, 0x17, 0x03, 0x09, 0x10, 0x6f, 0x67, 0xfe, 0x60, 0x01,
0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xdb, 0x37,
0x94, 0xfe, 0x1a, 0x16, 0x01, 0xfe, 0x28, 0x17, 0xfe, 0x0c, 0x13,
0x87, 0x37, 0x67, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xba,
0x27, 0xfe, 0x0a, 0x16, 0xfe, 0xe2, 0x10, 0x09, 0x10, 0x6f, 0x04,
0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1a, 0xfe, 0x18, 0x58, 0x04,
0xfe, 0x66, 0x01, 0xfe, 0x19, 0x58, 0x87, 0x1a, 0xfe, 0x3c, 0x90,
0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x67, 0xfe, 0x38, 0x00,
0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x1a, 0x94, 0xfe, 0x64, 0x16,
0xfe, 0xbe, 0x14, 0x35, 0x03, 0xba, 0x27, 0xfe, 0x3c, 0x16, 0xfe,
0xa4, 0x10, 0x09, 0x10, 0x6f, 0xb6, 0xfe, 0x18, 0xdf, 0xfe, 0x19,
0xdf, 0xdb, 0x42, 0x94, 0xfe, 0x86, 0x16, 0xfe, 0x9c, 0x14, 0xfe,
0x18, 0x13, 0x87, 0x42, 0x67, 0x1e, 0xfe, 0xaf, 0x19, 0xfe, 0x98,
0xe7, 0x00, 0xa2, 0x07, 0xfe, 0x7f, 0x00, 0xfe, 0x05, 0x40, 0x03,
0xba, 0x27, 0xfe, 0x7a, 0x16, 0xfe, 0x6c, 0x10, 0x09, 0x10, 0x6f,
0xfe, 0x30, 0xbc, 0xfe, 0xb2, 0xbc, 0x87, 0xd9, 0x67, 0x1e, 0xfe,
0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xd9, 0x94, 0xfe, 0xc6, 0x16, 0xfe,
0x5c, 0x14, 0x35, 0x03, 0xba, 0x27, 0xfe, 0xb2, 0x16, 0xfe, 0x42,
0x10, 0xfe, 0x02, 0xf6, 0x10, 0x6f, 0xfe, 0x18, 0xfe, 0x5d, 0xfe,
0x19, 0xfe, 0x5e, 0xc8, 0xdb, 0x45, 0x94, 0xfe, 0xec, 0x16, 0xfe,
0x36, 0x14, 0xfe, 0x1c, 0x13, 0x87, 0x45, 0x4e, 0xfe, 0x83, 0x58,
0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10,
0x11, 0xfe, 0xdd, 0x00, 0x64, 0x2f, 0x03, 0x64, 0x2f, 0xfe, 0x12,
0x45, 0x27, 0xfe, 0xdc, 0x16, 0x17, 0x06, 0x4a, 0xf4, 0xdd, 0x02,
0x26, 0xfe, 0x39, 0xf0, 0xfe, 0x30, 0x17, 0x2d, 0x03, 0xfe, 0x7e,
0x18, 0x1b, 0x19, 0x83, 0x08, 0x0d, 0x03, 0x6f, 0x04, 0xdf, 0x1b,
0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x1d, 0x0e, 0x1c, 0x01,
0x15, 0x05, 0x10, 0x40, 0x3e, 0xfe, 0x78, 0x14, 0xfe, 0x34, 0x12,
0x50, 0x86, 0x36, 0x37, 0xbf, 0xfe, 0xe9, 0x13, 0x1d, 0x0e, 0x3d,
0x01, 0x15, 0x05, 0x10, 0x40, 0x3e, 0xfe, 0x56, 0x14, 0xe1, 0x50,
0x86, 0x36, 0x37, 0xbf, 0xfe, 0xe9, 0x13, 0x09, 0x0c, 0x03, 0xfe,
0x9c, 0xe7, 0x0c, 0x13, 0xfe, 0x15, 0x00, 0x90, 0x9f, 0x2f, 0x01,
0xea, 0x09, 0x06, 0x03, 0x0a, 0x41, 0x37, 0x38, 0x08, 0x3d, 0x09,
0x99, 0x01, 0x46, 0x11, 0x47, 0x08, 0x1c, 0x09, 0x43, 0x01, 0x7b,
0x09, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x65, 0xf7,
0x31, 0x76, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x03, 0x21,
0xbe, 0x52, 0x16, 0xbe, 0x03, 0x0e, 0xc0, 0x01, 0x15, 0xe6, 0x0e,
0x79, 0x01, 0x15, 0xfe, 0x49, 0x44, 0x27, 0xfe, 0x26, 0x18, 0x0e,
0x1c, 0x01, 0x15, 0x05, 0x10, 0x40, 0x0e, 0x56, 0x01, 0xab, 0x0e,
0x79, 0x01, 0x15, 0x52, 0x7d, 0x03, 0xfe, 0x40, 0x5e, 0xfe, 0xe2,
0x08, 0xfe, 0xc0, 0x4c, 0x21, 0x3c, 0x05, 0x10, 0xfe, 0x52, 0x12,
0x3e, 0x05, 0x00, 0xfe, 0x18, 0x12, 0xfe, 0xe1, 0x18, 0xfe, 0x19,
0xf4, 0xfe, 0x7f, 0x00, 0xd4, 0xfe, 0xe2, 0x08, 0x52, 0x3e, 0x3f,
0x05, 0x76, 0xa5, 0xfe, 0x82, 0x48, 0xfe, 0x01, 0x80, 0xfe, 0xd7,
0x10, 0xfe, 0xc4, 0x48, 0x08, 0x2a, 0x09, 0x3c, 0xfe, 0x40, 0x5f,
0x1d, 0x01, 0x46, 0x11, 0xfe, 0xdd, 0x00, 0xfe, 0x14, 0x46, 0x08,
0x2a, 0x09, 0x3c, 0x01, 0x46, 0x11, 0xfe, 0xdd, 0x00, 0xfe, 0x40,
0x4a, 0x6a, 0xfe, 0x06, 0x17, 0xfe, 0x01, 0x07, 0xfe, 0x82, 0x48,
0xfe, 0x04, 0x17, 0x03, 0xeb, 0x19, 0x74, 0xfe, 0xae, 0x18, 0x04,
0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xeb, 0xcc,
0x74, 0xfe, 0xc0, 0x18, 0x04, 0xfe, 0x92, 0x00, 0xc7, 0x1e, 0xd8,
0xeb, 0xfe, 0x0b, 0x00, 0x74, 0xfe, 0xd2, 0x18, 0x04, 0xfe, 0x94,
0x00, 0xc7, 0x1a, 0xfe, 0x08, 0x10, 0x04, 0xfe, 0x96, 0x00, 0xc7,
0x85, 0xfe, 0x4e, 0x45, 0xd1, 0xfe, 0x0a, 0x45, 0xff, 0x04, 0x68,
0x54, 0xfe, 0xf1, 0x10, 0x1b, 0x6c, 0x03, 0x05, 0x80, 0xfe, 0x5a,
0xf0, 0xfe, 0xfe, 0x18, 0x20, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10,
0x05, 0x1e, 0xfe, 0x5a, 0xf0, 0xfe, 0x0c, 0x19, 0x20, 0xcd, 0xfe,
0x26, 0x10, 0x05, 0x19, 0x83, 0x20, 0x85, 0xd8, 0x05, 0x0c, 0x83,
0x20, 0x88, 0xfe, 0x0e, 0x10, 0x05, 0x06, 0x83, 0x20, 0x55, 0xc6,
0xaf, 0x03, 0x17, 0xfe, 0x09, 0x00, 0x01, 0x44, 0x2e, 0xfe, 0x3c,
0x19, 0x04, 0x6e, 0xb0, 0x03, 0x22, 0xfe, 0x54, 0x19, 0xfe, 0x14,
0xf0, 0x0b, 0x2e, 0xfe, 0x50, 0x19, 0x03, 0xff, 0x15, 0x00, 0x00,
};
const struct adw_mcode adw_asc3550_mcode_data =
{
adw_asc3550_mcode,
0x04FFFF0E,
sizeof(adw_asc3550_mcode)
};
const u_int8_t adw_asc38C0800_mcode[] =
{
0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x00, 0xfc, 0x48,
0xe4, 0x01, 0x00, 0x18, 0xe4, 0x00, 0xf6, 0x01, 0xf6, 0x18, 0x80,
0x02, 0x00, 0x40, 0x1a, 0x00, 0xfa, 0xff, 0xff, 0x03, 0xf6, 0xff,
0x00, 0x82, 0xe7, 0x01, 0xfa, 0x9e, 0xe7, 0x09, 0xe7, 0x1a, 0x0f,
0x00, 0xea, 0x01, 0xe6, 0x03, 0x00, 0x55, 0xf0, 0x18, 0xf4, 0x1e,
0xf0, 0x3e, 0x57, 0x04, 0x00, 0x3e, 0x01, 0x85, 0xf0, 0x00, 0xe6,
0x03, 0xfc, 0x08, 0x00, 0x2c, 0x1a, 0x32, 0xf0, 0x86, 0xf0, 0xbe,
0x0d, 0xd4, 0x01, 0xd5, 0xf0, 0x00, 0xec, 0x01, 0xfc, 0x38, 0x54,
0x98, 0x57, 0xbc, 0x00, 0x0c, 0x1c, 0xb1, 0xf0, 0x3c, 0x00, 0xb4,
0x00, 0xb8, 0x0d, 0x00, 0x57, 0x01, 0xf0, 0x02, 0x13, 0x02, 0xfc,
0x03, 0xe6, 0x10, 0x00, 0x18, 0x40, 0x3e, 0x1c, 0x44, 0x13, 0x6c,
0x01, 0x6e, 0x01, 0xbd, 0x00, 0xe0, 0x00, 0x02, 0x80, 0x30, 0xe4,
0x3e, 0x00, 0x74, 0x01, 0x76, 0x01, 0x7c, 0x16, 0x80, 0x00, 0xb9,
0x54, 0xbb, 0x00, 0xee, 0x13, 0x00, 0x4e, 0x01, 0x01, 0x01, 0xea,
0x02, 0x48, 0x02, 0xfa, 0x04, 0x12, 0x08, 0x12, 0x3c, 0x56, 0x4e,
0x01, 0x5d, 0xf0, 0x7a, 0x01, 0x7e, 0x10, 0xb6, 0x00, 0xc2, 0x10,
0xee, 0x08, 0x00, 0x80, 0x05, 0xfc, 0x10, 0x44, 0x24, 0x01, 0x28,
0x01, 0x32, 0x00, 0x3c, 0x01, 0x40, 0x00, 0x4b, 0xe4, 0x4b, 0xf4,
0x4c, 0x1c, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x78,
0x01, 0x7c, 0x01, 0xbb, 0x55, 0xc2, 0x0d, 0x00, 0x01, 0x02, 0xee,
0x03, 0x58, 0x03, 0xf7, 0x03, 0xfa, 0x04, 0x80, 0x08, 0x44, 0x09,
0xf0, 0x0f, 0x00, 0x1b, 0x80, 0x20, 0x01, 0x38, 0x1c, 0x4e, 0x1c,
0x5b, 0xf0, 0x62, 0x0a, 0xaa, 0x00, 0xbe, 0x00, 0xc0, 0x00, 0xc0,
0x15, 0xcc, 0x10, 0x00, 0x4c, 0x00, 0xdc, 0x02, 0x4a, 0x04, 0xfc,
0x05, 0x00, 0x05, 0xf0, 0x05, 0xf8, 0x06, 0x13, 0x06, 0xf7, 0x08,
0x13, 0x0a, 0x10, 0x0c, 0x00, 0x0e, 0x47, 0x0e, 0xf7, 0x10, 0x0f,
0x20, 0x00, 0x20, 0x16, 0x2a, 0x01, 0x32, 0x1c, 0x36, 0x00, 0x42,
0x54, 0x44, 0x55, 0x45, 0x5a, 0x52, 0x0c, 0x59, 0xf0, 0x5c, 0xf0,
0x69, 0x08, 0x6e, 0x0b, 0x83, 0x59, 0xb8, 0xf0, 0xbd, 0x56, 0xcc,
0x18, 0xce, 0x10, 0xd8, 0x18, 0xf0, 0x00, 0x01, 0x48, 0x04, 0x10,
0x04, 0xea, 0x04, 0xf6, 0x05, 0x80, 0x05, 0xe6, 0x06, 0x00, 0x06,
0x0f, 0x06, 0x12, 0x0b, 0xf0, 0x0c, 0x10, 0x0c, 0xf0, 0x10, 0x13,
0x12, 0x10, 0x19, 0x00, 0x19, 0xe4, 0x30, 0x1c, 0x33, 0x00, 0x34,
0x00, 0x38, 0x44, 0x40, 0x5c, 0x4a, 0xe4, 0x62, 0x1a, 0x68, 0x08,
0x68, 0x54, 0x6c, 0x15, 0x70, 0x15, 0x83, 0x55, 0x83, 0x5a, 0x91,
0x44, 0xa4, 0x00, 0xac, 0x13, 0xb0, 0x57, 0xb5, 0x00, 0xb8, 0x17,
0xba, 0x00, 0xce, 0x45, 0xd0, 0x00, 0xe1, 0x00, 0xe5, 0x55, 0xe7,
0x00, 0x00, 0x54, 0x01, 0x58, 0x02, 0x10, 0x02, 0xe6, 0x03, 0xa1,
0x04, 0x13, 0x06, 0x83, 0x06, 0xf0, 0x07, 0x00, 0x0a, 0x00, 0x0a,
0x12, 0x0a, 0xf0, 0x0c, 0x12, 0x0c, 0x13, 0x0c, 0x90, 0x0e, 0x13,
0x10, 0x04, 0x10, 0x10, 0x12, 0x1c, 0x19, 0x81, 0x1a, 0x10, 0x1c,
0x00, 0x1c, 0x12, 0x1d, 0xf7, 0x1e, 0x13, 0x20, 0x1c, 0x20, 0xe7,
0x22, 0x01, 0x26, 0x01, 0x2a, 0x12, 0x2c, 0x0f, 0x30, 0xe7, 0x32,
0x15, 0x34, 0x1c, 0x36, 0x1c, 0x38, 0x12, 0x3a, 0x55, 0x3f, 0x00,
0x41, 0x58, 0x43, 0x48, 0x46, 0x1c, 0x4e, 0xe4, 0x76, 0x02, 0x77,
0x57, 0x78, 0x03, 0x89, 0x48, 0x8e, 0x90, 0x98, 0x80, 0x99, 0x00,
0xfe, 0x9c, 0xf0, 0x27, 0x02, 0xfe, 0xe0, 0x0d, 0xff, 0x10, 0x00,
0x00, 0xfe, 0xc6, 0x01, 0xfe, 0x56, 0x1a, 0x00, 0xfe, 0xc4, 0x01,
0xfe, 0x84, 0x01, 0xff, 0x03, 0x00, 0x00, 0xfe, 0x6a, 0x13, 0xfe,
0x05, 0x05, 0xff, 0x40, 0x00, 0x00, 0x0e, 0xff, 0x09, 0x00, 0x00,
0xff, 0x08, 0x01, 0x01, 0xff, 0x10, 0xff, 0xff, 0xff, 0x1f, 0x00,
0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x11, 0x00, 0x00, 0xfe, 0x78,
0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, 0xfe, 0x04, 0xf7,
0xfe, 0xc4, 0x01, 0x2e, 0x88, 0x0b, 0x01, 0xfe, 0xca, 0x0f, 0xfe,
0x04, 0xf7, 0xfe, 0xc4, 0x01, 0x88, 0x0b, 0x1c, 0x2e, 0xfe, 0x3d,
0xf0, 0xfe, 0xfc, 0x01, 0xfe, 0x20, 0xf0, 0xdc, 0x04, 0x5f, 0x4f,
0x02, 0xfe, 0xfc, 0x0d, 0x01, 0xfe, 0x5c, 0x0e, 0xfe, 0xe9, 0x12,
0x02, 0xfe, 0x08, 0x03, 0xfe, 0x28, 0x1c, 0x04, 0xfe, 0xa6, 0x00,
0xfe, 0xdd, 0x12, 0x47, 0x12, 0xfe, 0xa6, 0x00, 0xcd, 0xfe, 0x48,
0xf0, 0xfe, 0x80, 0x02, 0xfe, 0x49, 0xf0, 0xfe, 0x9a, 0x02, 0xfe,
0x4a, 0xf0, 0xfe, 0xb8, 0x02, 0xfe, 0x46, 0xf0, 0xfe, 0x4a, 0x02,
0xfe, 0x47, 0xf0, 0xfe, 0x50, 0x02, 0xfe, 0x43, 0xf0, 0xfe, 0x3e,
0x02, 0xfe, 0x44, 0xf0, 0xfe, 0x42, 0x02, 0xfe, 0x45, 0xf0, 0xfe,
0x46, 0x02, 0x09, 0x0b, 0xa4, 0x09, 0x06, 0x12, 0xc1, 0x02, 0x27,
0xfe, 0x00, 0x1c, 0xfe, 0xf1, 0x10, 0xfe, 0x02, 0x1c, 0xfe, 0xed,
0x10, 0xfe, 0x1e, 0x1c, 0xfe, 0xe9, 0x10, 0x01, 0xfe, 0x2c, 0x18,
0xfe, 0xe7, 0x10, 0xfe, 0x06, 0xfc, 0xfe, 0xa8, 0x00, 0x0f, 0x7c,
0x01, 0xaa, 0x02, 0x27, 0x17, 0x5e, 0x4c, 0xc4, 0x01, 0xfe, 0x40,
0x10, 0x0f, 0x7c, 0x01, 0x8e, 0xfe, 0xbd, 0x10, 0x0f, 0x7c, 0x01,
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0x55, 0x29, 0xfc, 0x05, 0x06, 0x50, 0x0a, 0x41, 0x06, 0x39, 0x03,
0x0d, 0x5d, 0x12, 0x91, 0xfe, 0x43, 0x58, 0x01, 0x15, 0x05, 0x10,
0xfe, 0x1e, 0x12, 0x4a, 0xf3, 0x96, 0x01, 0x49, 0xfe, 0x90, 0x4d,
0xe6, 0x10, 0xfe, 0xc5, 0x59, 0x01, 0x49, 0xfe, 0x8d, 0x56, 0xbf,
0x4a, 0x03, 0x4a, 0x21, 0x91, 0x01, 0x15, 0x4a, 0x96, 0x01, 0x49,
0xeb, 0x10, 0xe6, 0x10, 0x21, 0x5d, 0x62, 0x1e, 0x89, 0x0f, 0x5f,
0x01, 0xaa, 0x03, 0x0d, 0x5d, 0x12, 0x91, 0xfe, 0xc3, 0x58, 0x01,
0x15, 0x05, 0x10, 0xfe, 0x1a, 0x12, 0x4a, 0xf3, 0x96, 0x01, 0x49,
0xeb, 0x10, 0xfe, 0x80, 0x4d, 0xfe, 0xc5, 0x59, 0x01, 0x49, 0x4a,
0x03, 0x4a, 0x21, 0x5d, 0x01, 0x15, 0x4a, 0x96, 0x01, 0x49, 0xeb,
0x10, 0xe6, 0x10, 0x21, 0x5d, 0x62, 0x1e, 0x89, 0x0f, 0x5f, 0x01,
0xaa, 0x03, 0x0d, 0x5d, 0x12, 0x91, 0xfe, 0x43, 0x58, 0x01, 0x15,
0xfe, 0x42, 0x48, 0x96, 0x01, 0x49, 0xfe, 0xc0, 0x5a, 0xb7, 0xfe,
0x00, 0xcd, 0xfe, 0x01, 0xcc, 0xfe, 0x4a, 0x46, 0xe4, 0x9c, 0x80,
0x05, 0x10, 0xfe, 0x2e, 0x13, 0x5a, 0x5d, 0xfe, 0x4d, 0xf4, 0x1e,
0xfe, 0x1c, 0x13, 0x0f, 0x5f, 0x01, 0x8e, 0xb0, 0xfe, 0x40, 0x4c,
0xfe, 0xc5, 0x58, 0x01, 0x49, 0xfe, 0x00, 0x07, 0x80, 0x05, 0x10,
0x89, 0x5a, 0x91, 0xfe, 0x05, 0x57, 0xfe, 0x08, 0x10, 0xfe, 0x45,
0x58, 0x01, 0x49, 0xfe, 0x8d, 0x56, 0xbf, 0xfe, 0x80, 0x4c, 0xfe,
0x05, 0x17, 0x03, 0x09, 0x10, 0x77, 0x6f, 0xfe, 0x60, 0x01, 0xfe,
0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xe3, 0x38, 0x9d,
0xfe, 0xfa, 0x16, 0x01, 0xfe, 0x08, 0x18, 0xd9, 0x8d, 0x38, 0x6f,
0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xc0, 0x28, 0xfe, 0xea,
0x16, 0xfe, 0xe2, 0x10, 0x09, 0x10, 0x77, 0x04, 0xfe, 0x64, 0x01,
0xfe, 0x00, 0xf4, 0x22, 0xfe, 0x18, 0x58, 0x04, 0xfe, 0x66, 0x01,
0xfe, 0x19, 0x58, 0x8d, 0x22, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4,
0x06, 0xfe, 0x3c, 0x50, 0x6f, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79,
0xfe, 0x1c, 0xf7, 0x22, 0x9d, 0xfe, 0x44, 0x17, 0xfe, 0xbe, 0x14,
0x35, 0x03, 0xc0, 0x28, 0xfe, 0x1c, 0x17, 0xfe, 0xa4, 0x10, 0x09,
0x10, 0x77, 0xbf, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xdf, 0xe3, 0x30,
0x9d, 0xfe, 0x66, 0x17, 0xfe, 0x9c, 0x14, 0xfe, 0x18, 0x13, 0x8d,
0x30, 0x6f, 0x1d, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00, 0xa7,
0x07, 0xfe, 0x7f, 0x00, 0xfe, 0x05, 0x40, 0x03, 0xc0, 0x28, 0xfe,
0x5a, 0x17, 0xfe, 0x6c, 0x10, 0x09, 0x10, 0x77, 0xfe, 0x30, 0xbc,
0xfe, 0xb2, 0xbc, 0x8d, 0xe1, 0x6f, 0x1d, 0xfe, 0x0f, 0x79, 0xfe,
0x1c, 0xf7, 0xe1, 0x9d, 0xfe, 0xa6, 0x17, 0xfe, 0x5c, 0x14, 0x35,
0x03, 0xc0, 0x28, 0xfe, 0x92, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02,
0xf6, 0x10, 0x77, 0xfe, 0x18, 0xfe, 0x66, 0xfe, 0x19, 0xfe, 0x67,
0xd0, 0xe3, 0x46, 0x9d, 0xfe, 0xcc, 0x17, 0xfe, 0x36, 0x14, 0xfe,
0x1c, 0x13, 0x8d, 0x46, 0x47, 0xfe, 0x83, 0x58, 0xfe, 0xaf, 0x19,
0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd,
0x00, 0x6d, 0x31, 0x03, 0x6d, 0x31, 0xfe, 0x12, 0x45, 0x28, 0xfe,
0xbc, 0x17, 0x17, 0x06, 0x4c, 0xfe, 0x9b, 0x00, 0xe5, 0x02, 0x27,
0xfe, 0x39, 0xf0, 0xfe, 0x10, 0x18, 0x2b, 0x03, 0xfe, 0x7e, 0x18,
0x1a, 0x18, 0x87, 0x08, 0x0e, 0x03, 0x77, 0x04, 0xe7, 0x1a, 0x06,
0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x1c, 0x0f, 0x1e, 0x01, 0x15,
0x05, 0x10, 0x50, 0x4d, 0xfe, 0x78, 0x14, 0xfe, 0x34, 0x12, 0x59,
0x8c, 0x37, 0x38, 0xc7, 0xfe, 0xe9, 0x13, 0x1c, 0x0f, 0x3f, 0x01,
0x15, 0x05, 0x10, 0x50, 0x4d, 0xfe, 0x56, 0x14, 0xe9, 0x59, 0x8c,
0x37, 0x38, 0xc7, 0xfe, 0xe9, 0x13, 0x09, 0x0b, 0x03, 0xfe, 0x9c,
0xe7, 0x0b, 0x13, 0xfe, 0x15, 0x00, 0x7a, 0xa5, 0x31, 0x01, 0xea,
0x09, 0x06, 0x03, 0x0a, 0x41, 0x38, 0x39, 0x08, 0x3f, 0x09, 0xa2,
0x01, 0x45, 0x11, 0x48, 0x08, 0x1e, 0x09, 0x52, 0x01, 0x7e, 0x09,
0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x36, 0xfe, 0xa8,
0x00, 0x21, 0x7b, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x03,
0x29, 0xc6, 0x5b, 0x16, 0xc6, 0x03, 0x0f, 0xc8, 0x01, 0x15, 0xf2,
0x0f, 0x7d, 0x01, 0x15, 0xfe, 0x49, 0x44, 0x28, 0xfe, 0x06, 0x19,
0x0f, 0x1e, 0x01, 0x15, 0x05, 0x10, 0x50, 0x0f, 0x5f, 0x01, 0xaa,
0x0f, 0x7d, 0x01, 0x15, 0x5b, 0x80, 0x03, 0xfe, 0x40, 0x5e, 0xfe,
0xe2, 0x08, 0xfe, 0xc0, 0x4c, 0x29, 0x3e, 0x05, 0x10, 0xfe, 0x52,
0x12, 0x4d, 0x05, 0x00, 0xfe, 0x18, 0x12, 0xfe, 0xe1, 0x18, 0xfe,
0x19, 0xf4, 0xfe, 0x7f, 0x00, 0xaf, 0xfe, 0xe2, 0x08, 0x5b, 0x4d,
0x40, 0x05, 0x7b, 0xab, 0xfe, 0x82, 0x48, 0xfe, 0x01, 0x80, 0xfe,
0xd7, 0x10, 0xfe, 0xc4, 0x48, 0x08, 0x2d, 0x09, 0x3e, 0xfe, 0x40,
0x5f, 0x1c, 0x01, 0x45, 0x11, 0xfe, 0xdd, 0x00, 0xfe, 0x14, 0x46,
0x08, 0x2d, 0x09, 0x3e, 0x01, 0x45, 0x11, 0xfe, 0xdd, 0x00, 0xfe,
0x40, 0x4a, 0x72, 0xfe, 0x06, 0x17, 0xfe, 0x01, 0x07, 0xfe, 0x82,
0x48, 0xfe, 0x04, 0x17, 0x03, 0xf5, 0x18, 0x79, 0xfe, 0x8e, 0x19,
0x04, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xf5,
0xd4, 0x79, 0xfe, 0xa0, 0x19, 0x04, 0xfe, 0x92, 0x00, 0xcf, 0x1d,
0xe0, 0xf5, 0xfe, 0x0b, 0x00, 0x79, 0xfe, 0xb2, 0x19, 0x04, 0xfe,
0x94, 0x00, 0xcf, 0x22, 0xfe, 0x08, 0x10, 0x04, 0xfe, 0x96, 0x00,
0xcf, 0x8b, 0xfe, 0x4e, 0x45, 0xd8, 0xfe, 0x0a, 0x45, 0xff, 0x04,
0x68, 0x54, 0xfe, 0xf1, 0x10, 0x1a, 0x74, 0xfe, 0x08, 0x1c, 0xfe,
0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00, 0x04,
0xd8, 0xfe, 0x48, 0xf4, 0x18, 0x99, 0xfe, 0xe6, 0x19, 0x08, 0x18,
0x03, 0x05, 0x84, 0xfe, 0x5a, 0xf0, 0xfe, 0xf6, 0x19, 0x20, 0xfe,
0x09, 0x00, 0xfe, 0x34, 0x10, 0x05, 0x1d, 0xfe, 0x5a, 0xf0, 0xfe,
0x04, 0x1a, 0x20, 0xd5, 0xfe, 0x26, 0x10, 0x05, 0x18, 0x87, 0x20,
0x8b, 0xe0, 0x05, 0x0b, 0x87, 0x20, 0xb1, 0xfe, 0x0e, 0x10, 0x05,
0x06, 0x87, 0x20, 0x5e, 0xce, 0xb6, 0x03, 0x17, 0xfe, 0x09, 0x00,
0x01, 0x3b, 0x2f, 0xfe, 0x34, 0x1a, 0x04, 0x76, 0xb7, 0x03, 0x1b,
0xfe, 0x54, 0x1a, 0xfe, 0x14, 0xf0, 0x0c, 0x2f, 0xfe, 0x48, 0x1a,
0x1b, 0xfe, 0x54, 0x1a, 0xfe, 0x82, 0xf0, 0xfe, 0x4c, 0x1a, 0x03,
0xff, 0x15, 0x00, 0x00,
};
const struct adw_mcode adw_asc38C0800_mcode_data =
{
adw_asc38C0800_mcode,
0x053503A5,
sizeof(adw_asc38C0800_mcode)
};

135
sys/dev/advansys/adwmcode.h
View File

@ -1,135 +0,0 @@
/*-
* Exported interface to downloadable microcode for AdvanSys SCSI Adapters
*
* $FreeBSD$
*
* Obtained from:
*
* Copyright (c) 1995-1999 Advanced System Products, Inc.
* All Rights Reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that redistributions of source
* code retain the above copyright notice and this comment without
* modification.
*/
#ifndef _ADMCODE_H_
#define _ADMCODE_H_
struct adw_mcode
{
const u_int8_t* mcode_buf;
const u_int32_t mcode_chksum;
const u_int16_t mcode_size;
};
extern const struct adw_mcode adw_asc3550_mcode_data;
extern const struct adw_mcode adw_asc38C0800_mcode_data;
/*
* Fixed LRAM locations of microcode operating variables.
*/
#define ADW_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
#define ADW_MC_CODE_END_ADDR 0x002A /* microcode end address */
#define ADW_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
#define ADW_MC_VERSION_DATE 0x0038 /* microcode version */
#define ADW_MC_VERSION_NUM 0x003A /* microcode number */
#define ADW_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
#define ADW_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
#define ADW_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
#define ADW_MC_BIOS_VERSION 0x005A /* BIOS Version (2 Bytes) */
#define ADW_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
#define ADW_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
#define ADW_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
#define ADW_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
#define ADW_MC_CHIP_TYPE 0x009A
#define ADW_MC_INTRB_CODE 0x009B
#define ADW_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
#define ADW_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected Bus Reset. */
#define ADW_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure.*/
#define ADW_ASYNC_HOST_SCSI_BUS_RESET 0x80 /*
* Host Initiated
* SCSI Bus Reset.
*/
#define ADW_MC_WDTR_ABLE_BIOS_31 0x0120
#define ADW_MC_WDTR_ABLE 0x009C
#define ADW_MC_SDTR_ABLE 0x009E
#define ADW_MC_TAGQNG_ABLE 0x00A0
#define ADW_MC_DISC_ENABLE 0x00A2
#define ADW_MC_IDLE_CMD_STATUS 0x00A4
#define ADW_MC_IDLE_CMD 0x00A6
#define ADW_MC_IDLE_CMD_PARAMETER 0x00A8
#define ADW_MC_DEFAULT_SCSI_CFG0 0x00AC
#define ADW_MC_DEFAULT_SCSI_CFG1 0x00AE
#define ADW_MC_DEFAULT_MEM_CFG 0x00B0
#define ADW_MC_DEFAULT_SEL_MASK 0x00B2
#define ADW_MC_RISC_NEXT_READY 0x00B4
#define ADW_MC_RISC_NEXT_DONE 0x00B5
#define ADW_MC_SDTR_DONE 0x00B6
#define ADW_MC_NUMBER_OF_QUEUED_CMD 0x00C0
#define ADW_MC_NUMBER_OF_MAX_CMD 0x00D0
#define ADW_MC_DEVICE_HSHK_CFG_TABLE 0x0100
#define ADW_HSHK_CFG_WIDE_XFR 0x8000
#define ADW_HSHK_CFG_RATE_MASK 0x7F00
#define ADW_HSHK_CFG_RATE_SHIFT 8
#define ADW_HSHK_CFG_OFFSET 0x001F
#define ADW_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
#define ADW_MC_CONTROL_IGN_PERR 0x0001 /* Ignore DMA Parity Errors */
#define ADW_MC_WDTR_DONE 0x0124
#define ADW_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
#define ADW_MC_ICQ 0x0160
#define ADW_MC_IRQ 0x0164
/* ADW_SCSI_REQ_Q 'cntl' field values */
#define ADW_QC_DATA_CHECK 0x01 /* Require ADW_QC_DATA_OUT set or clear. */
#define ADW_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
#define ADW_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
#define ADW_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
#define ADW_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request.XXXTBD */
#define ADW_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
#define ADW_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
#define ADW_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request.*/
#define ADW_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
#define ADW_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request.*/
/*
* Note: If a Tag Message is to be sent and neither ADW_QSC_HEAD_TAG or
* ADW_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
*/
#define ADW_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
#define ADW_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
struct adw_carrier
{
u_int32_t carr_offset; /* Carrier byte offset into our array */
u_int32_t carr_ba; /* Carrier Bus Address */
u_int32_t areq_ba; /* SCSI Req Queue Bus Address */
u_int32_t next_ba;
#define ADW_RQ_DONE 0x00000001
#define ADW_CQ_STOPPER 0x00000000
#define ADW_NEXT_BA_MASK 0xFFFFFFF0
};
/*
* Microcode idle loop commands
*/
typedef enum {
ADW_IDLE_CMD_COMPLETED = 0x0000,
ADW_IDLE_CMD_STOP_CHIP = 0x0001,
ADW_IDLE_CMD_STOP_CHIP_SEND_INT = 0x0002,
ADW_IDLE_CMD_SEND_INT = 0x0004,
ADW_IDLE_CMD_ABORT = 0x0008,
ADW_IDLE_CMD_DEVICE_RESET = 0x0010,
ADW_IDLE_CMD_SCSI_RESET_START = 0x0020,
ADW_IDLE_CMD_SCSI_RESET_END = 0x0040,
ADW_IDLE_CMD_SCSIREQ = 0x0080
} adw_idle_cmd_t;
typedef enum {
ADW_IDLE_CMD_FAILURE = 0x0000,
ADW_IDLE_CMD_SUCCESS = 0x0001
} adw_idle_cmd_status_t;
#endif /* _ADMCODE_H_ */

56
sys/dev/advansys/adwvar.h
View File

@ -1,56 +0,0 @@
/*-
* Generic driver definitions and exported functions for the Advanced
* Systems Inc. Second Generation SCSI controllers
*
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 1998, 1999, 2000 Justin Gibbs.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
* All rights reserved.
*
* $FreeBSD$
*/
#ifndef _ADWVAR_H_
#define _ADWVAR_H_
#include <dev/advansys/adwlib.h>
struct adw_softc * adw_alloc(device_t dev, struct resource *regs,
int regs_type, int regs_id);
void adw_map(void *arg, bus_dma_segment_t *segs,
int nseg, int error);
void adw_free(struct adw_softc *adw);
int adw_init(struct adw_softc *adw);
void adw_intr(void *arg);
int adw_attach(struct adw_softc *adw);
void adw_done(struct adw_softc *adw, union ccb* ccb,
u_int done_stat, u_int host_stat,
u_int scsi_stat, u_int q_no);
void adw_timeout(void *arg);
#endif /* _ADWVAR_H_ */

6
sys/kern/Make.tags.inc
View File

@ -10,8 +10,7 @@ SYS?= ${.CURDIR}/..
# win when there is a struct tag with the same name (e.g., vmmeter). The
# better solution would be for ctags to generate "struct vmmeter" tags.
COMM= ${SYS}/dev/advansys/*.[ch] \
${SYS}/sys/vnode.h \
COMM= ${SYS}/sys/vnode.h \
${SYS}/dev/alc/*.[ch] \
${SYS}/dev/buslogic/*.[ch] \
${SYS}/dev/dpt/*.[ch] \
@ -67,8 +66,7 @@ COMMDIR1= ${SYS}/conf \
${SYS}/vm \
${SYS}/sys
COMMDIR2= ${SYS}/dev/advansys \
${SYS}/dev/alc \
COMMDIR2= ${SYS}/dev/alc \
${SYS}/dev/buslogic \
${SYS}/dev/dpt \
${SYS}/dev/en \