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This commit was generated by cvs2svn to compensate for changes in r84865,

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This commit is contained in:
David E. O'Brien 2001-10-13 01:47:52 +00:00
commit 45a7ac086f
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=84866
36 changed files with 43264 additions and 36 deletions
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201
contrib/binutils/bfd/coff-ia64.c Normal file
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/* BFD back-end for HP/Intel IA-64 COFF files.
Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by David Mosberger <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
#include "coff/ia64.h"
#include "coff/internal.h"
#include "coff/pe.h"
#include "libcoff.h"
#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (2)
/* The page size is a guess based on ELF. */
#define COFF_PAGE_SIZE 0x1000
static reloc_howto_type howto_table[] =
{
EMPTY_HOWTO (0),
};
#define BADMAG(x) IA64BADMAG(x)
#define IA64 1 /* Customize coffcode.h */
#ifdef COFF_WITH_pep
# undef AOUTSZ
# define AOUTSZ PEPAOUTSZ
# define PEAOUTHDR PEPAOUTHDR
#endif
#define RTYPE2HOWTO(cache_ptr, dst) \
(cache_ptr)->howto = howto_table + (dst)->r_type;
#ifdef COFF_WITH_PE
/* Return true if this relocation should
appear in the output .reloc section. */
static boolean
in_reloc_p(abfd, howto)
bfd * abfd ATTRIBUTE_UNUSED;
reloc_howto_type *howto ATTRIBUTE_UNUSED;
{
return 0; /* We don't do relocs for now... */
}
#endif
#include "coffcode.h"
static const bfd_target *
ia64coff_object_p (abfd)
bfd *abfd;
{
#ifdef COFF_IMAGE_WITH_PE
{
struct external_PEI_DOS_hdr dos_hdr;
struct external_PEI_IMAGE_hdr image_hdr;
file_ptr offset;
if (bfd_seek (abfd, 0x00, SEEK_SET) != 0
|| bfd_read (&dos_hdr, 1, sizeof (dos_hdr), abfd)
!= sizeof (dos_hdr))
{
if (bfd_get_error () != bfd_error_system_call)
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
/* There are really two magic numbers involved; the magic number
that says this is a NT executable (PEI) and the magic number
that determines the architecture. The former is DOSMAGIC,
stored in the e_magic field. The latter is stored in the
f_magic field. If the NT magic number isn't valid, the
architecture magic number could be mimicked by some other
field (specifically, the number of relocs in section 3). Since
this routine can only be called correctly for a PEI file, check
the e_magic number here, and, if it doesn't match, clobber the
f_magic number so that we don't get a false match. */
if (bfd_h_get_16 (abfd, (bfd_byte *) dos_hdr.e_magic) != DOSMAGIC)
{
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
offset = bfd_h_get_32 (abfd, (bfd_byte *) dos_hdr.e_lfanew);
if (bfd_seek (abfd, (file_ptr) offset, SEEK_SET) != 0
|| bfd_read (&image_hdr, 1, sizeof (image_hdr), abfd)
!= sizeof (image_hdr))
{
if (bfd_get_error () != bfd_error_system_call)
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
if (bfd_h_get_32 (abfd, (bfd_byte *) image_hdr.nt_signature)
!= 0x4550)
{
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
/* Here is the hack. coff_object_p wants to read filhsz bytes to
pick up the COFF header for PE, see "struct external_PEI_filehdr"
in include/coff/pe.h. We adjust so that that will work. */
if (bfd_seek (abfd,
(file_ptr) (offset - sizeof (dos_hdr)),
SEEK_SET)
!= 0)
{
if (bfd_get_error () != bfd_error_system_call)
bfd_set_error (bfd_error_wrong_format);
return NULL;
}
}
#endif
return coff_object_p (abfd);
}
const bfd_target
#ifdef TARGET_SYM
TARGET_SYM =
#else
ia64coff_vec =
#endif
{
#ifdef TARGET_NAME
TARGET_NAME,
#else
"coff-ia64", /* name */
#endif
bfd_target_coff_flavour,
BFD_ENDIAN_LITTLE, /* data byte order is little */
BFD_ENDIAN_LITTLE, /* header byte order is little */
(HAS_RELOC | EXEC_P | /* object flags */
HAS_LINENO | HAS_DEBUG |
HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
#ifndef COFF_WITH_PE
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC /* section flags */
| SEC_CODE | SEC_DATA),
#else
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC /* section flags */
| SEC_CODE | SEC_DATA
| SEC_LINK_ONCE | SEC_LINK_DUPLICATES),
#endif
#ifdef TARGET_UNDERSCORE
TARGET_UNDERSCORE, /* leading underscore */
#else
0, /* leading underscore */
#endif
'/', /* ar_pad_char */
15, /* ar_max_namelen */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* data */
bfd_getl64, bfd_getl_signed_64, bfd_putl64,
bfd_getl32, bfd_getl_signed_32, bfd_putl32,
bfd_getl16, bfd_getl_signed_16, bfd_putl16, /* hdrs */
/* Note that we allow an object file to be treated as a core file as well. */
{_bfd_dummy_target, ia64coff_object_p, /* bfd_check_format */
bfd_generic_archive_p, ia64coff_object_p},
{bfd_false, coff_mkobject, _bfd_generic_mkarchive, /* bfd_set_format */
bfd_false},
{bfd_false, coff_write_object_contents, /* bfd_write_contents */
_bfd_write_archive_contents, bfd_false},
BFD_JUMP_TABLE_GENERIC (coff),
BFD_JUMP_TABLE_COPY (coff),
BFD_JUMP_TABLE_CORE (_bfd_nocore),
BFD_JUMP_TABLE_ARCHIVE (_bfd_archive_coff),
BFD_JUMP_TABLE_SYMBOLS (coff),
BFD_JUMP_TABLE_RELOCS (coff),
BFD_JUMP_TABLE_WRITE (coff),
BFD_JUMP_TABLE_LINK (coff),
BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
NULL,
COFF_SWAP_TABLE
};

2358
contrib/binutils/bfd/coff-rs6000.c Normal file
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589
contrib/binutils/bfd/cpu-ia64-opc.c Normal file
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/* Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* Logically, this code should be part of libopcode but since some of
the operand insertion/extraction functions help bfd to implement
relocations, this code is included as part of elf64-ia64.c. This
avoids circular dependencies between libopcode and libbfd and also
obviates the need for applications to link in libopcode when all
they really want is libbfd.
--davidm Mon Apr 13 22:14:02 1998 */
#include "../opcodes/ia64-opc.h"
#define NELEMS(a) ((int) (sizeof (a) / sizeof ((a)[0])))
static const char*
ins_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
{
return "internal error---this shouldn't happen";
}
static const char*
ext_rsvd (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
{
return "internal error---this shouldn't happen";
}
static const char*
ins_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn value ATTRIBUTE_UNUSED, ia64_insn *code ATTRIBUTE_UNUSED)
{
return 0;
}
static const char*
ext_const (const struct ia64_operand *self ATTRIBUTE_UNUSED,
ia64_insn code ATTRIBUTE_UNUSED, ia64_insn *valuep ATTRIBUTE_UNUSED)
{
return 0;
}
static const char*
ins_reg (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value >= 1u << self->field[0].bits)
return "register number out of range";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_reg (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift)
& ((1u << self->field[0].bits) - 1));
return 0;
}
static const char*
ins_immu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
ia64_insn new = 0;
int i;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
new |= ((value & ((((ia64_insn) 1) << self->field[i].bits) - 1))
<< self->field[i].shift);
value >>= self->field[i].bits;
}
if (value)
return "integer operand out of range";
*code |= new;
return 0;
}
static const char*
ext_immu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
BFD_HOST_U_64_BIT value = 0;
int i, bits = 0, total = 0;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
bits = self->field[i].bits;
value |= ((code >> self->field[i].shift)
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
total += bits;
}
*valuep = value;
return 0;
}
static const char*
ins_immus8 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value & 0x7)
return "value not an integer multiple of 8";
return ins_immu (self, value >> 3, code);
}
static const char*
ext_immus8 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *result;
result = ext_immu (self, code, valuep);
if (result)
return result;
*valuep = *valuep << 3;
return 0;
}
static const char*
ins_imms_scaled (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code, int scale)
{
BFD_HOST_64_BIT svalue = value, sign_bit = 0;
ia64_insn new = 0;
int i;
svalue >>= scale;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
new |= ((svalue & ((((ia64_insn) 1) << self->field[i].bits) - 1))
<< self->field[i].shift);
sign_bit = (svalue >> (self->field[i].bits - 1)) & 1;
svalue >>= self->field[i].bits;
}
if ((!sign_bit && svalue != 0) || (sign_bit && svalue != -1))
return "integer operand out of range";
*code |= new;
return 0;
}
static const char*
ext_imms_scaled (const struct ia64_operand *self, ia64_insn code,
ia64_insn *valuep, int scale)
{
int i, bits = 0, total = 0, shift;
BFD_HOST_64_BIT val = 0;
for (i = 0; i < NELEMS (self->field) && self->field[i].bits; ++i)
{
bits = self->field[i].bits;
val |= ((code >> self->field[i].shift)
& ((((BFD_HOST_U_64_BIT) 1) << bits) - 1)) << total;
total += bits;
}
/* sign extend: */
shift = 8*sizeof (val) - total;
val = (val << shift) >> shift;
*valuep = (val << scale);
return 0;
}
static const char*
ins_imms (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ins_immsu4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
if (value == (BFD_HOST_U_64_BIT) 0x100000000)
value = 0;
else
value = (((BFD_HOST_64_BIT)value << 32) >> 32);
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ext_imms (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 0);
}
static const char*
ins_immsm1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ins_immsm1u4 (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code)
{
if (value == (BFD_HOST_U_64_BIT) 0x100000000)
value = 0;
else
value = (((BFD_HOST_64_BIT)value << 32) >> 32);
--value;
return ins_imms_scaled (self, value, code, 0);
}
static const char*
ext_immsm1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *res = ext_imms_scaled (self, code, valuep, 0);
++*valuep;
return res;
}
static const char*
ins_imms1 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 1);
}
static const char*
ext_imms1 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 1);
}
static const char*
ins_imms4 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 4);
}
static const char*
ext_imms4 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 4);
}
static const char*
ins_imms16 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
return ins_imms_scaled (self, value, code, 16);
}
static const char*
ext_imms16 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
return ext_imms_scaled (self, code, valuep, 16);
}
static const char*
ins_cimmu (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
ia64_insn mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
return ins_immu (self, value ^ mask, code);
}
static const char*
ext_cimmu (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
const char *result;
ia64_insn mask;
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
result = ext_immu (self, code, valuep);
if (!result)
{
mask = (((ia64_insn) 1) << self->field[0].bits) - 1;
*valuep ^= mask;
}
return result;
}
static const char*
ins_cnt (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
if (value >= ((BFD_HOST_U_64_BIT) 1) << self->field[0].bits)
return "count out of range";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift)
& ((((BFD_HOST_U_64_BIT) 1) << self->field[0].bits) - 1)) + 1;
return 0;
}
static const char*
ins_cnt2b (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
--value;
if (value > 2)
return "count must be in range 1..3";
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt2b (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
*valuep = ((code >> self->field[0].shift) & 0x3) + 1;
return 0;
}
static const char*
ins_cnt2c (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
switch (value)
{
case 0: value = 0; break;
case 7: value = 1; break;
case 15: value = 2; break;
case 16: value = 3; break;
default: return "count must be 0, 7, 15, or 16";
}
*code |= value << self->field[0].shift;
return 0;
}
static const char*
ext_cnt2c (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
ia64_insn value;
value = (code >> self->field[0].shift) & 0x3;
switch (value)
{
case 0: value = 0; break;
case 1: value = 7; break;
case 2: value = 15; break;
case 3: value = 16; break;
}
*valuep = value;
return 0;
}
static const char*
ins_inc3 (const struct ia64_operand *self, ia64_insn value, ia64_insn *code)
{
BFD_HOST_64_BIT val = value;
BFD_HOST_U_64_BIT sign = 0;
if (val < 0)
{
sign = 0x4;
value = -value;
}
switch (value)
{
case 1: value = 3; break;
case 4: value = 2; break;
case 8: value = 1; break;
case 16: value = 0; break;
default: return "count must be +/- 1, 4, 8, or 16";
}
*code |= (sign | value) << self->field[0].shift;
return 0;
}
static const char*
ext_inc3 (const struct ia64_operand *self, ia64_insn code, ia64_insn *valuep)
{
BFD_HOST_64_BIT val;
int negate;
val = (code >> self->field[0].shift) & 0x7;
negate = val & 0x4;
switch (val & 0x3)
{
case 0: val = 16; break;
case 1: val = 8; break;
case 2: val = 4; break;
case 3: val = 1; break;
}
if (negate)
val = -val;
*valuep = val;
return 0;
}
#define CST IA64_OPND_CLASS_CST
#define REG IA64_OPND_CLASS_REG
#define IND IA64_OPND_CLASS_IND
#define ABS IA64_OPND_CLASS_ABS
#define REL IA64_OPND_CLASS_REL
#define SDEC IA64_OPND_FLAG_DECIMAL_SIGNED
#define UDEC IA64_OPND_FLAG_DECIMAL_UNSIGNED
const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT] =
{
/* constants: */
{ CST, ins_const, ext_const, "NIL", {{ 0, 0}}, 0, "<none>" },
{ CST, ins_const, ext_const, "ar.ccv", {{ 0, 0}}, 0, "ar.ccv" },
{ CST, ins_const, ext_const, "ar.pfs", {{ 0, 0}}, 0, "ar.pfs" },
{ CST, ins_const, ext_const, "1", {{ 0, 0}}, 0, "1" },
{ CST, ins_const, ext_const, "8", {{ 0, 0}}, 0, "8" },
{ CST, ins_const, ext_const, "16", {{ 0, 0}}, 0, "16" },
{ CST, ins_const, ext_const, "r0", {{ 0, 0}}, 0, "r0" },
{ CST, ins_const, ext_const, "ip", {{ 0, 0}}, 0, "ip" },
{ CST, ins_const, ext_const, "pr", {{ 0, 0}}, 0, "pr" },
{ CST, ins_const, ext_const, "pr.rot", {{ 0, 0}}, 0, "pr.rot" },
{ CST, ins_const, ext_const, "psr", {{ 0, 0}}, 0, "psr" },
{ CST, ins_const, ext_const, "psr.l", {{ 0, 0}}, 0, "psr.l" },
{ CST, ins_const, ext_const, "psr.um", {{ 0, 0}}, 0, "psr.um" },
/* register operands: */
{ REG, ins_reg, ext_reg, "ar", {{ 7, 20}}, 0, /* AR3 */
"an application register" },
{ REG, ins_reg, ext_reg, "b", {{ 3, 6}}, 0, /* B1 */
"a branch register" },
{ REG, ins_reg, ext_reg, "b", {{ 3, 13}}, 0, /* B2 */
"a branch register"},
{ REG, ins_reg, ext_reg, "cr", {{ 7, 20}}, 0, /* CR */
"a control register"},
{ REG, ins_reg, ext_reg, "f", {{ 7, 6}}, 0, /* F1 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 13}}, 0, /* F2 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 20}}, 0, /* F3 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "f", {{ 7, 27}}, 0, /* F4 */
"a floating-point register" },
{ REG, ins_reg, ext_reg, "p", {{ 6, 6}}, 0, /* P1 */
"a predicate register" },
{ REG, ins_reg, ext_reg, "p", {{ 6, 27}}, 0, /* P2 */
"a predicate register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 6}}, 0, /* R1 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 13}}, 0, /* R2 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 7, 20}}, 0, /* R3 */
"a general register" },
{ REG, ins_reg, ext_reg, "r", {{ 2, 20}}, 0, /* R3_2 */
"a general register r0-r3" },
/* indirect operands: */
{ IND, ins_reg, ext_reg, "cpuid", {{7, 20}}, 0, /* CPUID_R3 */
"a cpuid register" },
{ IND, ins_reg, ext_reg, "dbr", {{7, 20}}, 0, /* DBR_R3 */
"a dbr register" },
{ IND, ins_reg, ext_reg, "dtr", {{7, 20}}, 0, /* DTR_R3 */
"a dtr register" },
{ IND, ins_reg, ext_reg, "itr", {{7, 20}}, 0, /* ITR_R3 */
"an itr register" },
{ IND, ins_reg, ext_reg, "ibr", {{7, 20}}, 0, /* IBR_R3 */
"an ibr register" },
{ IND, ins_reg, ext_reg, "", {{7, 20}}, 0, /* MR3 */
"an indirect memory address" },
{ IND, ins_reg, ext_reg, "msr", {{7, 20}}, 0, /* MSR_R3 */
"an msr register" },
{ IND, ins_reg, ext_reg, "pkr", {{7, 20}}, 0, /* PKR_R3 */
"a pkr register" },
{ IND, ins_reg, ext_reg, "pmc", {{7, 20}}, 0, /* PMC_R3 */
"a pmc register" },
{ IND, ins_reg, ext_reg, "pmd", {{7, 20}}, 0, /* PMD_R3 */
"a pmd register" },
{ IND, ins_reg, ext_reg, "rr", {{7, 20}}, 0, /* RR_R3 */
"an rr register" },
/* immediate operands: */
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 5, 20 }}, UDEC, /* CCNT5 */
"a 5-bit count (0-31)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 2, 27 }}, UDEC, /* CNT2a */
"a 2-bit count (1-4)" },
{ ABS, ins_cnt2b, ext_cnt2b, 0, {{ 2, 27 }}, UDEC, /* CNT2b */
"a 2-bit count (1-3)" },
{ ABS, ins_cnt2c, ext_cnt2c, 0, {{ 2, 30 }}, UDEC, /* CNT2c */
"a count (0, 7, 15, or 16)" },
{ ABS, ins_immu, ext_immu, 0, {{ 5, 14}}, UDEC, /* CNT5 */
"a 5-bit count (0-31)" },
{ ABS, ins_immu, ext_immu, 0, {{ 6, 27}}, UDEC, /* CNT6 */
"a 6-bit count (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 20}}, UDEC, /* CPOS6a */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 14}}, UDEC, /* CPOS6b */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_cimmu, ext_cimmu, 0, {{ 6, 31}}, UDEC, /* CPOS6c */
"a 6-bit bit pos (0-63)" },
{ ABS, ins_imms, ext_imms, 0, {{ 1, 36}}, SDEC, /* IMM1 */
"a 1-bit integer (-1, 0)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 13}}, UDEC, /* IMMU2 */
"a 2-bit unsigned (0-3)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, 0, /* IMMU7a */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, 0, /* IMMU7b */
"a 7-bit unsigned (0-127)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 13}}, UDEC, /* SOF */
"a frame size (register count)" },
{ ABS, ins_immu, ext_immu, 0, {{ 7, 20}}, UDEC, /* SOL */
"a local register count" },
{ ABS, ins_immus8,ext_immus8,0, {{ 4, 27}}, UDEC, /* SOR */
"a rotating register count (integer multiple of 8)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM8 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer (-128-127)" },
{ ABS, ins_immsu4, ext_imms, 0, /* IMM8U4 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit signed integer for 32-bit unsigned compare (-128-127)" },
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer (-127-128)" },
{ ABS, ins_immsm1u4, ext_immsm1, 0, /* IMM8M1U4 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer for 32-bit unsigned compare (-127-(-1),1-128,0x100000000)" },
{ ABS, ins_immsm1, ext_immsm1, 0, /* IMM8M1U8 */
{{ 7, 13}, { 1, 36}}, SDEC,
"an 8-bit integer for 64-bit unsigned compare (-127-(-1),1-128,0x10000000000000000)" },
{ ABS, ins_immu, ext_immu, 0, {{ 2, 33}, { 7, 20}}, 0, /* IMMU9 */
"a 9-bit unsigned (0-511)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM9a */
{{ 7, 6}, { 1, 27}, { 1, 36}}, SDEC,
"a 9-bit integer (-256-255)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM9b */
{{ 7, 13}, { 1, 27}, { 1, 36}}, SDEC,
"a 9-bit integer (-256-255)" },
{ ABS, ins_imms, ext_imms, 0, /* IMM14 */
{{ 7, 13}, { 6, 27}, { 1, 36}}, SDEC,
"a 14-bit integer (-8192-8191)" },
{ ABS, ins_imms1, ext_imms1, 0, /* IMM17 */
{{ 7, 6}, { 8, 24}, { 1, 36}}, 0,
"a 17-bit integer (-65536-65535)" },
{ ABS, ins_immu, ext_immu, 0, {{20, 6}, { 1, 36}}, 0, /* IMMU21 */
"a 21-bit unsigned" },
{ ABS, ins_imms, ext_imms, 0, /* IMM22 */
{{ 7, 13}, { 9, 27}, { 5, 22}, { 1, 36}}, SDEC,
"a 22-bit signed integer" },
{ ABS, ins_immu, ext_immu, 0, /* IMMU24 */
{{21, 6}, { 2, 31}, { 1, 36}}, 0,
"a 24-bit unsigned" },
{ ABS, ins_imms16,ext_imms16,0, {{27, 6}, { 1, 36}}, 0, /* IMM44 */
"a 44-bit unsigned (least 16 bits ignored/zeroes)" },
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU62 */
"a 62-bit unsigned" },
{ ABS, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* IMMU64 */
"a 64-bit unsigned" },
{ ABS, ins_inc3, ext_inc3, 0, {{ 3, 13}}, SDEC, /* INC3 */
"an increment (+/- 1, 4, 8, or 16)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 4, 27}}, UDEC, /* LEN4 */
"a 4-bit length (1-16)" },
{ ABS, ins_cnt, ext_cnt, 0, {{ 6, 27}}, UDEC, /* LEN6 */
"a 6-bit length (1-64)" },
{ ABS, ins_immu, ext_immu, 0, {{ 4, 20}}, 0, /* MBTYPE4 */
"a mix type (@rev, @mix, @shuf, @alt, or @brcst)" },
{ ABS, ins_immu, ext_immu, 0, {{ 8, 20}}, 0, /* MBTYPE8 */
"an 8-bit mix type" },
{ ABS, ins_immu, ext_immu, 0, {{ 6, 14}}, UDEC, /* POS6 */
"a 6-bit bit pos (0-63)" },
{ REL, ins_imms4, ext_imms4, 0, {{ 7, 6}, { 2, 33}}, 0, /* TAG13 */
"a branch tag" },
{ REL, ins_imms4, ext_imms4, 0, {{ 9, 24}}, 0, /* TAG13b */
"a branch tag" },
{ REL, ins_imms4, ext_imms4, 0, {{20, 6}, { 1, 36}}, 0, /* TGT25 */
"a branch target" },
{ REL, ins_imms4, ext_imms4, 0, /* TGT25b */
{{ 7, 6}, {13, 20}, { 1, 36}}, 0,
"a branch target" },
{ REL, ins_imms4, ext_imms4, 0, {{20, 13}, { 1, 36}}, 0, /* TGT25c */
"a branch target" },
{ REL, ins_rsvd, ext_rsvd, 0, {{0, 0}}, 0, /* TGT64 */
"a branch target" },
};

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/* BFD support for the ia64 architecture.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
const bfd_arch_info_type bfd_ia64_elf32_arch =
{
64, /* 64 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_ia64,
bfd_mach_ia64_elf32,
"ia64",
"ia64-elf32",
3, /* log2 of section alignment */
true, /* the one and only */
bfd_default_compatible,
bfd_default_scan ,
0,
};
const bfd_arch_info_type bfd_ia64_arch =
{
64, /* 64 bits in a word */
64, /* 64 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_ia64,
bfd_mach_ia64_elf64,
"ia64",
"ia64-elf64",
3, /* log2 of section alignment */
true, /* the one and only */
bfd_default_compatible,
bfd_default_scan ,
&bfd_ia64_elf32_arch,
};
#include "cpu-ia64-opc.c"

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/* BFD back-end for rs6000 support
Copyright 1990, 1991, 1993, 1995, 2000 Free Software Foundation, Inc.
FIXME: Can someone provide a transliteration of this name into ASCII?
Using the following chars caused a compiler warning on HIUX (so I replaced
them with octal escapes), and isn't useful without an understanding of what
character set it is.
Written by Mimi Ph\373\364ng-Th\345o V\365 of IBM
and John Gilmore of Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#include "libbfd.h"
/* The RS/6000 architecture is compatible with the PowerPC common
architecture. */
static const bfd_arch_info_type *rs6000_compatible
PARAMS ((const bfd_arch_info_type *, const bfd_arch_info_type *));
static const bfd_arch_info_type *
rs6000_compatible (a,b)
const bfd_arch_info_type *a;
const bfd_arch_info_type *b;
{
BFD_ASSERT (a->arch == bfd_arch_rs6000);
switch (b->arch)
{
default:
return NULL;
case bfd_arch_rs6000:
return bfd_default_compatible (a, b);
case bfd_arch_powerpc:
if (b->mach == 0)
return b;
return NULL;
}
/*NOTREACHED*/
}
static const bfd_arch_info_type arch_info_struct[] =
{
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_rs6000,
bfd_mach_rs6k_rs1,
"rs6000",
"rs6000:rs1",
3,
false, /* not the default */
rs6000_compatible,
bfd_default_scan,
&arch_info_struct[1]
},
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_rs6000,
bfd_mach_rs6k_rsc,
"rs6000",
"rs6000:rsc",
3,
false, /* not the default */
rs6000_compatible,
bfd_default_scan,
&arch_info_struct[2]
},
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_rs6000,
bfd_mach_rs6k_rs2,
"rs6000",
"rs6000:rs2",
3,
false, /* not the default */
rs6000_compatible,
bfd_default_scan,
0
}
};
const bfd_arch_info_type bfd_rs6000_arch =
{
32, /* 32 bits in a word */
32, /* 32 bits in an address */
8, /* 8 bits in a byte */
bfd_arch_rs6000,
bfd_mach_rs6k, /* POWER common architecture */
"rs6000",
"rs6000:6000",
3,
true, /* the default */
rs6000_compatible,
bfd_default_scan,
&arch_info_struct[0]
};

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/* BFD back-end for HP/Intel IA-64 EFI application files.
Copyright 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by David Mosberger <davidm@hpl.hp.com>
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
#include "bfd.h"
#include "sysdep.h"
#define TARGET_SYM bfd_efi_app_ia64_vec
#define TARGET_NAME "efi-app-ia64"
#define COFF_IMAGE_WITH_PE
#define COFF_WITH_PE
#define COFF_WITH_pep
#define PCRELOFFSET true
#define TARGET_UNDERSCORE '_'
#define COFF_LONG_SECTION_NAMES
#define PEI_TARGET_SUBSYSTEM IMAGE_SUBSYSTEM_EFI_APPLICATION
#define PEI_FORCE_MINIMUM_ALIGNMENT
#include "coff-ia64.c"

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/* Support for the generic parts of PE/PEI; common header information.
Copyright 1995, 1996, 1997, 1998, 1999, 2000, 2001
Free Software Foundation, Inc.
Written by Cygnus Solutions.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/*
Most of this hacked by Steve Chamberlain,
sac@cygnus.com
PE/PEI rearrangement (and code added): Donn Terry
Softway Systems, Inc.
*/
/* Hey look, some documentation [and in a place you expect to find it]!
The main reference for the pei format is "Microsoft Portable Executable
and Common Object File Format Specification 4.1". Get it if you need to
do some serious hacking on this code.
Another reference:
"Peering Inside the PE: A Tour of the Win32 Portable Executable
File Format", MSJ 1994, Volume 9.
The *sole* difference between the pe format and the pei format is that the
latter has an MSDOS 2.0 .exe header on the front that prints the message
"This app must be run under Windows." (or some such).
(FIXME: Whether that statement is *really* true or not is unknown.
Are there more subtle differences between pe and pei formats?
For now assume there aren't. If you find one, then for God sakes
document it here!)
The Microsoft docs use the word "image" instead of "executable" because
the former can also refer to a DLL (shared library). Confusion can arise
because the `i' in `pei' also refers to "image". The `pe' format can
also create images (i.e. executables), it's just that to run on a win32
system you need to use the pei format.
FIXME: Please add more docs here so the next poor fool that has to hack
on this code has a chance of getting something accomplished without
wasting too much time.
*/
#ifndef GET_FCN_LNNOPTR
#define GET_FCN_LNNOPTR(abfd, ext) \
bfd_h_get_32(abfd, (bfd_byte *) ext->x_sym.x_fcnary.x_fcn.x_lnnoptr)
#endif
#ifndef GET_FCN_ENDNDX
#define GET_FCN_ENDNDX(abfd, ext) \
bfd_h_get_32(abfd, (bfd_byte *) ext->x_sym.x_fcnary.x_fcn.x_endndx)
#endif
#ifndef PUT_FCN_LNNOPTR
#define PUT_FCN_LNNOPTR(abfd, in, ext) bfd_h_put_32(abfd, in, (bfd_byte *) ext->x_sym.x_fcnary.x_fcn.x_lnnoptr)
#endif
#ifndef PUT_FCN_ENDNDX
#define PUT_FCN_ENDNDX(abfd, in, ext) bfd_h_put_32(abfd, in, (bfd_byte *) ext->x_sym.x_fcnary.x_fcn.x_endndx)
#endif
#ifndef GET_LNSZ_LNNO
#define GET_LNSZ_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) ext->x_sym.x_misc.x_lnsz.x_lnno)
#endif
#ifndef GET_LNSZ_SIZE
#define GET_LNSZ_SIZE(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) ext->x_sym.x_misc.x_lnsz.x_size)
#endif
#ifndef PUT_LNSZ_LNNO
#define PUT_LNSZ_LNNO(abfd, in, ext) bfd_h_put_16(abfd, in, (bfd_byte *)ext->x_sym.x_misc.x_lnsz.x_lnno)
#endif
#ifndef PUT_LNSZ_SIZE
#define PUT_LNSZ_SIZE(abfd, in, ext) bfd_h_put_16(abfd, in, (bfd_byte*) ext->x_sym.x_misc.x_lnsz.x_size)
#endif
#ifndef GET_SCN_SCNLEN
#define GET_SCN_SCNLEN(abfd, ext) bfd_h_get_32(abfd, (bfd_byte *) ext->x_scn.x_scnlen)
#endif
#ifndef GET_SCN_NRELOC
#define GET_SCN_NRELOC(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *)ext->x_scn.x_nreloc)
#endif
#ifndef GET_SCN_NLINNO
#define GET_SCN_NLINNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *)ext->x_scn.x_nlinno)
#endif
#ifndef PUT_SCN_SCNLEN
#define PUT_SCN_SCNLEN(abfd,in, ext) bfd_h_put_32(abfd, in, (bfd_byte *) ext->x_scn.x_scnlen)
#endif
#ifndef PUT_SCN_NRELOC
#define PUT_SCN_NRELOC(abfd,in, ext) bfd_h_put_16(abfd, in, (bfd_byte *)ext->x_scn.x_nreloc)
#endif
#ifndef PUT_SCN_NLINNO
#define PUT_SCN_NLINNO(abfd,in, ext) bfd_h_put_16(abfd,in, (bfd_byte *) ext->x_scn.x_nlinno)
#endif
#ifndef GET_LINENO_LNNO
#define GET_LINENO_LNNO(abfd, ext) bfd_h_get_16(abfd, (bfd_byte *) (ext->l_lnno));
#endif
#ifndef PUT_LINENO_LNNO
#define PUT_LINENO_LNNO(abfd,val, ext) bfd_h_put_16(abfd,val, (bfd_byte *) (ext->l_lnno));
#endif
/* The f_symptr field in the filehdr is sometimes 64 bits. */
#ifndef GET_FILEHDR_SYMPTR
#define GET_FILEHDR_SYMPTR bfd_h_get_32
#endif
#ifndef PUT_FILEHDR_SYMPTR
#define PUT_FILEHDR_SYMPTR bfd_h_put_32
#endif
/* Some fields in the aouthdr are sometimes 64 bits. */
#ifndef GET_AOUTHDR_TSIZE
#define GET_AOUTHDR_TSIZE bfd_h_get_32
#endif
#ifndef PUT_AOUTHDR_TSIZE
#define PUT_AOUTHDR_TSIZE bfd_h_put_32
#endif
#ifndef GET_AOUTHDR_DSIZE
#define GET_AOUTHDR_DSIZE bfd_h_get_32
#endif
#ifndef PUT_AOUTHDR_DSIZE
#define PUT_AOUTHDR_DSIZE bfd_h_put_32
#endif
#ifndef GET_AOUTHDR_BSIZE
#define GET_AOUTHDR_BSIZE bfd_h_get_32
#endif
#ifndef PUT_AOUTHDR_BSIZE
#define PUT_AOUTHDR_BSIZE bfd_h_put_32
#endif
#ifndef GET_AOUTHDR_ENTRY
#define GET_AOUTHDR_ENTRY bfd_h_get_32
#endif
#ifndef PUT_AOUTHDR_ENTRY
#define PUT_AOUTHDR_ENTRY bfd_h_put_32
#endif
#ifndef GET_AOUTHDR_TEXT_START
#define GET_AOUTHDR_TEXT_START bfd_h_get_32
#endif
#ifndef PUT_AOUTHDR_TEXT_START
#define PUT_AOUTHDR_TEXT_START bfd_h_put_32
#endif
#ifndef GET_AOUTHDR_DATA_START
#define GET_AOUTHDR_DATA_START bfd_h_get_32
#endif
#ifndef PUT_AOUTHDR_DATA_START
#define PUT_AOUTHDR_DATA_START bfd_h_put_32
#endif
/* Some fields in the scnhdr are sometimes 64 bits. */
#ifndef GET_SCNHDR_PADDR
#define GET_SCNHDR_PADDR bfd_h_get_32
#endif
#ifndef PUT_SCNHDR_PADDR
#define PUT_SCNHDR_PADDR bfd_h_put_32
#endif
#ifndef GET_SCNHDR_VADDR
#define GET_SCNHDR_VADDR bfd_h_get_32
#endif
#ifndef PUT_SCNHDR_VADDR
#define PUT_SCNHDR_VADDR bfd_h_put_32
#endif
#ifndef GET_SCNHDR_SIZE
#define GET_SCNHDR_SIZE bfd_h_get_32
#endif
#ifndef PUT_SCNHDR_SIZE
#define PUT_SCNHDR_SIZE bfd_h_put_32
#endif
#ifndef GET_SCNHDR_SCNPTR
#define GET_SCNHDR_SCNPTR bfd_h_get_32
#endif
#ifndef PUT_SCNHDR_SCNPTR
#define PUT_SCNHDR_SCNPTR bfd_h_put_32
#endif
#ifndef GET_SCNHDR_RELPTR
#define GET_SCNHDR_RELPTR bfd_h_get_32
#endif
#ifndef PUT_SCNHDR_RELPTR
#define PUT_SCNHDR_RELPTR bfd_h_put_32
#endif
#ifndef GET_SCNHDR_LNNOPTR
#define GET_SCNHDR_LNNOPTR bfd_h_get_32
#endif
#ifndef PUT_SCNHDR_LNNOPTR
#define PUT_SCNHDR_LNNOPTR bfd_h_put_32
#endif
#ifdef COFF_WITH_pep
#define GET_OPTHDR_IMAGE_BASE bfd_h_get_64
#define PUT_OPTHDR_IMAGE_BASE bfd_h_put_64
#define GET_OPTHDR_SIZE_OF_STACK_RESERVE bfd_h_get_64
#define PUT_OPTHDR_SIZE_OF_STACK_RESERVE bfd_h_put_64
#define GET_OPTHDR_SIZE_OF_STACK_COMMIT bfd_h_get_64
#define PUT_OPTHDR_SIZE_OF_STACK_COMMIT bfd_h_put_64
#define GET_OPTHDR_SIZE_OF_HEAP_RESERVE bfd_h_get_64
#define PUT_OPTHDR_SIZE_OF_HEAP_RESERVE bfd_h_put_64
#define GET_OPTHDR_SIZE_OF_HEAP_COMMIT bfd_h_get_64
#define PUT_OPTHDR_SIZE_OF_HEAP_COMMIT bfd_h_put_64
#define GET_PDATA_ENTRY bfd_get_64
#define _bfd_XX_bfd_copy_private_bfd_data_common _bfd_pep_bfd_copy_private_bfd_data_common
#define _bfd_XX_bfd_copy_private_section_data _bfd_pep_bfd_copy_private_section_data
#define _bfd_XX_get_symbol_info _bfd_pep_get_symbol_info
#define _bfd_XX_only_swap_filehdr_out _bfd_pep_only_swap_filehdr_out
#define _bfd_XX_print_private_bfd_data_common _bfd_pep_print_private_bfd_data_common
#define _bfd_XXi_final_link_postscript _bfd_pepi_final_link_postscript
#define _bfd_XXi_final_link_postscript _bfd_pepi_final_link_postscript
#define _bfd_XXi_only_swap_filehdr_out _bfd_pepi_only_swap_filehdr_out
#define _bfd_XXi_swap_aouthdr_in _bfd_pepi_swap_aouthdr_in
#define _bfd_XXi_swap_aouthdr_out _bfd_pepi_swap_aouthdr_out
#define _bfd_XXi_swap_aux_in _bfd_pepi_swap_aux_in
#define _bfd_XXi_swap_aux_out _bfd_pepi_swap_aux_out
#define _bfd_XXi_swap_lineno_in _bfd_pepi_swap_lineno_in
#define _bfd_XXi_swap_lineno_out _bfd_pepi_swap_lineno_out
#define _bfd_XXi_swap_scnhdr_out _bfd_pepi_swap_scnhdr_out
#define _bfd_XXi_swap_sym_in _bfd_pepi_swap_sym_in
#define _bfd_XXi_swap_sym_out _bfd_pepi_swap_sym_out
#else /* !COFF_WITH_pep */
#define GET_OPTHDR_IMAGE_BASE bfd_h_get_32
#define PUT_OPTHDR_IMAGE_BASE bfd_h_put_32
#define GET_OPTHDR_SIZE_OF_STACK_RESERVE bfd_h_get_32
#define PUT_OPTHDR_SIZE_OF_STACK_RESERVE bfd_h_put_32
#define GET_OPTHDR_SIZE_OF_STACK_COMMIT bfd_h_get_32
#define PUT_OPTHDR_SIZE_OF_STACK_COMMIT bfd_h_put_32
#define GET_OPTHDR_SIZE_OF_HEAP_RESERVE bfd_h_get_32
#define PUT_OPTHDR_SIZE_OF_HEAP_RESERVE bfd_h_put_32
#define GET_OPTHDR_SIZE_OF_HEAP_COMMIT bfd_h_get_32
#define PUT_OPTHDR_SIZE_OF_HEAP_COMMIT bfd_h_put_32
#define GET_PDATA_ENTRY bfd_get_32
#define _bfd_XX_bfd_copy_private_bfd_data_common _bfd_pe_bfd_copy_private_bfd_data_common
#define _bfd_XX_bfd_copy_private_section_data _bfd_pe_bfd_copy_private_section_data
#define _bfd_XX_get_symbol_info _bfd_pe_get_symbol_info
#define _bfd_XX_only_swap_filehdr_out _bfd_pe_only_swap_filehdr_out
#define _bfd_XX_print_private_bfd_data_common _bfd_pe_print_private_bfd_data_common
#define _bfd_XXi_final_link_postscript _bfd_pei_final_link_postscript
#define _bfd_XXi_final_link_postscript _bfd_pei_final_link_postscript
#define _bfd_XXi_only_swap_filehdr_out _bfd_pei_only_swap_filehdr_out
#define _bfd_XXi_swap_aouthdr_in _bfd_pei_swap_aouthdr_in
#define _bfd_XXi_swap_aouthdr_out _bfd_pei_swap_aouthdr_out
#define _bfd_XXi_swap_aux_in _bfd_pei_swap_aux_in
#define _bfd_XXi_swap_aux_out _bfd_pei_swap_aux_out
#define _bfd_XXi_swap_lineno_in _bfd_pei_swap_lineno_in
#define _bfd_XXi_swap_lineno_out _bfd_pei_swap_lineno_out
#define _bfd_XXi_swap_scnhdr_out _bfd_pei_swap_scnhdr_out
#define _bfd_XXi_swap_sym_in _bfd_pei_swap_sym_in
#define _bfd_XXi_swap_sym_out _bfd_pei_swap_sym_out
#endif /* !COFF_WITH_pep */
/* These functions are architecture dependent, and are in peicode.h:
coff_swap_reloc_in
int coff_swap_reloc_out
coff_swap_filehdr_in
coff_swap_scnhdr_in
pe_mkobject
pe_mkobject_hook */
/* The functions described below are common across all PE/PEI
implementations architecture types, and actually appear in
peigen.c. */
void _bfd_XXi_swap_sym_in PARAMS ((bfd*, PTR, PTR));
#define coff_swap_sym_in _bfd_XXi_swap_sym_in
unsigned int _bfd_XXi_swap_sym_out PARAMS ((bfd*, PTR, PTR));
#define coff_swap_sym_out _bfd_XXi_swap_sym_out
void _bfd_XXi_swap_aux_in PARAMS ((bfd *, PTR, int, int, int, int, PTR));
#define coff_swap_aux_in _bfd_XXi_swap_aux_in
unsigned int _bfd_XXi_swap_aux_out \
PARAMS ((bfd *, PTR, int, int, int, int, PTR));
#define coff_swap_aux_out _bfd_XXi_swap_aux_out
void _bfd_XXi_swap_lineno_in PARAMS ((bfd*, PTR, PTR));
#define coff_swap_lineno_in _bfd_XXi_swap_lineno_in
unsigned int _bfd_XXi_swap_lineno_out PARAMS ((bfd*, PTR, PTR));
#define coff_swap_lineno_out _bfd_XXi_swap_lineno_out
void _bfd_XXi_swap_aouthdr_in PARAMS ((bfd*, PTR, PTR));
#define coff_swap_aouthdr_in _bfd_XXi_swap_aouthdr_in
unsigned int _bfd_XXi_swap_aouthdr_out PARAMS ((bfd *, PTR, PTR));
#define coff_swap_aouthdr_out _bfd_XXi_swap_aouthdr_out
unsigned int _bfd_XXi_swap_scnhdr_out PARAMS ((bfd *, PTR, PTR));
#define coff_swap_scnhdr_out _bfd_XXi_swap_scnhdr_out
boolean _bfd_XX_print_private_bfd_data_common PARAMS ((bfd *, PTR));
boolean _bfd_XX_bfd_copy_private_bfd_data_common PARAMS ((bfd *, bfd *));
void _bfd_XX_get_symbol_info PARAMS ((bfd *, asymbol *, symbol_info *));
boolean _bfd_XXi_final_link_postscript
PARAMS ((bfd *, struct coff_final_link_info *));
#ifndef coff_final_link_postscript
#define coff_final_link_postscript _bfd_XXi_final_link_postscript
#endif
/* The following are needed only for ONE of pe or pei, but don't
otherwise vary; peicode.h fixes up ifdefs but we provide the
prototype. */
unsigned int _bfd_XX_only_swap_filehdr_out PARAMS ((bfd*, PTR, PTR));
unsigned int _bfd_XXi_only_swap_filehdr_out PARAMS ((bfd*, PTR, PTR));
boolean _bfd_XX_bfd_copy_private_section_data
PARAMS ((bfd *, asection *, bfd *, asection *));

1324
contrib/binutils/bfd/peicode.h Normal file
View File

File diff suppressed because it is too large Load Diff

102
contrib/binutils/bfd/sunos.c
View File

@ -1,5 +1,5 @@
/* BFD backend for SunOS binaries.
Copyright (C) 1990, 91, 92, 93, 94, 95, 96, 97, 1998
Copyright 1990, 1991, 1992, 1994, 1995, 1996, 1997, 1998, 2000
Free Software Foundation, Inc.
Written by Cygnus Support.
@ -84,12 +84,17 @@ static boolean sunos_finish_dynamic_link
(((mtype) == M_SPARC && bfd_lookup_arch (bfd_arch_sparc, 0) != NULL) \
|| ((mtype) == M_SPARCLET \
&& bfd_lookup_arch (bfd_arch_sparc, bfd_mach_sparc_sparclet) != NULL) \
|| ((mtype) == M_SPARCLITE_LE \
&& bfd_lookup_arch (bfd_arch_sparc, bfd_mach_sparc_sparclet) != NULL) \
|| (((mtype) == M_UNKNOWN || (mtype) == M_68010 || (mtype) == M_68020) \
&& bfd_lookup_arch (bfd_arch_m68k, 0) != NULL))
/* Include the usual a.out support. */
#include "aoutf1.h"
/* The SunOS 4.1.4 /usr/include/locale.h defines valid as a macro. */
#undef valid
/* SunOS shared library support. We store a pointer to this structure
in obj_aout_dynamic_info (abfd). */
@ -503,7 +508,7 @@ sunos_canonicalize_dynamic_reloc (abfd, storage, syms)
* sizeof (arelent))));
if (info->canonical_dynrel == NULL && info->dynrel_count != 0)
return -1;
to = info->canonical_dynrel;
if (obj_reloc_entry_size (abfd) == RELOC_EXT_SIZE)
@ -1252,7 +1257,7 @@ sunos_add_one_symbol (info, abfd, name, flags, section, value, string,
/*ARGSUSED*/
struct bfd_link_needed_list *
bfd_sunos_get_needed_list (abfd, info)
bfd *abfd;
bfd *abfd ATTRIBUTE_UNUSED;
struct bfd_link_info *info;
{
if (info->hash->creator != &MY(vec))
@ -1416,7 +1421,7 @@ bfd_sunos_size_dynamic_sections (output_bfd, info, sdynptr, sneedptr,
s->contents = (bfd_byte *) bfd_alloc (output_bfd, s->_raw_size);
if (s->contents == NULL && s->_raw_size != 0)
return false;
/* The number of buckets is just the number of symbols divided
by four. To compute the final size of the hash table, we
must actually compute the hash table. Normally we need
@ -1602,7 +1607,7 @@ static boolean
sunos_scan_std_relocs (info, abfd, sec, relocs, rel_size)
struct bfd_link_info *info;
bfd *abfd;
asection *sec;
asection *sec ATTRIBUTE_UNUSED;
const struct reloc_std_external *relocs;
bfd_size_type rel_size;
{
@ -1762,7 +1767,7 @@ static boolean
sunos_scan_ext_relocs (info, abfd, sec, relocs, rel_size)
struct bfd_link_info *info;
bfd *abfd;
asection *sec;
asection *sec ATTRIBUTE_UNUSED;
const struct reloc_ext_external *relocs;
bfd_size_type rel_size;
{
@ -2168,8 +2173,8 @@ sunos_scan_dynamic_symbol (h, data)
/*ARGSUSED*/
static boolean
sunos_link_dynamic_object (info, abfd)
struct bfd_link_info *info;
bfd *abfd;
struct bfd_link_info *info ATTRIBUTE_UNUSED;
bfd *abfd ATTRIBUTE_UNUSED;
{
return true;
}
@ -2269,16 +2274,16 @@ sunos_write_dynamic_symbol (output_bfd, info, harg)
PUT_WORD (output_bfd, r_address, srel->r_address);
if (bfd_header_big_endian (output_bfd))
{
srel->r_index[0] = (bfd_byte)(h->dynindx >> 16);
srel->r_index[1] = (bfd_byte)(h->dynindx >> 8);
srel->r_index[2] = (bfd_byte)(h->dynindx);
srel->r_index[0] = (bfd_byte) (h->dynindx >> 16);
srel->r_index[1] = (bfd_byte) (h->dynindx >> 8);
srel->r_index[2] = (bfd_byte) (h->dynindx);
srel->r_type[0] = (RELOC_STD_BITS_EXTERN_BIG
| RELOC_STD_BITS_JMPTABLE_BIG);
}
else
{
srel->r_index[2] = (bfd_byte)(h->dynindx >> 16);
srel->r_index[1] = (bfd_byte)(h->dynindx >> 8);
srel->r_index[2] = (bfd_byte) (h->dynindx >> 16);
srel->r_index[1] = (bfd_byte) (h->dynindx >> 8);
srel->r_index[0] = (bfd_byte)h->dynindx;
srel->r_type[0] = (RELOC_STD_BITS_EXTERN_LITTLE
| RELOC_STD_BITS_JMPTABLE_LITTLE);
@ -2292,8 +2297,8 @@ sunos_write_dynamic_symbol (output_bfd, info, harg)
PUT_WORD (output_bfd, r_address, erel->r_address);
if (bfd_header_big_endian (output_bfd))
{
erel->r_index[0] = (bfd_byte)(h->dynindx >> 16);
erel->r_index[1] = (bfd_byte)(h->dynindx >> 8);
erel->r_index[0] = (bfd_byte) (h->dynindx >> 16);
erel->r_index[1] = (bfd_byte) (h->dynindx >> 8);
erel->r_index[2] = (bfd_byte)h->dynindx;
erel->r_type[0] =
(RELOC_EXT_BITS_EXTERN_BIG
@ -2301,8 +2306,8 @@ sunos_write_dynamic_symbol (output_bfd, info, harg)
}
else
{
erel->r_index[2] = (bfd_byte)(h->dynindx >> 16);
erel->r_index[1] = (bfd_byte)(h->dynindx >> 8);
erel->r_index[2] = (bfd_byte) (h->dynindx >> 16);
erel->r_index[1] = (bfd_byte) (h->dynindx >> 8);
erel->r_index[0] = (bfd_byte)h->dynindx;
erel->r_type[0] =
(RELOC_EXT_BITS_EXTERN_LITTLE
@ -2422,7 +2427,7 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
asection *input_section;
struct aout_link_hash_entry *harg;
PTR reloc;
bfd_byte *contents;
bfd_byte *contents ATTRIBUTE_UNUSED;
boolean *skip;
bfd_vma *relocationp;
{
@ -2430,6 +2435,7 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
bfd *dynobj;
boolean baserel;
boolean jmptbl;
boolean pcrel;
asection *s;
bfd_byte *p;
long indx;
@ -2438,7 +2444,10 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
dynobj = sunos_hash_table (info)->dynobj;
if (h != NULL && h->plt_offset != 0)
if (h != NULL
&& h->plt_offset != 0
&& (info->shared
|| (h->flags & SUNOS_DEF_REGULAR) == 0))
{
asection *splt;
@ -2458,11 +2467,13 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
{
baserel = (0 != (srel->r_type[0] & RELOC_STD_BITS_BASEREL_BIG));
jmptbl = (0 != (srel->r_type[0] & RELOC_STD_BITS_JMPTABLE_BIG));
pcrel = (0 != (srel->r_type[0] & RELOC_STD_BITS_PCREL_BIG));
}
else
{
baserel = (0 != (srel->r_type[0] & RELOC_STD_BITS_BASEREL_LITTLE));
jmptbl = (0 != (srel->r_type[0] & RELOC_STD_BITS_JMPTABLE_LITTLE));
pcrel = (0 != (srel->r_type[0] & RELOC_STD_BITS_PCREL_LITTLE));
}
}
else
@ -2481,6 +2492,13 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
|| r_type == RELOC_BASE13
|| r_type == RELOC_BASE22);
jmptbl = r_type == RELOC_JMP_TBL;
pcrel = (r_type == RELOC_DISP8
|| r_type == RELOC_DISP16
|| r_type == RELOC_DISP32
|| r_type == RELOC_WDISP30
|| r_type == RELOC_WDISP22);
/* We don't consider the PC10 and PC22 types to be PC relative,
because they are pcrel_offset. */
}
if (baserel)
@ -2576,8 +2594,8 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
srel->r_address);
if (bfd_header_big_endian (dynobj))
{
srel->r_index[0] = (bfd_byte)(indx >> 16);
srel->r_index[1] = (bfd_byte)(indx >> 8);
srel->r_index[0] = (bfd_byte) (indx >> 16);
srel->r_index[1] = (bfd_byte) (indx >> 8);
srel->r_index[2] = (bfd_byte)indx;
if (h == NULL)
srel->r_type[0] = 2 << RELOC_STD_BITS_LENGTH_SH_BIG;
@ -2590,8 +2608,8 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
}
else
{
srel->r_index[2] = (bfd_byte)(indx >> 16);
srel->r_index[1] = (bfd_byte)(indx >> 8);
srel->r_index[2] = (bfd_byte) (indx >> 16);
srel->r_index[1] = (bfd_byte) (indx >> 8);
srel->r_index[0] = (bfd_byte)indx;
if (h == NULL)
srel->r_type[0] = 2 << RELOC_STD_BITS_LENGTH_SH_LITTLE;
@ -2615,8 +2633,8 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
erel->r_address);
if (bfd_header_big_endian (dynobj))
{
erel->r_index[0] = (bfd_byte)(indx >> 16);
erel->r_index[1] = (bfd_byte)(indx >> 8);
erel->r_index[0] = (bfd_byte) (indx >> 16);
erel->r_index[1] = (bfd_byte) (indx >> 8);
erel->r_index[2] = (bfd_byte)indx;
if (h == NULL)
erel->r_type[0] =
@ -2628,8 +2646,8 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
}
else
{
erel->r_index[2] = (bfd_byte)(indx >> 16);
erel->r_index[1] = (bfd_byte)(indx >> 8);
erel->r_index[2] = (bfd_byte) (indx >> 16);
erel->r_index[1] = (bfd_byte) (indx >> 8);
erel->r_index[0] = (bfd_byte)indx;
if (h == NULL)
erel->r_type[0] =
@ -2708,16 +2726,18 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
srel->r_address);
if (bfd_header_big_endian (dynobj))
{
srel->r_index[0] = (bfd_byte)(indx >> 16);
srel->r_index[1] = (bfd_byte)(indx >> 8);
srel->r_index[0] = (bfd_byte) (indx >> 16);
srel->r_index[1] = (bfd_byte) (indx >> 8);
srel->r_index[2] = (bfd_byte)indx;
}
else
{
srel->r_index[2] = (bfd_byte)(indx >> 16);
srel->r_index[1] = (bfd_byte)(indx >> 8);
srel->r_index[2] = (bfd_byte) (indx >> 16);
srel->r_index[1] = (bfd_byte) (indx >> 8);
srel->r_index[0] = (bfd_byte)indx;
}
/* FIXME: We may have to change the addend for a PC relative
reloc. */
}
else
{
@ -2731,16 +2751,26 @@ sunos_check_dynamic_reloc (info, input_bfd, input_section, harg, reloc,
erel->r_address);
if (bfd_header_big_endian (dynobj))
{
erel->r_index[0] = (bfd_byte)(indx >> 16);
erel->r_index[1] = (bfd_byte)(indx >> 8);
erel->r_index[0] = (bfd_byte) (indx >> 16);
erel->r_index[1] = (bfd_byte) (indx >> 8);
erel->r_index[2] = (bfd_byte)indx;
}
else
{
erel->r_index[2] = (bfd_byte)(indx >> 16);
erel->r_index[1] = (bfd_byte)(indx >> 8);
erel->r_index[2] = (bfd_byte) (indx >> 16);
erel->r_index[1] = (bfd_byte) (indx >> 8);
erel->r_index[0] = (bfd_byte)indx;
}
if (pcrel && h != NULL)
{
/* Adjust the addend for the change in address. */
PUT_WORD (dynobj,
(GET_WORD (dynobj, erel->r_addend)
- (input_section->output_section->vma
+ input_section->output_offset
- input_section->vma)),
erel->r_addend);
}
}
++s->reloc_count;
@ -2903,7 +2933,7 @@ sunos_finish_dynamic_link (abfd, info)
PUT_WORD (dynobj,
BFD_ALIGN (obj_textsec (abfd)->_raw_size, 0x2000),
esdl.ld_text);
if (! bfd_set_section_contents (abfd, sdyn->output_section, &esdl,
(sdyn->output_offset
+ sizeof esd

194
contrib/binutils/bfd/xcoff-target.h Normal file
View File

@ -0,0 +1,194 @@
/* Common definitions for backends based on IBM RS/6000 "XCOFF64" files.
Copyright 2000, 2001
Free Software Foundation, Inc.
Contributed by Cygnus Support.
This file is part of BFD, the Binary File Descriptor library.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/* Internalcoff.h and coffcode.h modify themselves based on this flag. */
#define RS6000COFF_C 1
#define SELECT_RELOC(internal, howto) \
{ \
internal.r_type = howto->type; \
internal.r_size = \
((howto->complain_on_overflow == complain_overflow_signed \
? 0x80 \
: 0) \
| (howto->bitsize - 1)); \
}
#define COFF_DEFAULT_SECTION_ALIGNMENT_POWER (3)
#define COFF_LONG_FILENAMES
#define NO_COFF_SYMBOLS
#define RTYPE2HOWTO(cache_ptr, dst) _bfd_xcoff_rtype2howto (cache_ptr, dst)
#define coff_mkobject _bfd_xcoff_mkobject
#define coff_bfd_copy_private_bfd_data _bfd_xcoff_copy_private_bfd_data
#define coff_bfd_is_local_label_name _bfd_xcoff_is_local_label_name
#define coff_bfd_reloc_type_lookup _bfd_xcoff_reloc_type_lookup
#define coff_relocate_section _bfd_ppc_xcoff_relocate_section
#define CORE_FILE_P _bfd_dummy_target
#define coff_core_file_failing_command _bfd_nocore_core_file_failing_command
#define coff_core_file_failing_signal _bfd_nocore_core_file_failing_signal
#define coff_core_file_matches_executable_p \
_bfd_nocore_core_file_matches_executable_p
#ifdef AIX_CORE
#undef CORE_FILE_P
#define CORE_FILE_P rs6000coff_core_p
extern const bfd_target * rs6000coff_core_p ();
extern boolean rs6000coff_core_file_matches_executable_p ();
#undef coff_core_file_matches_executable_p
#define coff_core_file_matches_executable_p \
rs6000coff_core_file_matches_executable_p
extern char *rs6000coff_core_file_failing_command PARAMS ((bfd *abfd));
#undef coff_core_file_failing_command
#define coff_core_file_failing_command rs6000coff_core_file_failing_command
extern int rs6000coff_core_file_failing_signal PARAMS ((bfd *abfd));
#undef coff_core_file_failing_signal
#define coff_core_file_failing_signal rs6000coff_core_file_failing_signal
#endif /* AIX_CORE */
#ifdef LYNX_CORE
#undef CORE_FILE_P
#define CORE_FILE_P lynx_core_file_p
extern const bfd_target *lynx_core_file_p PARAMS ((bfd *abfd));
extern boolean lynx_core_file_matches_executable_p PARAMS ((bfd *core_bfd,
bfd *exec_bfd));
#undef coff_core_file_matches_executable_p
#define coff_core_file_matches_executable_p lynx_core_file_matches_executable_p
extern char *lynx_core_file_failing_command PARAMS ((bfd *abfd));
#undef coff_core_file_failing_command
#define coff_core_file_failing_command lynx_core_file_failing_command
extern int lynx_core_file_failing_signal PARAMS ((bfd *abfd));
#undef coff_core_file_failing_signal
#define coff_core_file_failing_signal lynx_core_file_failing_signal
#endif /* LYNX_CORE */
#define _bfd_xcoff_bfd_get_relocated_section_contents \
coff_bfd_get_relocated_section_contents
#define _bfd_xcoff_bfd_relax_section coff_bfd_relax_section
#define _bfd_xcoff_bfd_gc_sections coff_bfd_gc_sections
#define _bfd_xcoff_bfd_link_split_section coff_bfd_link_split_section
/* XCOFF archives do not have anything which corresponds to an
extended name table. */
#define _bfd_xcoff_slurp_extended_name_table bfd_false
#define _bfd_xcoff_construct_extended_name_table \
((boolean (*) PARAMS ((bfd *, char **, bfd_size_type *, const char **))) \
bfd_false)
#define _bfd_xcoff_truncate_arname bfd_dont_truncate_arname
/* We can use the standard get_elt_at_index routine. */
#define _bfd_xcoff_get_elt_at_index _bfd_generic_get_elt_at_index
/* XCOFF archives do not have a timestamp. */
#define _bfd_xcoff_update_armap_timestamp bfd_true
extern boolean _bfd_xcoff_mkobject PARAMS ((bfd *));
extern boolean _bfd_xcoff_copy_private_bfd_data PARAMS ((bfd *, bfd *));
extern boolean _bfd_xcoff_is_local_label_name PARAMS ((bfd *, const char *));
extern void _bfd_xcoff_rtype2howto
PARAMS ((arelent *, struct internal_reloc *));
extern reloc_howto_type *_bfd_xcoff_reloc_type_lookup
PARAMS ((bfd *, bfd_reloc_code_real_type));
extern boolean _bfd_xcoff_slurp_armap PARAMS ((bfd *));
extern const bfd_target *_bfd_xcoff_archive_p PARAMS ((bfd *));
extern PTR _bfd_xcoff_read_ar_hdr PARAMS ((bfd *));
extern bfd *_bfd_xcoff_openr_next_archived_file PARAMS ((bfd *, bfd *));
extern int _bfd_xcoff_generic_stat_arch_elt PARAMS ((bfd *, struct stat *));
extern boolean _bfd_xcoff_write_armap
PARAMS ((bfd *, unsigned int, struct orl *, unsigned int, int));
extern boolean _bfd_xcoff_write_archive_contents PARAMS ((bfd *));
extern int _bfd_xcoff_sizeof_headers PARAMS ((bfd *, boolean));
extern void _bfd_xcoff_swap_sym_in PARAMS ((bfd *, PTR, PTR));
extern unsigned int _bfd_xcoff_swap_sym_out PARAMS ((bfd *, PTR, PTR));
extern void _bfd_xcoff_swap_aux_in PARAMS ((bfd *, PTR, int, int, int, int, PTR));
extern unsigned int _bfd_xcoff_swap_aux_out PARAMS ((bfd *, PTR, int, int, int, int, PTR));
#ifndef coff_SWAP_sym_in
#define coff_SWAP_sym_in _bfd_xcoff_swap_sym_in
#define coff_SWAP_sym_out _bfd_xcoff_swap_sym_out
#define coff_SWAP_aux_in _bfd_xcoff_swap_aux_in
#define coff_SWAP_aux_out _bfd_xcoff_swap_aux_out
#endif
#include "coffcode.h"
/* The transfer vector that leads the outside world to all of the above. */
const bfd_target TARGET_SYM =
{
TARGET_NAME,
bfd_target_xcoff_flavour,
BFD_ENDIAN_BIG, /* data byte order is big */
BFD_ENDIAN_BIG, /* header byte order is big */
(HAS_RELOC | EXEC_P | /* object flags */
HAS_LINENO | HAS_DEBUG | DYNAMIC |
HAS_SYMS | HAS_LOCALS | WP_TEXT),
(SEC_HAS_CONTENTS | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* section flags */
0, /* leading char */
'/', /* ar_pad_char */
15, /* ar_max_namelen??? FIXMEmgo */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* data */
bfd_getb64, bfd_getb_signed_64, bfd_putb64,
bfd_getb32, bfd_getb_signed_32, bfd_putb32,
bfd_getb16, bfd_getb_signed_16, bfd_putb16, /* hdrs */
{_bfd_dummy_target, coff_object_p, /* bfd_check_format */
_bfd_xcoff_archive_p, CORE_FILE_P},
{bfd_false, coff_mkobject, /* bfd_set_format */
_bfd_generic_mkarchive, bfd_false},
{bfd_false, coff_write_object_contents, /* bfd_write_contents */
_bfd_xcoff_write_archive_contents, bfd_false},
BFD_JUMP_TABLE_GENERIC (coff),
BFD_JUMP_TABLE_COPY (coff),
BFD_JUMP_TABLE_CORE (coff),
BFD_JUMP_TABLE_ARCHIVE (_bfd_xcoff),
BFD_JUMP_TABLE_SYMBOLS (coff),
BFD_JUMP_TABLE_RELOCS (coff),
BFD_JUMP_TABLE_WRITE (coff),
BFD_JUMP_TABLE_LINK (_bfd_xcoff),
BFD_JUMP_TABLE_DYNAMIC (_bfd_xcoff),
NULL,
COFF_SWAP_TABLE
};

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/* tc-ia64.h -- Header file for tc-ia64.c.
Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to
the Free Software Foundation, 59 Temple Place - Suite 330,
Boston, MA 02111-1307, USA. */
#include <opcode/ia64.h>
#include <elf/ia64.h>
#define TC_IA64
/* Linux is little endian by default. HPUX is big endian by default. */
#ifdef TE_HPUX
#define md_number_to_chars number_to_chars_bigendian
#define TARGET_BYTES_BIG_ENDIAN 1
#else
#define md_number_to_chars number_to_chars_littleendian
#define TARGET_BYTES_BIG_ENDIAN 0
#endif /* TE_HPUX */
/* We need to set the default object file format in ia64_init and not in
md_begin. This is because parse_args is called before md_begin, and we
do not want md_begin to wipe out the flag settings set by options parsed in
md_parse_args. */
#define HOST_SPECIAL_INIT ia64_init
extern void ia64_init PARAMS ((int, char **));
#define TARGET_FORMAT ia64_target_format()
extern const char *ia64_target_format PARAMS ((void));
#define TARGET_ARCH bfd_arch_ia64
#define DOUBLESLASH_LINE_COMMENTS /* allow //-style comments */
#define TC_HANDLES_FX_DONE
#define NEED_LITERAL_POOL /* need gp literal pool */
#define RELOC_REQUIRES_SYMBOL
#define DIFF_EXPR_OK /* foo-. gets turned into PC relative relocs */
#define NEED_INDEX_OPERATOR /* [ ] is index operator */
#define QUOTES_IN_INSN /* allow `string "foo;bar"' */
#define LEX_AT LEX_NAME /* allow `@' inside name */
#define LEX_QM LEX_NAME /* allow `?' inside name */
#define LEX_HASH LEX_END_NAME /* allow `#' ending a name */
struct ia64_fix
{
int bigendian; /* byte order at fix location */
enum ia64_opnd opnd;
};
extern void ia64_do_align PARAMS((int n));
extern void ia64_end_of_source PARAMS((void));
extern void ia64_start_line PARAMS((void));
extern int ia64_unrecognized_line PARAMS((int ch));
extern void ia64_frob_label PARAMS((struct symbol *sym));
extern void ia64_flush_pending_output PARAMS((void));
extern int ia64_parse_name (char *name, expressionS *e);
extern int ia64_optimize_expr PARAMS((expressionS *l, operatorT op,
expressionS *r));
extern void ia64_cons_align PARAMS((int));
extern void ia64_flush_insns PARAMS((void));
extern int ia64_fix_adjustable PARAMS((struct fix *fix));
extern int ia64_force_relocation PARAMS((struct fix *));
extern void ia64_cons_fix_new PARAMS ((fragS *f, int where, int nbytes,
expressionS *exp));
extern void ia64_validate_fix PARAMS ((struct fix *fix));
extern char * ia64_canonicalize_symbol_name PARAMS ((char *));
extern flagword ia64_elf_section_flags PARAMS ((flagword, int, int));
extern int ia64_elf_section_type PARAMS ((const char *, size_t len));
extern long ia64_pcrel_from_section PARAMS ((struct fix *fix, segT sec));
extern void ia64_md_do_align PARAMS ((int, const char *, int, int));
extern void ia64_handle_align PARAMS ((fragS *f));
#define md_end() ia64_end_of_source ()
#define md_start_line_hook() ia64_start_line ()
#define tc_unrecognized_line(ch) ia64_unrecognized_line (ch)
#define tc_frob_label(s) ia64_frob_label (s)
#define md_flush_pending_output() ia64_flush_pending_output ()
#define md_parse_name(s,e) ia64_parse_name (s, e)
#define tc_canonicalize_symbol_name(s) ia64_canonicalize_symbol_name (s)
#define md_optimize_expr(l,o,r) ia64_optimize_expr (l, o, r)
#define md_cons_align(n) ia64_cons_align (n)
#define TC_FORCE_RELOCATION(f) ia64_force_relocation (f)
#define tc_fix_adjustable(f) ia64_fix_adjustable (f)
#define md_convert_frag(b,s,f) as_fatal ("ia64_convert_frag")
#define md_create_long_jump(p,f,t,fr,s) as_fatal("ia64_create_long_jump")
#define md_create_short_jump(p,f,t,fr,s) \
as_fatal("ia64_create_short_jump")
#define md_estimate_size_before_relax(f,s) \
(as_fatal ("ia64_estimate_size_before_relax"), 1)
#define md_elf_section_flags ia64_elf_section_flags
#define TC_FIX_TYPE struct ia64_fix
#define TC_INIT_FIX_DATA(f) { f->tc_fix_data.opnd = 0; }
#define TC_CONS_FIX_NEW(f,o,l,e) ia64_cons_fix_new (f, o, l, e)
#define TC_VALIDATE_FIX(fix,seg,skip) ia64_validate_fix (fix)
#define MD_PCREL_FROM_SECTION(fix,sec) ia64_pcrel_from_section (fix, sec)
#define md_do_align(n,f,l,m,j) ia64_md_do_align (n,f,l,m)
#define HANDLE_ALIGN(f) ia64_handle_align (f)
#define md_elf_section_type(str,len) ia64_elf_section_type (str, len)
#define MAX_MEM_FOR_RS_ALIGN_CODE (15 + 16)
/* Call md_apply_fix3 with segment instead of md_apply_fix. */
#define MD_APPLY_FIX3
#define WORKING_DOT_WORD /* don't do broken word processing for now */
#define ELF_TC_SPECIAL_SECTIONS \
{ ".sbss", SHT_NOBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT }, \
{ ".sdata", SHT_PROGBITS, SHF_ALLOC + SHF_WRITE + SHF_IA_64_SHORT },
#define DWARF2_LINE_MIN_INSN_LENGTH 1 /* so slot-multipliers can be 1 */
/* This is the information required for unwind records in an ia64
object file. This is required by GAS and the compiler runtime. */
/* These are the starting point masks for the various types of
unwind records. To create a record of type R3 for instance, one
starts by using the value UNW_R3 and or-ing in any other required values.
These values are also unique (in context), so they can be used to identify
the various record types as well. UNW_Bx and some UNW_Px do have the
same value, but Px can only occur in a prologue context, and Bx in
a body context. */
#define UNW_R1 0x00
#define UNW_R2 0x40
#define UNW_R3 0x60
#define UNW_P1 0x80
#define UNW_P2 0xA0
#define UNW_P3 0xB0
#define UNW_P4 0xB8
#define UNW_P5 0xB9
#define UNW_P6 0xC0
#define UNW_P7 0xE0
#define UNW_P8 0xF0
#define UNW_P9 0xF1
#define UNW_P10 0xFF
#define UNW_X1 0xF9
#define UNW_X2 0xFA
#define UNW_X3 0xFB
#define UNW_X4 0xFC
#define UNW_B1 0x80
#define UNW_B2 0xC0
#define UNW_B3 0xE0
#define UNW_B4 0xF0
/* These are all the various types of unwind records. */
typedef enum
{
prologue, prologue_gr, body, mem_stack_f, mem_stack_v, psp_gr, psp_sprel,
rp_when, rp_gr, rp_br, rp_psprel, rp_sprel, pfs_when, pfs_gr, pfs_psprel,
pfs_sprel, preds_when, preds_gr, preds_psprel, preds_sprel,
fr_mem, frgr_mem, gr_gr, gr_mem, br_mem, br_gr, spill_base, spill_mask,
unat_when, unat_gr, unat_psprel, unat_sprel, lc_when, lc_gr, lc_psprel,
lc_sprel, fpsr_when, fpsr_gr, fpsr_psprel, fpsr_sprel,
priunat_when_gr, priunat_when_mem, priunat_gr, priunat_psprel,
priunat_sprel, bsp_when, bsp_gr, bsp_psprel, bsp_sprel, bspstore_when,
bspstore_gr, bspstore_psprel, bspstore_sprel, rnat_when, rnat_gr,
rnat_psprel, rnat_sprel, epilogue, label_state, copy_state,
spill_psprel, spill_sprel, spill_reg, spill_psprel_p, spill_sprel_p,
spill_reg_p, unwabi
} unw_record_type;
/* These structures declare the fields that can be used in each of the
4 record formats, R, P, B and X. */
typedef struct unw_r_record
{
unsigned long rlen;
unsigned short grmask;
unsigned short grsave;
/* masks to represent the union of save.g, save.f, save.b, and
save.gf: */
unsigned long imask_size;
struct
{
unsigned char *i;
unsigned long fr_mem;
unsigned char gr_mem;
unsigned char br_mem;
} mask;
} unw_r_record;
typedef struct unw_p_record
{
void *imask;
unsigned long t;
unsigned long size;
unsigned long spoff;
unsigned long br;
unsigned long pspoff;
unsigned short gr;
unsigned short rmask;
unsigned short grmask;
unsigned long frmask;
unsigned short brmask;
unsigned char abi;
unsigned char context;
} unw_p_record;
typedef struct unw_b_record
{
unsigned long t;
unsigned long label;
unsigned short ecount;
} unw_b_record;
typedef struct unw_x_record
{
unsigned long t;
unsigned long spoff;
unsigned long pspoff;
unsigned short reg;
unsigned short treg;
unsigned short qp;
unsigned short ab; /* Value of the AB field.. */
unsigned short xy; /* Value of the XY field.. */
} unw_x_record;
/* This structure is used to determine the specific record type and
its fields. */
typedef struct unwind_record
{
unw_record_type type;
union {
unw_r_record r;
unw_p_record p;
unw_b_record b;
unw_x_record x;
} record;
} unwind_record;
/* This expression evaluates to false if the relocation is for a local
object for which we still want to do the relocation at runtime.
True if we are willing to perform this relocation while building
the .o file. This is only used for pcrel relocations. */
#define TC_RELOC_RTSYM_LOC_FIXUP(FIX) \
((FIX)->fx_addsy == NULL \
|| (FIX)->fx_r_type == 0 \
|| (! S_IS_EXTERNAL ((FIX)->fx_addsy) \
&& ! S_IS_WEAK ((FIX)->fx_addsy) \
&& S_IS_DEFINED ((FIX)->fx_addsy) \
&& ! S_IS_COMMON ((FIX)->fx_addsy)))

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/* coff information for HP/Intel IA-64.
Copyright 2001 Free Software Foundation, Inc.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */
/********************** FILE HEADER **********************/
struct external_filehdr {
char f_magic[2]; /* magic number */
char f_nscns[2]; /* number of sections */
char f_timdat[4]; /* time & date stamp */
char f_symptr[4]; /* file pointer to symtab */
char f_nsyms[4]; /* number of symtab entries */
char f_opthdr[2]; /* sizeof(optional hdr) */
char f_flags[2]; /* flags */
};
#define IA64MAGIC 0x200
#define IA64BADMAG(x) (((x).f_magic != IA64MAGIC))
/* Bits for f_flags:
* F_RELFLG relocation info stripped from file
* F_EXEC file is executable (no unresolved external references)
* F_LNNO line numbers stripped from file
* F_LSYMS local symbols stripped from file
* F_AR32WR file has byte ordering of an AR32WR machine (e.g. vax)
*/
#define F_RELFLG (0x0001)
#define F_EXEC (0x0002)
#define F_LNNO (0x0004)
#define F_LSYMS (0x0008)
#define FILHDR struct external_filehdr
#define FILHSZ 20
/********************** AOUT "OPTIONAL HEADER" **********************/
typedef struct
{
char magic[2]; /* type of file */
char vstamp[2]; /* version stamp */
char tsize[4]; /* text size in bytes, padded to FW bdry*/
char dsize[4]; /* initialized data " " */
char bsize[4]; /* uninitialized data " " */
char entry[4]; /* entry pt. */
char text_start[4]; /* base of text used for this file */
#ifndef BFD64
char data_start[4]; /* base of data used for this file */
#endif
}
AOUTHDR;
#define PE32MAGIC 0x10b /* 32-bit image */
#define PE32PMAGIC 0x20b /* 32-bit image inside 64-bit address space */
#define PE32PBADMAG(x) (((x).f_magic != PE32PMAGIC))
#define AOUTSZ 108
#define AOUTHDRSZ 108
#define OMAGIC 0404 /* object files, eg as output */
#define ZMAGIC 0413 /* demand load format, eg normal ld output */
#define STMAGIC 0401 /* target shlib */
#define SHMAGIC 0443 /* host shlib */
/* define some NT default values */
/* #define NT_IMAGE_BASE 0x400000 moved to internal.h */
#define NT_SECTION_ALIGNMENT 0x1000
#define NT_FILE_ALIGNMENT 0x200
#define NT_DEF_RESERVE 0x100000
#define NT_DEF_COMMIT 0x1000
/********************** SECTION HEADER **********************/
struct external_scnhdr {
char s_name[8]; /* section name */
char s_paddr[4]; /* physical address, aliased s_nlib */
char s_vaddr[4]; /* virtual address */
char s_size[4]; /* section size */
char s_scnptr[4]; /* file ptr to raw data for section */
char s_relptr[4]; /* file ptr to relocation */
char s_lnnoptr[4]; /* file ptr to line numbers */
char s_nreloc[2]; /* number of relocation entries */
char s_nlnno[2]; /* number of line number entries*/
char s_flags[4]; /* flags */
};
#define SCNHDR struct external_scnhdr
#define SCNHSZ 40
/*
* names of "special" sections
*/
#define _TEXT ".text"
#define _DATA ".data"
#define _BSS ".bss"
#define _COMMENT ".comment"
#define _LIB ".lib"
/********************** LINE NUMBERS **********************/
/* 1 line number entry for every "breakpointable" source line in a section.
* Line numbers are grouped on a per function basis; first entry in a function
* grouping will have l_lnno = 0 and in place of physical address will be the
* symbol table index of the function name.
*/
struct external_lineno {
union {
char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
char l_paddr[4]; /* (physical) address of line number */
} l_addr;
char l_lnno[2]; /* line number */
};
#define LINENO struct external_lineno
#define LINESZ 6
/********************** SYMBOLS **********************/
#define E_SYMNMLEN 8 /* # characters in a symbol name */
#define E_FILNMLEN 14 /* # characters in a file name */
#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */
struct external_syment
{
union {
char e_name[E_SYMNMLEN];
struct {
char e_zeroes[4];
char e_offset[4];
} e;
} e;
char e_value[4];
char e_scnum[2];
char e_type[2];
char e_sclass[1];
char e_numaux[1];
};
#define N_BTMASK (0xf)
#define N_TMASK (0x30)
#define N_BTSHFT (4)
#define N_TSHIFT (2)
union external_auxent {
struct {
char x_tagndx[4]; /* str, un, or enum tag indx */
union {
struct {
char x_lnno[2]; /* declaration line number */
char x_size[2]; /* str/union/array size */
} x_lnsz;
char x_fsize[4]; /* size of function */
} x_misc;
union {
struct { /* if ISFCN, tag, or .bb */
char x_lnnoptr[4]; /* ptr to fcn line # */
char x_endndx[4]; /* entry ndx past block end */
} x_fcn;
struct { /* if ISARY, up to 4 dimen. */
char x_dimen[E_DIMNUM][2];
} x_ary;
} x_fcnary;
char x_tvndx[2]; /* tv index */
} x_sym;
union {
char x_fname[E_FILNMLEN];
struct {
char x_zeroes[4];
char x_offset[4];
} x_n;
} x_file;
struct {
char x_scnlen[4]; /* section length */
char x_nreloc[2]; /* # relocation entries */
char x_nlinno[2]; /* # line numbers */
char x_checksum[4]; /* section COMDAT checksum */
char x_associated[2]; /* COMDAT associated section index */
char x_comdat[1]; /* COMDAT selection number */
} x_scn;
struct {
char x_tvfill[4]; /* tv fill value */
char x_tvlen[2]; /* length of .tv */
char x_tvran[2][2]; /* tv range */
} x_tv; /* info about .tv section (in auxent of symbol .tv)) */
};
#define SYMENT struct external_syment
#define SYMESZ 18
#define AUXENT union external_auxent
#define AUXESZ 18
# define _ETEXT "etext"
/********************** RELOCATION DIRECTIVES **********************/
struct external_reloc {
char r_vaddr[4];
char r_symndx[4];
char r_type[2];
};
#define RELOC struct external_reloc
#define RELSZ 10

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/* IBM RS/6000 "XCOFF" file definitions for BFD.
Copyright (C) 1990, 1991 Free Software Foundation, Inc.
FIXME: Can someone provide a transliteration of this name into ASCII?
Using the following chars caused a compiler warning on HIUX (so I replaced
them with octal escapes), and isn't useful without an understanding of what
character set it is.
Written by Mimi Ph\373\364ng-Th\345o V\365 of IBM
and John Gilmore of Cygnus Support. */
/********************** FILE HEADER **********************/
struct external_filehdr {
char f_magic[2]; /* magic number */
char f_nscns[2]; /* number of sections */
char f_timdat[4]; /* time & date stamp */
char f_symptr[4]; /* file pointer to symtab */
char f_nsyms[4]; /* number of symtab entries */
char f_opthdr[2]; /* sizeof(optional hdr) */
char f_flags[2]; /* flags */
};
/* IBM RS/6000 */
#define U802WRMAGIC 0730 /* writeable text segments **chh** */
#define U802ROMAGIC 0735 /* readonly sharable text segments */
#define U802TOCMAGIC 0737 /* readonly text segments and TOC */
#define BADMAG(x) \
((x).f_magic != U802ROMAGIC && (x).f_magic != U802WRMAGIC && \
(x).f_magic != U802TOCMAGIC)
#define FILHDR struct external_filehdr
#define FILHSZ 20
/********************** AOUT "OPTIONAL HEADER" **********************/
typedef struct
{
unsigned char magic[2]; /* type of file */
unsigned char vstamp[2]; /* version stamp */
unsigned char tsize[4]; /* text size in bytes, padded to FW bdry */
unsigned char dsize[4]; /* initialized data " " */
unsigned char bsize[4]; /* uninitialized data " " */
unsigned char entry[4]; /* entry pt. */
unsigned char text_start[4]; /* base of text used for this file */
unsigned char data_start[4]; /* base of data used for this file */
unsigned char o_toc[4]; /* address of TOC */
unsigned char o_snentry[2]; /* section number of entry point */
unsigned char o_sntext[2]; /* section number of .text section */
unsigned char o_sndata[2]; /* section number of .data section */
unsigned char o_sntoc[2]; /* section number of TOC */
unsigned char o_snloader[2]; /* section number of .loader section */
unsigned char o_snbss[2]; /* section number of .bss section */
unsigned char o_algntext[2]; /* .text alignment */
unsigned char o_algndata[2]; /* .data alignment */
unsigned char o_modtype[2]; /* module type (??) */
unsigned char o_cputype[2]; /* cpu type */
unsigned char o_maxstack[4]; /* max stack size (??) */
unsigned char o_maxdata[4]; /* max data size (??) */
unsigned char o_resv2[12]; /* reserved */
}
AOUTHDR;
#define AOUTSZ 72
#define SMALL_AOUTSZ (28)
#define AOUTHDRSZ 72
#define RS6K_AOUTHDR_OMAGIC 0x0107 /* old: text & data writeable */
#define RS6K_AOUTHDR_NMAGIC 0x0108 /* new: text r/o, data r/w */
#define RS6K_AOUTHDR_ZMAGIC 0x010B /* paged: text r/o, both page-aligned */
/********************** SECTION HEADER **********************/
struct external_scnhdr {
char s_name[8]; /* section name */
char s_paddr[4]; /* physical address, aliased s_nlib */
char s_vaddr[4]; /* virtual address */
char s_size[4]; /* section size */
char s_scnptr[4]; /* file ptr to raw data for section */
char s_relptr[4]; /* file ptr to relocation */
char s_lnnoptr[4]; /* file ptr to line numbers */
char s_nreloc[2]; /* number of relocation entries */
char s_nlnno[2]; /* number of line number entries*/
char s_flags[4]; /* flags */
};
/*
* names of "special" sections
*/
#define _TEXT ".text"
#define _DATA ".data"
#define _BSS ".bss"
#define _PAD ".pad"
#define _LOADER ".loader"
#define SCNHDR struct external_scnhdr
#define SCNHSZ 40
/* XCOFF uses a special .loader section with type STYP_LOADER. */
#define STYP_LOADER 0x1000
/* XCOFF uses a special .debug section with type STYP_DEBUG. */
#define STYP_DEBUG 0x2000
/* XCOFF handles line number or relocation overflow by creating
another section header with STYP_OVRFLO set. */
#define STYP_OVRFLO 0x8000
/********************** LINE NUMBERS **********************/
/* 1 line number entry for every "breakpointable" source line in a section.
* Line numbers are grouped on a per function basis; first entry in a function
* grouping will have l_lnno = 0 and in place of physical address will be the
* symbol table index of the function name.
*/
struct external_lineno {
union {
char l_symndx[4]; /* function name symbol index, iff l_lnno == 0*/
char l_paddr[4]; /* (physical) address of line number */
} l_addr;
char l_lnno[2]; /* line number */
};
#define LINENO struct external_lineno
#define LINESZ 6
/********************** SYMBOLS **********************/
#define E_SYMNMLEN 8 /* # characters in a symbol name */
#define E_FILNMLEN 14 /* # characters in a file name */
#define E_DIMNUM 4 /* # array dimensions in auxiliary entry */
struct external_syment
{
union {
char e_name[E_SYMNMLEN];
struct {
char e_zeroes[4];
char e_offset[4];
} e;
} e;
char e_value[4];
char e_scnum[2];
char e_type[2];
char e_sclass[1];
char e_numaux[1];
};
#define N_BTMASK (017)
#define N_TMASK (060)
#define N_BTSHFT (4)
#define N_TSHIFT (2)
union external_auxent {
struct {
char x_tagndx[4]; /* str, un, or enum tag indx */
union {
struct {
char x_lnno[2]; /* declaration line number */
char x_size[2]; /* str/union/array size */
} x_lnsz;
char x_fsize[4]; /* size of function */
} x_misc;
union {
struct { /* if ISFCN, tag, or .bb */
char x_lnnoptr[4]; /* ptr to fcn line # */
char x_endndx[4]; /* entry ndx past block end */
} x_fcn;
struct { /* if ISARY, up to 4 dimen. */
char x_dimen[E_DIMNUM][2];
} x_ary;
} x_fcnary;
char x_tvndx[2]; /* tv index */
} x_sym;
union {
char x_fname[E_FILNMLEN];
struct {
char x_zeroes[4];
char x_offset[4];
} x_n;
} x_file;
struct {
char x_scnlen[4]; /* section length */
char x_nreloc[2]; /* # relocation entries */
char x_nlinno[2]; /* # line numbers */
} x_scn;
struct {
char x_tvfill[4]; /* tv fill value */
char x_tvlen[2]; /* length of .tv */
char x_tvran[2][2]; /* tv range */
} x_tv; /* info about .tv section (in auxent of symbol .tv)) */
struct {
unsigned char x_scnlen[4];
unsigned char x_parmhash[4];
unsigned char x_snhash[2];
unsigned char x_smtyp[1];
unsigned char x_smclas[1];
unsigned char x_stab[4];
unsigned char x_snstab[2];
} x_csect;
};
#define SYMENT struct external_syment
#define SYMESZ 18
#define AUXENT union external_auxent
#define AUXESZ 18
#define DBXMASK 0x80 /* for dbx storage mask */
#define SYMNAME_IN_DEBUG(symptr) ((symptr)->n_sclass & DBXMASK)
/********************** RELOCATION DIRECTIVES **********************/
struct external_reloc {
char r_vaddr[4];
char r_symndx[4];
char r_size[1];
char r_type[1];
};
#define RELOC struct external_reloc
#define RELSZ 10
#define DEFAULT_DATA_SECTION_ALIGNMENT 4
#define DEFAULT_BSS_SECTION_ALIGNMENT 4
#define DEFAULT_TEXT_SECTION_ALIGNMENT 4
/* For new sections we havn't heard of before */
#define DEFAULT_SECTION_ALIGNMENT 4

391
contrib/binutils/include/opcode/ia64.h Normal file
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/* ia64.h -- Header file for ia64 opcode table
Copyright (C) 1998, 1999 David Mosberger-Tang <davidm@hpl.hp.com>
See the file HP-COPYRIGHT for additional information. */
#ifndef opcode_ia64_h
#define opcode_ia64_h
#include <sys/types.h>
#include <bfd.h>
typedef BFD_HOST_U_64_BIT ia64_insn;
enum ia64_insn_type
{
IA64_TYPE_NIL = 0, /* illegal type */
IA64_TYPE_A, /* integer alu (I- or M-unit) */
IA64_TYPE_I, /* non-alu integer (I-unit) */
IA64_TYPE_M, /* memory (M-unit) */
IA64_TYPE_B, /* branch (B-unit) */
IA64_TYPE_F, /* floating-point (F-unit) */
IA64_TYPE_X, /* long encoding (X-unit) */
IA64_TYPE_DYN, /* Dynamic opcode */
IA64_NUM_TYPES
};
enum ia64_unit
{
IA64_UNIT_NIL = 0, /* illegal unit */
IA64_UNIT_I, /* integer unit */
IA64_UNIT_M, /* memory unit */
IA64_UNIT_B, /* branching unit */
IA64_UNIT_F, /* floating-point unit */
IA64_UNIT_L, /* long "unit" */
IA64_UNIT_X, /* may be integer or branch unit */
IA64_NUM_UNITS
};
/* Changes to this enumeration must be propagated to the operand table in
bfd/cpu-ia64-opc.c
*/
enum ia64_opnd
{
IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/
/* constants */
IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */
IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */
IA64_OPND_C1, /* the constant 1 */
IA64_OPND_C8, /* the constant 8 */
IA64_OPND_C16, /* the constant 16 */
IA64_OPND_GR0, /* gr0 */
IA64_OPND_IP, /* instruction pointer (ip) */
IA64_OPND_PR, /* predicate register (pr) */
IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */
IA64_OPND_PSR, /* processor status register (psr) */
IA64_OPND_PSR_L, /* processor status register L (psr.l) */
IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */
/* register operands: */
IA64_OPND_AR3, /* third application register # (bits 20-26) */
IA64_OPND_B1, /* branch register # (bits 6-8) */
IA64_OPND_B2, /* branch register # (bits 13-15) */
IA64_OPND_CR3, /* third control register # (bits 20-26) */
IA64_OPND_F1, /* first floating-point register # */
IA64_OPND_F2, /* second floating-point register # */
IA64_OPND_F3, /* third floating-point register # */
IA64_OPND_F4, /* fourth floating-point register # */
IA64_OPND_P1, /* first predicate # */
IA64_OPND_P2, /* second predicate # */
IA64_OPND_R1, /* first register # */
IA64_OPND_R2, /* second register # */
IA64_OPND_R3, /* third register # */
IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */
/* indirect operands: */
IA64_OPND_CPUID_R3, /* cpuid[reg] */
IA64_OPND_DBR_R3, /* dbr[reg] */
IA64_OPND_DTR_R3, /* dtr[reg] */
IA64_OPND_ITR_R3, /* itr[reg] */
IA64_OPND_IBR_R3, /* ibr[reg] */
IA64_OPND_MR3, /* memory at addr of third register # */
IA64_OPND_MSR_R3, /* msr[reg] */
IA64_OPND_PKR_R3, /* pkr[reg] */
IA64_OPND_PMC_R3, /* pmc[reg] */
IA64_OPND_PMD_R3, /* pmd[reg] */
IA64_OPND_RR_R3, /* rr[reg] */
/* immediate operands: */
IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */
IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */
IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */
IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */
IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */
IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */
IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */
IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */
IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */
IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */
IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */
IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */
IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */
IA64_OPND_SOF, /* 8-bit stack frame size */
IA64_OPND_SOL, /* 8-bit size of locals */
IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */
IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */
IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/
IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */
IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */
IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */
IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */
IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */
IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */
IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */
IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */
IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */
IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */
IA64_OPND_IMMU62, /* unsigned 62-bit immediate */
IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */
IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */
IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */
IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */
IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */
IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */
IA64_OPND_POS6, /* 6-bit count (bits 14-19) */
IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */
IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */
IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */
IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */
IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */
IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */
IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */
};
enum ia64_dependency_mode
{
IA64_DV_RAW,
IA64_DV_WAW,
IA64_DV_WAR,
};
enum ia64_dependency_semantics
{
IA64_DVS_NONE,
IA64_DVS_IMPLIED,
IA64_DVS_IMPLIEDF,
IA64_DVS_DATA,
IA64_DVS_INSTR,
IA64_DVS_SPECIFIC,
IA64_DVS_STOP,
IA64_DVS_OTHER,
};
enum ia64_resource_specifier
{
IA64_RS_ANY,
IA64_RS_AR_K,
IA64_RS_AR_UNAT,
IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */
IA64_RS_ARb, /* 48-63, 112-127 */
IA64_RS_BR,
IA64_RS_CFM,
IA64_RS_CPUID,
IA64_RS_CR_IRR,
IA64_RS_CR_LRR,
IA64_RS_CR, /* 3-7,10-15,18,26-63,75-79,82-127 */
IA64_RS_DBR,
IA64_RS_FR,
IA64_RS_FRb,
IA64_RS_GR0,
IA64_RS_GR,
IA64_RS_IBR,
IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */
IA64_RS_MSR,
IA64_RS_PKR,
IA64_RS_PMC,
IA64_RS_PMD,
IA64_RS_PR, /* non-rotating, 1-15 */
IA64_RS_PRr, /* rotating, 16-62 */
IA64_RS_PR63,
IA64_RS_RR,
IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */
IA64_RS_CRX, /* CRs not in RS_CR */
IA64_RS_PSR, /* PSR bits */
IA64_RS_RSE, /* implementation-specific RSE resources */
IA64_RS_AR_FPSR,
};
enum ia64_rse_resource
{
IA64_RSE_N_STACKED_PHYS,
IA64_RSE_BOF,
IA64_RSE_STORE_REG,
IA64_RSE_LOAD_REG,
IA64_RSE_BSPLOAD,
IA64_RSE_RNATBITINDEX,
IA64_RSE_CFLE,
IA64_RSE_NDIRTY,
};
/* Information about a given resource dependency */
struct ia64_dependency
{
/* Name of the resource */
const char *name;
/* Does this dependency need further specification? */
enum ia64_resource_specifier specifier;
/* Mode of dependency */
enum ia64_dependency_mode mode;
/* Dependency semantics */
enum ia64_dependency_semantics semantics;
/* Register index, if applicable (distinguishes AR, CR, and PSR deps) */
#define REG_NONE (-1)
int regindex;
/* Special info on semantics */
const char *info;
};
/* Two arrays of indexes into the ia64_dependency table.
chks are dependencies to check for conflicts when an opcode is
encountered; regs are dependencies to register (mark as used) when an
opcode is used. chks correspond to readers (RAW) or writers (WAW or
WAR) of a resource, while regs correspond to writers (RAW or WAW) and
readers (WAR) of a resource. */
struct ia64_opcode_dependency
{
int nchks;
const unsigned short *chks;
int nregs;
const unsigned short *regs;
};
/* encode/extract the note/index for a dependency */
#define RDEP(N,X) (((N)<<11)|(X))
#define NOTE(X) (((X)>>11)&0x1F)
#define DEP(X) ((X)&0x7FF)
/* A template descriptor describes the execution units that are active
for each of the three slots. It also specifies the location of
instruction group boundaries that may be present between two slots. */
struct ia64_templ_desc
{
int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */
enum ia64_unit exec_unit[3];
const char *name;
};
/* The opcode table is an array of struct ia64_opcode. */
struct ia64_opcode
{
/* The opcode name. */
const char *name;
/* The type of the instruction: */
enum ia64_insn_type type;
/* Number of output operands: */
int num_outputs;
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
ia64_insn opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
ia64_insn mask;
/* An array of operand codes. Each code is an index into the
operand table. They appear in the order which the operands must
appear in assembly code, and are terminated by a zero. */
enum ia64_opnd operands[5];
/* One bit flags for the opcode. These are primarily used to
indicate specific processors and environments support the
instructions. The defined values are listed below. */
unsigned int flags;
/* Used by ia64_find_next_opcode (). */
short ent_index;
/* Opcode dependencies. */
const struct ia64_opcode_dependency *dependencies;
};
/* Values defined for the flags field of a struct ia64_opcode. */
#define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */
#define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */
#define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */
#define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */
#define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */
#define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */
#define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */
#define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */
#define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */
#define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */
#define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */
/* A macro to extract the major opcode from an instruction. */
#define IA64_OP(i) (((i) >> 37) & 0xf)
enum ia64_operand_class
{
IA64_OPND_CLASS_CST, /* constant */
IA64_OPND_CLASS_REG, /* register */
IA64_OPND_CLASS_IND, /* indirect register */
IA64_OPND_CLASS_ABS, /* absolute value */
IA64_OPND_CLASS_REL, /* IP-relative value */
};
/* The operands table is an array of struct ia64_operand. */
struct ia64_operand
{
enum ia64_operand_class class;
/* Set VALUE as the operand bits for the operand of type SELF in the
instruction pointed to by CODE. If an error occurs, *CODE is not
modified and the returned string describes the cause of the
error. If no error occurs, NULL is returned. */
const char *(*insert) (const struct ia64_operand *self, ia64_insn value,
ia64_insn *code);
/* Extract the operand bits for an operand of type SELF from
instruction CODE store them in *VALUE. If an error occurs, the
cause of the error is described by the string returned. If no
error occurs, NULL is returned. */
const char *(*extract) (const struct ia64_operand *self, ia64_insn code,
ia64_insn *value);
/* A string whose meaning depends on the operand class. */
const char *str;
struct bit_field
{
/* The number of bits in the operand. */
int bits;
/* How far the operand is left shifted in the instruction. */
int shift;
}
field[4]; /* no operand has more than this many bit-fields */
unsigned int flags;
const char *desc; /* brief description */
};
/* Values defined for the flags field of a struct ia64_operand. */
/* Disassemble as signed decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0)
/* Disassemble as unsigned decimal (instead of hex): */
#define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1)
extern const struct ia64_templ_desc ia64_templ_desc[16];
/* The tables are sorted by major opcode number and are otherwise in
the order in which the disassembler should consider instructions. */
extern struct ia64_opcode ia64_opcodes_a[];
extern struct ia64_opcode ia64_opcodes_i[];
extern struct ia64_opcode ia64_opcodes_m[];
extern struct ia64_opcode ia64_opcodes_b[];
extern struct ia64_opcode ia64_opcodes_f[];
extern struct ia64_opcode ia64_opcodes_d[];
extern struct ia64_opcode *ia64_find_opcode (const char *name);
extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *ent);
extern struct ia64_opcode *ia64_dis_opcode (ia64_insn insn,
enum ia64_insn_type type);
extern void ia64_free_opcode (struct ia64_opcode *ent);
extern const struct ia64_dependency *ia64_find_dependency (int index);
/* To avoid circular library dependencies, this array is implemented
in bfd/cpu-ia64-opc.c: */
extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT];
#endif /* opcode_ia64_h */

15
contrib/binutils/ld/emulparams/elf64_ia64.sh Normal file
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# See genscripts.sh and ../scripttempl/elf.sc for the meaning of these.
SCRIPT_NAME=elf
ELFSIZE=64
TEMPLATE_NAME=elf32
OUTPUT_FORMAT="elf64-ia64-little"
ARCH=ia64
MACHINE=
MAXPAGESIZE=0x10000
TEXT_START_ADDR="0x4000000000000000"
DATA_ADDR="0x6000000000000000 + (. & (${MAXPAGESIZE} - 1))"
GENERATE_SHLIB_SCRIPT=yes
NOP=0x00300000010070000002000001000400 # a bundle full of nops
OTHER_GOT_SECTIONS='.IA_64.pltoff : { *(.IA_64.pltoff) }'
OTHER_PLT_RELOC_SECTIONS='.rela.IA_64.pltoff : { *(.rela.IA_64.pltoff) }'
OTHER_READONLY_SECTIONS='.opd : { *(.opd) } .IA_64.unwind_info : { *(.IA_64.unwind_info*) } .IA_64.unwind : { *(.IA_64.unwind*) }'

689
contrib/binutils/ltcf-c.sh Normal file
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#### This script is meant to be sourced by ltconfig.
# ltcf-c.sh - Create a C compiler specific configuration
#
# Copyright (C) 1996-2000 Free Software Foundation, Inc.
# Originally by Gordon Matzigkeit <gord@gnu.ai.mit.edu>, 1996
#
# This file is free software; you can redistribute it and/or modify it
# under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful, but
# WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
# General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
#
# As a special exception to the GNU General Public License, if you
# distribute this file as part of a program that contains a
# configuration script generated by Autoconf, you may include it under
# the same distribution terms that you use for the rest of that program.
# Source file extension for C test sources.
ac_ext=c
# Object file extension for compiled C test sources.
objext=o
# Code to be used in simple compile tests
lt_simple_compile_test_code="int some_variable = 0;"
# Code to be used in simple link tests
lt_simple_link_test_code='main(){return(0);}'
## Linker Characteristics
case "$host_os" in
cygwin* | mingw*)
# FIXME: the MSVC++ port hasn't been tested in a loooong time
# When not using gcc, we currently assume that we are using
# Microsoft Visual C++.
if test "$with_gcc" != yes; then
with_gnu_ld=no
fi
;;
esac
ld_shlibs=yes
if test "$with_gnu_ld" = yes; then
# If archive_cmds runs LD, not CC, wlarc should be empty
wlarc='${wl}'
# See if GNU ld supports shared libraries.
case "$host_os" in
aix3* | aix4*)
# On AIX, the GNU linker is very broken
ld_shlibs=no
cat <<EOF 1>&2
*** Warning: the GNU linker, at least up to release 2.9.1, is reported
*** to be unable to reliably create shared libraries on AIX.
*** Therefore, libtool is disabling shared libraries support. If you
*** really care for shared libraries, you may want to modify your PATH
*** so that a non-GNU linker is found, and then restart.
EOF
;;
amigaos*)
archive_cmds='$rm $output_objdir/a2ixlibrary.data~$echo "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$echo "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$echo "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$echo "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
hardcode_libdir_flag_spec='-L$libdir'
hardcode_minus_L=yes
# Samuel A. Falvo II <kc5tja@dolphin.openprojects.net> reports
# that the semantics of dynamic libraries on AmigaOS, at least up
# to version 4, is to share data among multiple programs linked
# with the same dynamic library. Since this doesn't match the
# behavior of shared libraries on other platforms, we can use
# them.
ld_shlibs=no
;;
beos*)
if $LD --help 2>&1 | egrep ': supported targets:.* elf' > /dev/null; then
allow_undefined_flag=unsupported
# Joseph Beckenbach <jrb3@best.com> says some releases of gcc
# support --undefined. This deserves some investigation. FIXME
archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
else
ld_shlibs=no
fi
;;
cygwin* | mingw*)
# hardcode_libdir_flag_spec is actually meaningless, as there is
# no search path for DLLs.
hardcode_libdir_flag_spec='-L$libdir'
allow_undefined_flag=unsupported
always_export_symbols=yes
extract_expsyms_cmds='test -f $output_objdir/impgen.c || \
sed -e "/^# \/\* impgen\.c starts here \*\//,/^# \/\* impgen.c ends here \*\// { s/^# //; p; }" -e d < $0 > $output_objdir/impgen.c~
test -f $output_objdir/impgen.exe || (cd $output_objdir && \
if test "x$HOST_CC" != "x" ; then $HOST_CC -o impgen impgen.c ; \
else $CC -o impgen impgen.c ; fi)~
$output_objdir/impgen $dir/$soname > $output_objdir/$soname-def'
old_archive_from_expsyms_cmds='$DLLTOOL --as=$AS --dllname $soname --def $output_objdir/$soname-def --output-lib $output_objdir/$newlib'
# cygwin and mingw dlls have different entry points and sets of symbols
# to exclude.
# FIXME: what about values for MSVC?
dll_entry=__cygwin_dll_entry@12
dll_exclude_symbols=DllMain@12,_cygwin_dll_entry@12,_cygwin_noncygwin_dll_entry@12~
case "$host_os" in
mingw*)
# mingw values
dll_entry=_DllMainCRTStartup@12
dll_exclude_symbols=DllMain@12,DllMainCRTStartup@12,DllEntryPoint@12~
;;
esac
# mingw and cygwin differ, and it's simplest to just exclude the union
# of the two symbol sets.
dll_exclude_symbols=DllMain@12,_cygwin_dll_entry@12,_cygwin_noncygwin_dll_entry@12,DllMainCRTStartup@12,DllEntryPoint@12
# recent cygwin and mingw systems supply a stub DllMain which the user
# can override, but on older systems we have to supply one (in ltdll.c)
if test "x$lt_cv_need_dllmain" = "xyes"; then
ltdll_obj='$output_objdir/$soname-ltdll.'"$objext "
ltdll_cmds='test -f $output_objdir/$soname-ltdll.c || sed -e "/^# \/\* ltdll\.c starts here \*\//,/^# \/\* ltdll.c ends here \*\// { s/^# //; p; }" -e d < $0 > $output_objdir/$soname-ltdll.c~
test -f $output_objdir/$soname-ltdll.$objext || (cd $output_objdir && $CC -c $soname-ltdll.c)~'
else
ltdll_obj=
ltdll_cmds=
fi
# Extract the symbol export list from an `--export-all' def file,
# then regenerate the def file from the symbol export list, so that
# the compiled dll only exports the symbol export list.
# Be careful not to strip the DATA tag left be newer dlltools.
export_symbols_cmds="$ltdll_cmds"'
$DLLTOOL --export-all --exclude-symbols '$dll_exclude_symbols' --output-def $output_objdir/$soname-def '$ltdll_obj'$libobjs $convenience~
sed -e "1,/EXPORTS/d" -e "s/ @ [0-9]*//" -e "s/ *;.*$//" < $output_objdir/$soname-def > $export_symbols'
# If DATA tags from a recent dlltool are present, honour them!
archive_expsym_cmds='echo EXPORTS > $output_objdir/$soname-def~
_lt_hint=1;
cat $export_symbols | while read symbol; do
set dummy \$symbol;
case \$# in
2) echo " \$2 @ \$_lt_hint ; " >> $output_objdir/$soname-def;;
*) echo " \$2 @ \$_lt_hint \$3 ; " >> $output_objdir/$soname-def;;
esac;
_lt_hint=`expr 1 + \$_lt_hint`;
done~
'"$ltdll_cmds"'
$CC -Wl,--base-file,$output_objdir/$soname-base '$lt_cv_cc_dll_switch' -Wl,-e,'$dll_entry' -o $lib '$ltdll_obj'$libobjs $deplibs $compiler_flags~
$DLLTOOL --as=$AS --dllname $soname --exclude-symbols '$dll_exclude_symbols' --def $output_objdir/$soname-def --base-file $output_objdir/$soname-base --output-exp $output_objdir/$soname-exp~
$CC -Wl,--base-file,$output_objdir/$soname-base $output_objdir/$soname-exp '$lt_cv_cc_dll_switch' -Wl,-e,'$dll_entry' -o $lib '$ltdll_obj'$libobjs $deplibs $compiler_flags~
$DLLTOOL --as=$AS --dllname $soname --exclude-symbols '$dll_exclude_symbols' --def $output_objdir/$soname-def --base-file $output_objdir/$soname-base --output-exp $output_objdir/$soname-exp~
$CC $output_objdir/$soname-exp '$lt_cv_cc_dll_switch' -Wl,-e,'$dll_entry' -o $lib '$ltdll_obj'$libobjs $deplibs $compiler_flags'
;;
netbsd*)
if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then
archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib'
wlarc=
else
archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
fi
;;
solaris* | sysv5*)
if $LD -v 2>&1 | egrep 'BFD 2\.8' > /dev/null; then
ld_shlibs=no
cat <<EOF 1>&2
*** Warning: The releases 2.8.* of the GNU linker cannot reliably
*** create shared libraries on Solaris systems. Therefore, libtool
*** is disabling shared libraries support. We urge you to upgrade GNU
*** binutils to release 2.9.1 or newer. Another option is to modify
*** your PATH or compiler configuration so that the native linker is
*** used, and then restart.
EOF
elif $LD --help 2>&1 | egrep ': supported targets:.* elf' > /dev/null; then
archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
else
ld_shlibs=no
fi
;;
sunos4*)
archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags'
wlarc=
hardcode_direct=yes
hardcode_shlibpath_var=no
;;
*)
if $LD --help 2>&1 | egrep ': supported targets:.* elf' > /dev/null; then
archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib'
archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib'
else
ld_shlibs=no
fi
;;
esac
if test "$ld_shlibs" = yes; then
runpath_var=LD_RUN_PATH
hardcode_libdir_flag_spec='${wl}--rpath ${wl}$libdir'
export_dynamic_flag_spec='${wl}--export-dynamic'
case $host_os in
cygwin* | mingw*)
# dlltool doesn't understand --whole-archive et. al.
whole_archive_flag_spec=
;;
*)
# ancient GNU ld didn't support --whole-archive et. al.
if $LD --help 2>&1 | egrep 'no-whole-archive' > /dev/null; then
whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive'
else
whole_archive_flag_spec=
fi
;;
esac
fi
else
# PORTME fill in a description of your system's linker (not GNU ld)
case "$host_os" in
aix3*)
allow_undefined_flag=unsupported
always_export_symbols=yes
archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname'
# Note: this linker hardcodes the directories in LIBPATH if there
# are no directories specified by -L.
hardcode_minus_L=yes
if test "$with_gcc" = yes && test -z "$link_static_flag"; then
# Neither direct hardcoding nor static linking is supported with a
# broken collect2.
hardcode_direct=unsupported
fi
;;
aix4*)
hardcode_libdir_flag_spec='${wl}-b ${wl}nolibpath ${wl}-b ${wl}libpath:$libdir:/usr/lib:/lib'
hardcode_libdir_separator=':'
if test "$with_gcc" = yes; then
collect2name=`${CC} -print-prog-name=collect2`
if test -f "$collect2name" && \
strings "$collect2name" | grep resolve_lib_name >/dev/null
then
# We have reworked collect2
hardcode_direct=yes
else
# We have old collect2
hardcode_direct=unsupported
# It fails to find uninstalled libraries when the uninstalled
# path is not listed in the libpath. Setting hardcode_minus_L
# to unsupported forces relinking
hardcode_minus_L=yes
hardcode_libdir_flag_spec='-L$libdir'
hardcode_libdir_separator=
fi
shared_flag='-shared'
else
shared_flag='${wl}-bM:SRE'
hardcode_direct=yes
fi
allow_undefined_flag=' ${wl}-berok'
archive_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs $compiler_flags ${wl}-bexpall ${wl}-bnoentry${allow_undefined_flag}'
archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs $compiler_flags ${wl}-bE:$export_symbols ${wl}-bnoentry${allow_undefined_flag}'
case "$host_os" in aix4.[01]|aix4.[01].*)
# According to Greg Wooledge, -bexpall is only supported from AIX 4.2 on
always_export_symbols=yes ;;
esac
;;
amigaos*)
archive_cmds='$rm $output_objdir/a2ixlibrary.data~$echo "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$echo "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$echo "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$echo "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)'
hardcode_libdir_flag_spec='-L$libdir'
hardcode_minus_L=yes
# see comment about different semantics on the GNU ld section
ld_shlibs=no
;;
cygwin* | mingw*)
# When not using gcc, we currently assume that we are using
# Microsoft Visual C++.
# hardcode_libdir_flag_spec is actually meaningless, as there is
# no search path for DLLs.
hardcode_libdir_flag_spec=' '
allow_undefined_flag=unsupported
# Tell ltmain to make .lib files, not .a files.
libext=lib
# FIXME: Setting linknames here is a bad hack.
archive_cmds='$CC -o $lib $libobjs $compiler_flags `echo "$deplibs" | sed -e '\''s/ -lc$//'\''` -link -dll~linknames='
# The linker will automatically build a .lib file if we build a DLL.
old_archive_from_new_cmds='true'
# FIXME: Should let the user specify the lib program.
old_archive_cmds='lib /OUT:$oldlib$oldobjs$old_deplibs'
fix_srcfile_path='`cygpath -w $srcfile`'
;;
freebsd1*)
ld_shlibs=no
;;
# FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor
# support. Future versions do this automatically, but an explicit c++rt0.o
# does not break anything, and helps significantly (at the cost of a little
# extra space).
freebsd2.2*)
archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o'
hardcode_libdir_flag_spec='-R$libdir'
hardcode_direct=yes
hardcode_shlibpath_var=no
;;
# Unfortunately, older versions of FreeBSD 2 do not have this feature.
freebsd2*)
archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
hardcode_direct=yes
hardcode_minus_L=yes
hardcode_shlibpath_var=no
;;
# FreeBSD 3 and greater uses gcc -shared to do shared libraries.
freebsd*)
archive_cmds='$CC -shared -o $lib $libobjs $deplibs $compiler_flags'
hardcode_libdir_flag_spec='-R$libdir'
hardcode_direct=yes
hardcode_shlibpath_var=no
;;
hpux9* | hpux10* | hpux11*)
case "$host_os" in
hpux9*) archive_cmds='$rm $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' ;;
*) archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' ;;
esac
hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir'
hardcode_libdir_separator=:
hardcode_direct=yes
hardcode_minus_L=yes # Not in the search PATH, but as the default
# location of the library.
export_dynamic_flag_spec='${wl}-E'
;;
irix5* | irix6*)
if test "$with_gcc" = yes; then
archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${objdir}/so_locations -o $lib'
else
archive_cmds='$LD -shared $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${objdir}/so_locations -o $lib'
fi
hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
hardcode_libdir_separator=:
link_all_deplibs=yes
;;
netbsd*)
if echo __ELF__ | $CC -E - | grep __ELF__ >/dev/null; then
archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out
else
archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF
fi
hardcode_libdir_flag_spec='${wl}-R$libdir'
hardcode_direct=yes
hardcode_shlibpath_var=no
;;
openbsd*)
archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags'
hardcode_libdir_flag_spec='-R$libdir'
hardcode_direct=yes
hardcode_shlibpath_var=no
;;
os2*)
hardcode_libdir_flag_spec='-L$libdir'
hardcode_minus_L=yes
allow_undefined_flag=unsupported
archive_cmds='$echo "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$echo "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~$echo DATA >> $output_objdir/$libname.def~$echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~$echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def'
old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def'
;;
osf3*)
if test "$with_gcc" = yes; then
allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${objdir}/so_locations -o $lib'
else
allow_undefined_flag=' -expect_unresolved \*'
archive_cmds='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${objdir}/so_locations -o $lib'
fi
hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
hardcode_libdir_separator=:
;;
osf4* | osf5*) # as osf3* with the addition of -msym flag
if test "$with_gcc" = yes; then
allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*'
archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && echo ${wl}-set_version ${wl}$verstring` ${wl}-update_registry ${wl}${objdir}/so_locations -o $lib'
else
allow_undefined_flag=' -expect_unresolved \*'
archive_cmds='$LD -shared${allow_undefined_flag} $libobjs $deplibs $linker_flags -msym -soname $soname `test -n "$verstring" && echo -set_version $verstring` -update_registry ${objdir}/so_locations -o $lib'
fi
hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir'
hardcode_libdir_separator=:
;;
sco3.2v5*)
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
hardcode_shlibpath_var=no
runpath_var=LD_RUN_PATH
hardcode_runpath_var=yes
;;
solaris*)
no_undefined_flag=' -z text'
# $CC -shared without GNU ld will not create a library from C++
# object files and a static libstdc++, better avoid it by now
archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags'
archive_expsym_cmds='$echo "{ global:" > $lib.exp~cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~
$LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$rm $lib.exp'
hardcode_libdir_flag_spec='-R$libdir'
hardcode_shlibpath_var=no
case "$host_os" in
solaris2.[0-5] | solaris2.[0-5].*) ;;
*) # Supported since Solaris 2.6 (maybe 2.5.1?)
whole_archive_flag_spec='-z allextract$convenience -z defaultextract' ;;
esac
link_all_deplibs=yes
;;
sunos4*)
archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags'
hardcode_libdir_flag_spec='-L$libdir'
hardcode_direct=yes
hardcode_minus_L=yes
hardcode_shlibpath_var=no
;;
sysv4)
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
runpath_var='LD_RUN_PATH'
hardcode_shlibpath_var=no
hardcode_direct=no #Motorola manual says yes, but my tests say they lie
;;
sysv4.3*)
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
hardcode_shlibpath_var=no
export_dynamic_flag_spec='-Bexport'
;;
sysv5*)
no_undefined_flag=' -z text'
# $CC -shared without GNU ld will not create a library from C++
# object files and a static libstdc++, better avoid it by now
archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags'
archive_expsym_cmds='$echo "{ global:" > $lib.exp~cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $lib.exp~$echo "local: *; };" >> $lib.exp~
$LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$rm $lib.exp'
hardcode_libdir_flag_spec=
hardcode_shlibpath_var=no
runpath_var='LD_RUN_PATH'
;;
uts4*)
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
hardcode_libdir_flag_spec='-L$libdir'
hardcode_shlibpath_var=no
;;
dgux*)
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
hardcode_libdir_flag_spec='-L$libdir'
hardcode_shlibpath_var=no
;;
sysv4*MP*)
if test -d /usr/nec; then
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
hardcode_shlibpath_var=no
runpath_var=LD_RUN_PATH
hardcode_runpath_var=yes
ld_shlibs=yes
fi
;;
sysv4.2uw2*)
archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags'
hardcode_direct=yes
hardcode_minus_L=no
hardcode_shlibpath_var=no
hardcode_runpath_var=yes
runpath_var=LD_RUN_PATH
;;
unixware7*)
archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags'
runpath_var='LD_RUN_PATH'
hardcode_shlibpath_var=no
;;
*)
ld_shlibs=no
;;
esac
fi
## Compiler Characteristics: PIC flags, static flags, etc
if test "X${ac_cv_prog_cc_pic+set}" = Xset; then
:
else
ac_cv_prog_cc_pic=
ac_cv_prog_cc_shlib=
ac_cv_prog_cc_wl=
ac_cv_prog_cc_static=
ac_cv_prog_cc_no_builtin=
ac_cv_prog_cc_can_build_shared=$can_build_shared
if test "$with_gcc" = yes; then
ac_cv_prog_cc_wl='-Wl,'
ac_cv_prog_cc_static='-static'
case "$host_os" in
beos* | irix5* | irix6* | osf3* | osf4* | osf5*)
# PIC is the default for these OSes.
;;
aix*)
# Below there is a dirty hack to force normal static linking with -ldl
# The problem is because libdl dynamically linked with both libc and
# libC (AIX C++ library), which obviously doesn't included in libraries
# list by gcc. This cause undefined symbols with -static flags.
# This hack allows C programs to be linked with "-static -ldl", but
# we not sure about C++ programs.
ac_cv_prog_cc_static="$ac_cv_prog_cc_static ${ac_cv_prog_cc_wl}-lC"
;;
cygwin* | mingw* | os2*)
# This hack is so that the source file can tell whether it is being
# built for inclusion in a dll (and should export symbols for example).
ac_cv_prog_cc_pic='-DDLL_EXPORT'
;;
amigaos*)
# FIXME: we need at least 68020 code to build shared libraries, but
# adding the `-m68020' flag to GCC prevents building anything better,
# like `-m68040'.
ac_cv_prog_cc_pic='-m68020 -resident32 -malways-restore-a4'
;;
sysv4*MP*)
if test -d /usr/nec; then
ac_cv_prog_cc_pic=-Kconform_pic
fi
;;
*)
ac_cv_prog_cc_pic='-fPIC'
;;
esac
else
# PORTME Check for PIC flags for the system compiler.
case "$host_os" in
aix3* | aix4*)
# All AIX code is PIC.
ac_cv_prog_cc_static='-bnso -bI:/lib/syscalls.exp'
;;
hpux9* | hpux10* | hpux11*)
# Is there a better ac_cv_prog_cc_static that works with the bundled CC?
ac_cv_prog_cc_wl='-Wl,'
ac_cv_prog_cc_static="${ac_cv_prog_cc_wl}-a ${ac_cv_prog_cc_wl}archive"
ac_cv_prog_cc_pic='+Z'
;;
irix5* | irix6*)
ac_cv_prog_cc_wl='-Wl,'
ac_cv_prog_cc_static='-non_shared'
# PIC (with -KPIC) is the default.
;;
cygwin* | mingw* | os2*)
# This hack is so that the source file can tell whether it is being
# built for inclusion in a dll (and should export symbols for example).
ac_cv_prog_cc_pic='-DDLL_EXPORT'
;;
osf3* | osf4* | osf5*)
# All OSF/1 code is PIC.
ac_cv_prog_cc_wl='-Wl,'
ac_cv_prog_cc_static='-non_shared'
;;
sco3.2v5*)
ac_cv_prog_cc_pic='-Kpic'
ac_cv_prog_cc_static='-dn'
ac_cv_prog_cc_shlib='-belf'
;;
solaris*)
ac_cv_prog_cc_pic='-KPIC'
ac_cv_prog_cc_static='-Bstatic'
ac_cv_prog_cc_wl='-Wl,'
;;
sunos4*)
ac_cv_prog_cc_pic='-PIC'
ac_cv_prog_cc_static='-Bstatic'
ac_cv_prog_cc_wl='-Qoption ld '
;;
sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*)
ac_cv_prog_cc_pic='-KPIC'
ac_cv_prog_cc_static='-Bstatic'
ac_cv_prog_cc_wl='-Wl,'
;;
uts4*)
ac_cv_prog_cc_pic='-pic'
ac_cv_prog_cc_static='-Bstatic'
;;
sysv4*MP*)
if test -d /usr/nec ;then
ac_cv_prog_cc_pic='-Kconform_pic'
ac_cv_prog_cc_static='-Bstatic'
fi
;;
*)
ac_cv_prog_cc_can_build_shared=no
;;
esac
fi
ac_cv_prog_cc_pic="$ac_cv_prog_cc_pic -DPIC"
fi
need_lc=yes
if test "$enable_shared" = yes && test "$with_gcc" = yes; then
case "$archive_cmds" in
*'~'*)
# FIXME: we may have to deal with multi-command sequences.
;;
'$CC '*)
# Test whether the compiler implicitly links with -lc since on some
# systems, -lgcc has to come before -lc. If gcc already passes -lc
# to ld, don't add -lc before -lgcc.
echo $ac_n "checking whether -lc should be explicitly linked in... $ac_c" 1>&6
if eval "test \"`echo '$''{'ac_cv_archive_cmds_needs_lc'+set}'`\" = set"; then
echo $ac_n "(cached) $ac_c" 1>&6
need_lc=$ac_cv_archive_cmds_needs_lc
else
$rm conftest*
echo "static int dummy;" > conftest.$ac_ext
if { (eval echo ltcf-c.sh:need_lc: \"$ac_compile\") 1>&5; (eval $ac_compile) 2>conftest.err; }; then
# Append any warnings to the config.log.
cat conftest.err 1>&5
soname=conftest
lib=conftest
libobjs=conftest.o
deplibs=
wl=$ac_cv_prog_cc_wl
compiler_flags=-v
linker_flags=-v
verstring=
output_objdir=.
libname=conftest
save_allow_undefined_flag=$allow_undefined_flag
allow_undefined_flag=
if { (eval echo ltcf-c.sh:need_lc: \"$archive_cmds\") 1>&5; (eval $archive_cmds) 2>&1 | grep " -lc " 1>&5 ; }; then
need_lc=no
fi
allow_undefined_flag=$save_allow_undefined_flag
else
cat conftest.err 1>&5
fi
fi
$rm conftest*
echo "$ac_t$need_lc" 1>&6
;;
esac
fi
ac_cv_archive_cmds_needs_lc=$need_lc

7436
contrib/binutils/opcodes/ia64-asmtab.c Normal file
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contrib/binutils/opcodes/ia64-asmtab.h Normal file
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/* ia64-asmtab.h -- Header for compacted IA-64 opcode tables.
Copyright 1999, 2000 Free Software Foundation, Inc.
Contributed by Bob Manson of Cygnus Support <manson@cygnus.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#ifndef IA64_ASMTAB_H
#define IA64_ASMTAB_H
#include "opcode/ia64.h"
/* The primary opcode table is made up of the following: */
struct ia64_main_table
{
/* The entry in the string table that corresponds to the name of this
opcode. */
unsigned short name_index;
/* The type of opcode; corresponds to the TYPE field in
struct ia64_opcode. */
unsigned char opcode_type;
/* The number of outputs for this opcode. */
unsigned char num_outputs;
/* The base insn value for this opcode. It may be modified by completers. */
ia64_insn opcode;
/* The mask of valid bits in OPCODE. Zeros indicate operand fields. */
ia64_insn mask;
/* The operands of this instruction. Corresponds to the OPERANDS field
in struct ia64_opcode. */
unsigned char operands[5];
/* The flags for this instruction. Corresponds to the FLAGS field in
struct ia64_opcode. */
short flags;
/* The tree of completers for this instruction; this is an offset into
completer_table. */
short completers;
};
/* Each instruction has a set of possible "completers", or additional
suffixes that can alter the instruction's behavior, and which has
potentially different dependencies.
The completer entries modify certain bits in the instruction opcode.
Which bits are to be modified are marked by the BITS, MASK and
OFFSET fields. The completer entry may also note dependencies for the
opcode.
These completers are arranged in a DAG; the pointers are indexes
into the completer_table array. The completer DAG is searched by
find_completer () and ia64_find_matching_opcode ().
Note that each completer needs to be applied in turn, so that if we
have the instruction
cmp.lt.unc
the completer entries for both "lt" and "unc" would need to be applied
to the opcode's value.
Some instructions do not require any completers; these contain an
empty completer entry. Instructions that require a completer do
not contain an empty entry.
Terminal completers (those completers that validly complete an
instruction) are marked by having the TERMINAL_COMPLETER flag set.
Only dependencies listed in the terminal completer for an opcode are
considered to apply to that opcode instance. */
struct ia64_completer_table
{
/* The bit value that this completer sets. */
unsigned int bits;
/* And its mask. 1s are bits that are to be modified in the
instruction. */
unsigned int mask;
/* The entry in the string table that corresponds to the name of this
completer. */
unsigned short name_index;
/* An alternative completer, or -1 if this is the end of the chain. */
short alternative;
/* A pointer to the DAG of completers that can potentially follow
this one, or -1. */
short subentries;
/* The bit offset in the instruction where BITS and MASK should be
applied. */
unsigned char offset : 7;
unsigned char terminal_completer : 1;
/* Index into the dependency list table */
short dependencies;
};
/* This contains sufficient information for the disassembler to resolve
the complete name of the original instruction. */
struct ia64_dis_names
{
/* COMPLETER_INDEX represents the tree of completers that make up
the instruction. The LSB represents the top of the tree for the
specified instruction.
A 0 bit indicates to go to the next alternate completer via the
alternative field; a 1 bit indicates that the current completer
is part of the instruction, and to go down the subentries index.
We know we've reached the final completer when we run out of 1
bits.
There is always at least one 1 bit. */
unsigned int completer_index : 20;
/* The index in the main_table[] array for the instruction. */
unsigned short insn_index : 11;
/* If set, the next entry in this table is an alternate possibility
for this instruction encoding. Which one to use is determined by
the instruction type and other factors (see opcode_verify ()). */
unsigned int next_flag : 1;
/* The disassembly priority of this entry among instructions. */
unsigned short priority;
};
#endif

273
contrib/binutils/opcodes/ia64-dis.c Normal file
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/* ia64-dis.c -- Disassemble ia64 instructions
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include <assert.h>
#include <string.h>
#include "dis-asm.h"
#include "opcode/ia64.h"
#define NELEMS(a) ((int) (sizeof (a) / sizeof (a[0])))
/* Disassemble ia64 instruction. */
/* Return the instruction type for OPCODE found in unit UNIT. */
static enum ia64_insn_type
unit_to_type (ia64_insn opcode, enum ia64_unit unit)
{
enum ia64_insn_type type;
int op;
op = IA64_OP (opcode);
if (op >= 8 && (unit == IA64_UNIT_I || unit == IA64_UNIT_M))
{
type = IA64_TYPE_A;
}
else
{
switch (unit)
{
case IA64_UNIT_I:
type = IA64_TYPE_I; break;
case IA64_UNIT_M:
type = IA64_TYPE_M; break;
case IA64_UNIT_B:
type = IA64_TYPE_B; break;
case IA64_UNIT_F:
type = IA64_TYPE_F; break;
case IA64_UNIT_L:
case IA64_UNIT_X:
type = IA64_TYPE_X; break;
default:
type = -1;
}
}
return type;
}
int
print_insn_ia64 (bfd_vma memaddr, struct disassemble_info *info)
{
ia64_insn t0, t1, slot[3], template, s_bit, insn;
int slotnum, j, status, need_comma, retval, slot_multiplier;
const struct ia64_operand *odesc;
const struct ia64_opcode *idesc;
const char *err, *str, *tname;
BFD_HOST_U_64_BIT value;
bfd_byte bundle[16];
enum ia64_unit unit;
char regname[16];
if (info->bytes_per_line == 0)
info->bytes_per_line = 6;
info->display_endian = info->endian;
slot_multiplier = info->bytes_per_line;
retval = slot_multiplier;
slotnum = (((long) memaddr) & 0xf) / slot_multiplier;
if (slotnum > 2)
return -1;
memaddr -= (memaddr & 0xf);
status = (*info->read_memory_func) (memaddr, bundle, sizeof (bundle), info);
if (status != 0)
{
(*info->memory_error_func) (status, memaddr, info);
return -1;
}
/* bundles are always in little-endian byte order */
t0 = bfd_getl64 (bundle);
t1 = bfd_getl64 (bundle + 8);
s_bit = t0 & 1;
template = (t0 >> 1) & 0xf;
slot[0] = (t0 >> 5) & 0x1ffffffffffLL;
slot[1] = ((t0 >> 46) & 0x3ffff) | ((t1 & 0x7fffff) << 18);
slot[2] = (t1 >> 23) & 0x1ffffffffffLL;
tname = ia64_templ_desc[template].name;
if (slotnum == 0)
(*info->fprintf_func) (info->stream, "[%s] ", tname);
else
(*info->fprintf_func) (info->stream, " ", tname);
unit = ia64_templ_desc[template].exec_unit[slotnum];
if (template == 2 && slotnum == 1)
{
/* skip L slot in MLI template: */
slotnum = 2;
retval += slot_multiplier;
}
insn = slot[slotnum];
if (unit == IA64_UNIT_NIL)
goto decoding_failed;
idesc = ia64_dis_opcode (insn, unit_to_type (insn, unit));
if (idesc == NULL)
goto decoding_failed;
/* print predicate, if any: */
if ((idesc->flags & IA64_OPCODE_NO_PRED)
|| (insn & 0x3f) == 0)
(*info->fprintf_func) (info->stream, " ");
else
(*info->fprintf_func) (info->stream, "(p%02d) ", (int)(insn & 0x3f));
/* now the actual instruction: */
(*info->fprintf_func) (info->stream, "%s", idesc->name);
if (idesc->operands[0])
(*info->fprintf_func) (info->stream, " ");
need_comma = 0;
for (j = 0; j < NELEMS (idesc->operands) && idesc->operands[j]; ++j)
{
odesc = elf64_ia64_operands + idesc->operands[j];
if (need_comma)
(*info->fprintf_func) (info->stream, ",");
if (odesc - elf64_ia64_operands == IA64_OPND_IMMU64)
{
/* special case of 64 bit immediate load: */
value = ((insn >> 13) & 0x7f) | (((insn >> 27) & 0x1ff) << 7)
| (((insn >> 22) & 0x1f) << 16) | (((insn >> 21) & 0x1) << 21)
| (slot[1] << 22) | (((insn >> 36) & 0x1) << 63);
}
else if (odesc - elf64_ia64_operands == IA64_OPND_IMMU62)
{
/* 62-bit immediate for nop.x/break.x */
value = ((slot[1] & 0x1ffffffffffLL) << 21)
| (((insn >> 36) & 0x1) << 20)
| ((insn >> 6) & 0xfffff);
}
else if (odesc - elf64_ia64_operands == IA64_OPND_TGT64)
{
/* 60-bit immedate for long branches. */
value = (((insn >> 13) & 0xfffff)
| (((insn >> 36) & 1) << 59)
| (slot[1] << 20)) << 4;
}
else
{
err = (*odesc->extract) (odesc, insn, &value);
if (err)
{
(*info->fprintf_func) (info->stream, "%s", err);
goto done;
}
}
switch (odesc->class)
{
case IA64_OPND_CLASS_CST:
(*info->fprintf_func) (info->stream, "%s", odesc->str);
break;
case IA64_OPND_CLASS_REG:
if (odesc->str[0] == 'a' && odesc->str[1] == 'r')
{
switch (value)
{
case 0: case 1: case 2: case 3:
case 4: case 5: case 6: case 7:
sprintf (regname, "ar.k%u", (unsigned int) value);
break;
case 16: strcpy (regname, "ar.rsc"); break;
case 17: strcpy (regname, "ar.bsp"); break;
case 18: strcpy (regname, "ar.bspstore"); break;
case 19: strcpy (regname, "ar.rnat"); break;
case 32: strcpy (regname, "ar.ccv"); break;
case 36: strcpy (regname, "ar.unat"); break;
case 40: strcpy (regname, "ar.fpsr"); break;
case 44: strcpy (regname, "ar.itc"); break;
case 64: strcpy (regname, "ar.pfs"); break;
case 65: strcpy (regname, "ar.lc"); break;
case 66: strcpy (regname, "ar.ec"); break;
default:
sprintf (regname, "ar%u", (unsigned int) value);
break;
}
(*info->fprintf_func) (info->stream, "%s", regname);
}
else
(*info->fprintf_func) (info->stream, "%s%d", odesc->str, (int)value);
break;
case IA64_OPND_CLASS_IND:
(*info->fprintf_func) (info->stream, "%s[r%d]", odesc->str, (int)value);
break;
case IA64_OPND_CLASS_ABS:
str = 0;
if (odesc - elf64_ia64_operands == IA64_OPND_MBTYPE4)
switch (value)
{
case 0x0: str = "@brcst"; break;
case 0x8: str = "@mix"; break;
case 0x9: str = "@shuf"; break;
case 0xa: str = "@alt"; break;
case 0xb: str = "@rev"; break;
}
if (str)
(*info->fprintf_func) (info->stream, "%s", str);
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_SIGNED)
(*info->fprintf_func) (info->stream, "%lld", value);
else if (odesc->flags & IA64_OPND_FLAG_DECIMAL_UNSIGNED)
(*info->fprintf_func) (info->stream, "%llu", value);
else
(*info->fprintf_func) (info->stream, "0x%llx", value);
break;
case IA64_OPND_CLASS_REL:
(*info->print_address_func) (memaddr + value, info);
break;
}
need_comma = 1;
if (j + 1 == idesc->num_outputs)
{
(*info->fprintf_func) (info->stream, "=");
need_comma = 0;
}
}
if (slotnum + 1 == ia64_templ_desc[template].group_boundary
|| ((slotnum == 2) && s_bit))
(*info->fprintf_func) (info->stream, ";;");
done:
ia64_free_opcode ((struct ia64_opcode *)idesc);
failed:
if (slotnum == 2)
retval += 16 - 3*slot_multiplier;
return retval;
decoding_failed:
(*info->fprintf_func) (info->stream, " data8 %#011llx", insn);
goto failed;
}

2789
contrib/binutils/opcodes/ia64-gen.c Normal file
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234
contrib/binutils/opcodes/ia64-ic.tbl Normal file
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Class; Events/Instructions
all; IC:predicatable-instructions, IC:unpredicatable-instructions
branches; IC:indirect-brs, IC:ip-rel-brs
cfm-readers; IC:fr-readers, IC:fr-writers, IC:gr-readers, IC:gr-writers, IC:mod-sched-brs, IC:predicatable-instructions, IC:pr-writers, alloc, br.call, brl.call, br.ret, cover, loadrs, rfi, IC:chk-a, invala.e
chk-a; chk.a.clr, chk.a.nc
cmpxchg; cmpxchg1, cmpxchg2, cmpxchg4, cmpxchg8
czx; czx1, czx2
fcmp-s0; fcmp[Field(sf)==s0]
fcmp-s1; fcmp[Field(sf)==s1]
fcmp-s2; fcmp[Field(sf)==s2]
fcmp-s3; fcmp[Field(sf)==s3]
fetchadd; fetchadd4, fetchadd8
fp-arith; fadd, famax, famin, fcvt.fx, fcvt.fxu, fcvt.xuf, fma, fmax, fmin, fmpy, fms, fnma, fnmpy, fnorm, fpamax, fpamin, fpcvt.fx, fpcvt.fxu, fpma, fpmax, fpmin, fpmpy, fpms, fpnma, fpnmpy, fprcpa, fprsqrta, frcpa, frsqrta, fsub
fp-arith-s0; IC:fp-arith[Field(sf)==s0]
fp-arith-s1; IC:fp-arith[Field(sf)==s1]
fp-arith-s2; IC:fp-arith[Field(sf)==s2]
fp-arith-s3; IC:fp-arith[Field(sf)==s3]
fp-non-arith; fabs, fand, fandcm, fclass, fcvt.xf, fmerge, fmix, fneg, fnegabs, for, fpabs, fpmerge, fpack, fpneg, fpnegabs, fselect, fswap, fsxt, fxor, xma
fpcmp-s0; fpcmp[Field(sf)==s0]
fpcmp-s1; fpcmp[Field(sf)==s1]
fpcmp-s2; fpcmp[Field(sf)==s2]
fpcmp-s3; fpcmp[Field(sf)==s3]
fr-readers; IC:fp-arith, IC:fp-non-arith, IC:pr-writers-fp, chk.s[Format in {M21}], getf
fr-writers; IC:fp-arith, IC:fp-non-arith\fclass, IC:mem-readers-fp, setf
gr-readers; IC:gr-readers-writers, IC:mem-readers, IC:mem-writers, chk.s, cmp, cmp4, fc, itc.i, itc.d, itr.i, itr.d, IC:mov-to-AR-gr, IC:mov-to-BR, IC:mov-to-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-to-PR-allreg, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:probe-all, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, setf, tbit, tnat
gr-readers-writers; IC:mov-from-IND, add, addl, addp4, adds, and, andcm, IC:czx, dep\dep[Format in {I13}], extr, IC:mem-readers-int, IC:ld-all-postinc, IC:lfetch-postinc, IC:mix, IC:mux, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-nofault, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, shl, shladd, shladdp4, shr, shrp, IC:st-postinc, sub, IC:sxt, tak, thash, tpa, ttag, IC:unpack, xor, IC:zxt
gr-writers; alloc, dep, getf, IC:gr-readers-writers, IC:mem-readers-int, IC:mov-from-AR, IC:mov-from-BR, IC:mov-from-CR, IC:mov-from-PR, IC:mov-from-PSR, IC:mov-from-PSR-um, IC:mov-ip, movl
indirect-brp; brp[Format in {B7}]
indirect-brs; br.call[Format in {B5}], br.cond[Format in {B4}], br.ia, br.ret
invala-all; invala[Format in {M24}], invala.e
ip-rel-brs; IC:mod-sched-brs, br.call[Format in {B3}], brl.call, brl.cond, br.cond[Format in {B1}], br.cloop
ld; ld1, ld2, ld4, ld8, ld8.fill
ld-a; ld1.a, ld2.a, ld4.a, ld8.a
ld-all-postinc; IC:ld[Format in {M2 M3}], IC:ldfp[Format in {M12}], IC:ldf[Format in {M7 M8}]
ld-c; IC:ld-c-nc, IC:ld-c-clr
ld-c-clr; ld1.c.clr, ld2.c.clr, ld4.c.clr, ld8.c.clr, IC:ld-c-clr-acq
ld-c-clr-acq; ld1.c.clr.acq, ld2.c.clr.acq, ld4.c.clr.acq, ld8.c.clr.acq
ld-c-nc; ld1.c.nc, ld2.c.nc, ld4.c.nc, ld8.c.nc
ld-s; ld1.s, ld2.s, ld4.s, ld8.s
ld-sa; ld1.sa, ld2.sa, ld4.sa, ld8.sa
ldf; ldfs, ldfd, ldfe, ldf8, ldf.fill
ldf-a; ldfs.a, ldfd.a, ldfe.a, ldf8.a
ldf-c; IC:ldf-c-nc, IC:ldf-c-clr
ldf-c-clr; ldfs.c.clr, ldfd.c.clr, ldfe.c.clr, ldf8.c.clr
ldf-c-nc; ldfs.c.nc, ldfd.c.nc, ldfe.c.nc, ldf8.c.nc
ldf-s; ldfs.s, ldfd.s, ldfe.s, ldf8.s
ldf-sa; ldfs.sa, ldfd.sa, ldfe.sa, ldf8.sa
ldfp; ldfps, ldfpd, ldfp8
ldfp-a; ldfps.a, ldfpd.a, ldfp8.a
ldfp-c; IC:ldfp-c-nc, IC:ldfp-c-clr
ldfp-c-clr; ldfps.c.clr, ldfpd.c.clr, ldfp8.c.clr
ldfp-c-nc; ldfps.c.nc, ldfpd.c.nc, ldfp8.c.nc
ldfp-s; ldfps.s, ldfpd.s, ldfp8.s
ldfp-sa; ldfps.sa, ldfpd.sa, ldfp8.sa
lfetch-all; lfetch
lfetch-fault; lfetch[Field(lftype)==fault]
lfetch-nofault; lfetch[Field(lftype)==]
lfetch-postinc; lfetch[Format in {M14 M15}]
mem-readers; IC:mem-readers-fp, IC:mem-readers-int
mem-readers-alat; IC:ld-a, IC:ldf-a, IC:ldfp-a, IC:ld-sa, IC:ldf-sa, IC:ldfp-sa, IC:ld-c, IC:ldf-c, IC:ldfp-c
mem-readers-fp; IC:ldf, IC:ldfp
mem-readers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:ld
mem-readers-spec; IC:ld-s, IC:ld-sa, IC:ldf-s, IC:ldf-sa, IC:ldfp-s, IC:ldfp-sa
mem-writers; IC:mem-writers-fp, IC:mem-writers-int
mem-writers-fp; IC:stf
mem-writers-int; IC:cmpxchg, IC:fetchadd, IC:xchg, IC:st
mix; mix1, mix2, mix4
mod-sched-brs; br.cexit, br.ctop, br.wexit, br.wtop
mod-sched-brs-counted; br.cexit, br.cloop, br.ctop
mov-from-AR; IC:mov-from-AR-M, IC:mov-from-AR-I, IC:mov-from-AR-IM
mov-from-AR-BSP; IC:mov-from-AR-M[Field(ar3) == BSP]
mov-from-AR-BSPSTORE; IC:mov-from-AR-M[Field(ar3) == BSPSTORE]
mov-from-AR-CCV; IC:mov-from-AR-M[Field(ar3) == CCV]
mov-from-AR-EC; IC:mov-from-AR-I[Field(ar3) == EC]
mov-from-AR-FPSR; IC:mov-from-AR-M[Field(ar3) == FPSR]
mov-from-AR-I; mov_ar[Format in {I28}]
mov-from-AR-ig; IC:mov-from-AR-IM[Field(ar3) in {48-63 112-127}]
mov-from-AR-IM; mov_ar[Format in {I28 M31}]
mov-from-AR-ITC; IC:mov-from-AR-M[Field(ar3) == ITC]
mov-from-AR-K; IC:mov-from-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
mov-from-AR-LC; IC:mov-from-AR-I[Field(ar3) == LC]
mov-from-AR-M; mov_ar[Format in {M31}]
mov-from-AR-PFS; IC:mov-from-AR-I[Field(ar3) == PFS]
mov-from-AR-RNAT; IC:mov-from-AR-M[Field(ar3) == RNAT]
mov-from-AR-RSC; IC:mov-from-AR-M[Field(ar3) == RSC]
mov-from-AR-rv; IC:none
mov-from-AR-UNAT; IC:mov-from-AR-M[Field(ar3) == UNAT]
mov-from-BR; mov_br[Format in {I22}]
mov-from-CR; mov_cr[Format in {M33}]
mov-from-CR-CMCV; IC:mov-from-CR[Field(cr3) == CMCV]
mov-from-CR-DCR; IC:mov-from-CR[Field(cr3) == DCR]
mov-from-CR-EOI; IC:mov-from-CR[Field(cr3) == EOI]
mov-from-CR-GPTA; IC:mov-from-CR[Field(cr3) == GPTA]
mov-from-CR-IFA; IC:mov-from-CR[Field(cr3) == IFA]
mov-from-CR-IFS; IC:mov-from-CR[Field(cr3) == IFS]
mov-from-CR-IHA; IC:mov-from-CR[Field(cr3) == IHA]
mov-from-CR-IIM; IC:mov-from-CR[Field(cr3) == IIM]
mov-from-CR-IIP; IC:mov-from-CR[Field(cr3) == IIP]
mov-from-CR-IIPA; IC:mov-from-CR[Field(cr3) == IIPA]
mov-from-CR-IPSR; IC:mov-from-CR[Field(cr3) == IPSR]
mov-from-CR-IRR; IC:mov-from-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
mov-from-CR-ISR; IC:mov-from-CR[Field(cr3) == ISR]
mov-from-CR-ITIR; IC:mov-from-CR[Field(cr3) == ITIR]
mov-from-CR-ITM; IC:mov-from-CR[Field(cr3) == ITM]
mov-from-CR-ITV; IC:mov-from-CR[Field(cr3) == ITV]
mov-from-CR-IVA; IC:mov-from-CR[Field(cr3) == IVA]
mov-from-CR-IVR; IC:mov-from-CR[Field(cr3) == IVR]
mov-from-CR-LID; IC:mov-from-CR[Field(cr3) == LID]
mov-from-CR-LRR; IC:mov-from-CR[Field(cr3) in {LRR0 LRR1}]
mov-from-CR-PMV; IC:mov-from-CR[Field(cr3) == PMV]
mov-from-CR-PTA; IC:mov-from-CR[Field(cr3) == PTA]
mov-from-CR-rv; IC:none
mov-from-CR-TPR; IC:mov-from-CR[Field(cr3) == TPR]
mov-from-IND; mov_indirect[Format in {M43}]
mov-from-IND-CPUID; IC:mov-from-IND[Field(ireg) == cpuid]
mov-from-IND-DBR; IC:mov-from-IND[Field(ireg) == dbr]
mov-from-IND-IBR; IC:mov-from-IND[Field(ireg) == ibr]
mov-from-IND-MSR; IC:mov-from-IND[Field(ireg) == msr]
mov-from-IND-PKR; IC:mov-from-IND[Field(ireg) == pkr]
mov-from-IND-PMC; IC:mov-from-IND[Field(ireg) == pmc]
mov-from-IND-PMD; IC:mov-from-IND[Field(ireg) == pmd]
mov-from-IND-priv; IC:mov-from-IND[Field(ireg) in {dbr ibr msr pkr pmc rr}]
mov-from-IND-RR; IC:mov-from-IND[Field(ireg) == rr]
mov-from-PR; mov_pr[Format in {I25}]
mov-from-PSR; mov_psr[Format in {M36}]
mov-from-PSR-um; mov_um[Format in {M36}]
mov-ip; mov_ip[Format in {I25}]
mov-to-AR; IC:mov-to-AR-M, IC:mov-to-AR-I
mov-to-AR-BSP; IC:mov-to-AR-M[Field(ar3) == BSP]
mov-to-AR-BSPSTORE; IC:mov-to-AR-M[Field(ar3) == BSPSTORE]
mov-to-AR-CCV; IC:mov-to-AR-M[Field(ar3) == CCV]
mov-to-AR-EC; IC:mov-to-AR-I[Field(ar3) == EC]
mov-to-AR-FPSR; IC:mov-to-AR-M[Field(ar3) == FPSR]
mov-to-AR-gr; IC:mov-to-AR-M[Format in {M29}], IC:mov-to-AR-I[Format in {I26}]
mov-to-AR-I; mov_ar[Format in {I26 I27}]
mov-to-AR-ig; IC:mov-to-AR-IM[Field(ar3) in {48-63 112-127}]
mov-to-AR-IM; mov_ar[Format in {I26 I27 M29 M30}]
mov-to-AR-ITC; IC:mov-to-AR-M[Field(ar3) == ITC]
mov-to-AR-K; IC:mov-to-AR-M[Field(ar3) in {K0 K1 K2 K3 K4 K5 K6 K7}]
mov-to-AR-LC; IC:mov-to-AR-I[Field(ar3) == LC]
mov-to-AR-M; mov_ar[Format in {M29 M30}]
mov-to-AR-PFS; IC:mov-to-AR-I[Field(ar3) == PFS]
mov-to-AR-RNAT; IC:mov-to-AR-M[Field(ar3) == RNAT]
mov-to-AR-RSC; IC:mov-to-AR-M[Field(ar3) == RSC]
mov-to-AR-UNAT; IC:mov-to-AR-M[Field(ar3) == UNAT]
mov-to-BR; mov_br[Format in {I21}]
mov-to-CR; mov_cr[Format in {M32}]
mov-to-CR-CMCV; IC:mov-to-CR[Field(cr3) == CMCV]
mov-to-CR-DCR; IC:mov-to-CR[Field(cr3) == DCR]
mov-to-CR-EOI; IC:mov-to-CR[Field(cr3) == EOI]
mov-to-CR-GPTA; IC:mov-to-CR[Field(cr3) == GPTA]
mov-to-CR-IFA; IC:mov-to-CR[Field(cr3) == IFA]
mov-to-CR-IFS; IC:mov-to-CR[Field(cr3) == IFS]
mov-to-CR-IHA; IC:mov-to-CR[Field(cr3) == IHA]
mov-to-CR-IIM; IC:mov-to-CR[Field(cr3) == IIM]
mov-to-CR-IIP; IC:mov-to-CR[Field(cr3) == IIP]
mov-to-CR-IIPA; IC:mov-to-CR[Field(cr3) == IIPA]
mov-to-CR-IPSR; IC:mov-to-CR[Field(cr3) == IPSR]
mov-to-CR-IRR; IC:mov-to-CR[Field(cr3) in {IRR0 IRR1 IRR2 IRR3}]
mov-to-CR-ISR; IC:mov-to-CR[Field(cr3) == ISR]
mov-to-CR-ITIR; IC:mov-to-CR[Field(cr3) == ITIR]
mov-to-CR-ITM; IC:mov-to-CR[Field(cr3) == ITM]
mov-to-CR-ITV; IC:mov-to-CR[Field(cr3) == ITV]
mov-to-CR-IVA; IC:mov-to-CR[Field(cr3) == IVA]
mov-to-CR-IVR; IC:mov-to-CR[Field(cr3) == IVR]
mov-to-CR-LID; IC:mov-to-CR[Field(cr3) == LID]
mov-to-CR-LRR; IC:mov-to-CR[Field(cr3) in {LRR0 LRR1}]
mov-to-CR-PMV; IC:mov-to-CR[Field(cr3) == PMV]
mov-to-CR-PTA; IC:mov-to-CR[Field(cr3) == PTA]
mov-to-CR-TPR; IC:mov-to-CR[Field(cr3) == TPR]
mov-to-IND; mov_indirect[Format in {M42}]
mov-to-IND-CPUID; IC:mov-to-IND[Field(ireg) == cpuid]
mov-to-IND-DBR; IC:mov-to-IND[Field(ireg) == dbr]
mov-to-IND-IBR; IC:mov-to-IND[Field(ireg) == ibr]
mov-to-IND-MSR; IC:mov-to-IND[Field(ireg) == msr]
mov-to-IND-PKR; IC:mov-to-IND[Field(ireg) == pkr]
mov-to-IND-PMC; IC:mov-to-IND[Field(ireg) == pmc]
mov-to-IND-PMD; IC:mov-to-IND[Field(ireg) == pmd]
mov-to-IND-priv; IC:mov-to-IND
mov-to-IND-RR; IC:mov-to-IND[Field(ireg) == rr]
mov-to-PR; IC:mov-to-PR-allreg, IC:mov-to-PR-rotreg
mov-to-PR-allreg; mov_pr[Format in {I23}]
mov-to-PR-rotreg; mov_pr[Format in {I24}]
mov-to-PSR-l; mov_psr[Format in {M35}]
mov-to-PSR-um; mov_um[Format in {M35}]
mux; mux1, mux2
none; -
pack; pack2, pack4
padd; padd1, padd2, padd4
pavg; pavg1, pavg2
pavgsub; pavgsub1, pavgsub2
pcmp; pcmp1, pcmp2, pcmp4
pmax; pmax1, pmax2
pmin; pmin1, pmin2
pmpy; pmpy2
pmpyshr; pmpyshr2
pr-and-writers; IC:pr-gen-writers-int[Field(ctype) in {and andcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
pr-gen-writers-fp; fclass, fcmp
pr-gen-writers-int; cmp, cmp4, tbit, tnat
pr-norm-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==]
pr-norm-writers-int; IC:pr-gen-writers-int[Field(ctype)==]
pr-or-writers; IC:pr-gen-writers-int[Field(ctype) in {or orcm}], IC:pr-gen-writers-int[Field(ctype) in {or.andcm and.orcm}]
pr-readers-br; br.call, br.cond, brl.call, brl.cond, br.ret, br.wexit, br.wtop, break.b, nop.b, IC:ReservedBQP
pr-readers-nobr-nomovpr; add, addl, addp4, adds, and, andcm, break.f, break.i, break.m, break.x, chk.s, IC:chk-a, cmp, cmp4, IC:cmpxchg, IC:czx, dep, extr, IC:fp-arith, IC:fp-non-arith, fc, fchkf, fclrf, fcmp, IC:fetchadd, fpcmp, fsetc, fwb, getf, IC:invala-all, itc.i, itc.d, itr.i, itr.d, IC:ld, IC:ldf, IC:ldfp, IC:lfetch-all, mf, IC:mix, IC:mov-from-AR-M, IC:mov-from-AR-IM, IC:mov-from-AR-I, IC:mov-to-AR-M, IC:mov-to-AR-I, IC:mov-to-AR-IM, IC:mov-to-BR, IC:mov-from-BR, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-IND, IC:mov-from-IND, IC:mov-ip, IC:mov-to-PSR-l, IC:mov-to-PSR-um, IC:mov-from-PSR, IC:mov-from-PSR-um, movl, IC:mux, nop.f, nop.i, nop.m, nop.x, or, IC:pack, IC:padd, IC:pavg, IC:pavgsub, IC:pcmp, IC:pmax, IC:pmin, IC:pmpy, IC:pmpyshr, popcnt, IC:probe-all, IC:psad, IC:pshl, IC:pshladd, IC:pshr, IC:pshradd, IC:psub, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.d, ptr.i, IC:ReservedQP, rsm, setf, shl, shladd, shladdp4, shr, shrp, srlz.i, srlz.d, ssm, IC:st, IC:stf, sub, sum, IC:sxt, sync, tak, tbit, thash, tnat, tpa, ttag, IC:unpack, IC:xchg, xma, xmpy, xor, IC:zxt
pr-unc-writers-fp; IC:pr-gen-writers-fp[Field(ctype)==unc]+11, fprcpa+11, fprsqrta+11, frcpa+11, frsqrta+11
pr-unc-writers-int; IC:pr-gen-writers-int[Field(ctype)==unc]+11
pr-writers; IC:pr-writers-int, IC:pr-writers-fp
pr-writers-fp; IC:pr-norm-writers-fp, IC:pr-unc-writers-fp
pr-writers-int; IC:pr-norm-writers-int, IC:pr-unc-writers-int, IC:pr-and-writers, IC:pr-or-writers
predicatable-instructions; IC:mov-from-PR, IC:mov-to-PR, IC:pr-readers-br, IC:pr-readers-nobr-nomovpr
priv-ops; IC:mov-to-IND-priv, bsw, itc.i, itc.d, itr.i, itr.d, IC:mov-to-CR, IC:mov-from-CR, IC:mov-to-PSR-l, IC:mov-from-PSR, IC:mov-from-IND-priv, ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, rfi, rsm, ssm, tak, tpa
probe-all; IC:probe-fault, IC:probe-nofault
probe-fault; probe[Format in {M40}]
probe-nofault; probe[Format in {M38 M39}]
psad; psad1
pshl; pshl2, pshl4
pshladd; pshladd2
pshr; pshr2, pshr4
pshradd; pshradd2
psub; psub1, psub2, psub4
ReservedBQP; -+15
ReservedQP; -+16
rse-readers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-from-AR-BSP, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-BSPSTORE, IC:mov-from-AR-RNAT, IC:mov-to-AR-RNAT, rfi
rse-writers; alloc, br.call, br.ia, br.ret, brl.call, cover, flushrs, loadrs, IC:mov-to-AR-BSPSTORE, rfi
st; st1, st2, st4, st8, st8.spill
st-postinc; IC:stf[Format in {M10}], IC:st[Format in {M5}]
stf; stfs, stfd, stfe, stf8, stf.spill
sxt; sxt1, sxt2, sxt4
sys-mask-writers-partial; rsm, ssm
unpack; unpack1, unpack2, unpack4
unpredicatable-instructions; alloc, br.cloop, br.ctop, br.cexit, br.ia, brp, bsw, clrrrb, cover, epc, flushrs, loadrs, rfi
user-mask-writers-partial; rum, sum
xchg; xchg1, xchg2, xchg4, xchg8
zxt; zxt1, zxt2, zxt4

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/* ia64-opc-a.c -- IA-64 `A' opcode table.
Copyright 1998, 1999, 2000, 2001 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
#define A IA64_TYPE_A, 1
#define A2 IA64_TYPE_A, 2
/* instruction bit fields: */
#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bImm14(x) ((((ia64_insn) (((x) >> 0) & 0x7f)) << 13) | \
(((ia64_insn) (((x) >> 7) & 0x3f)) << 27) | \
(((ia64_insn) (((x) >> 13) & 0x01)) << 36))
#define bR3a(x) (((ia64_insn) ((x) & 0x7f)) << 20)
#define bR3b(x) (((ia64_insn) ((x) & 0x3)) << 20)
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 27)
#define bX4(x) (((ia64_insn) ((x) & 0xf)) << 29)
#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
/* instruction bit masks: */
#define mC bC (-1)
#define mImm14 bImm14 (-1)
#define mR3a bR3a (-1)
#define mR3b bR3b (-1)
#define mTa bTa (-1)
#define mTb bTb (-1)
#define mVe bVe (-1)
#define mX bX (-1)
#define mX2 bX2 (-1)
#define mX2a bX2a (-1)
#define mX2b bX2b (-1)
#define mX4 bX4 (-1)
#define mZa bZa (-1)
#define mZb bZb (-1)
#define OpR3b(a,b) (bOp (a) | bR3b (b)), (mOp | mR3b)
#define OpX2aVe(a,b,c) (bOp (a) | bX2a (b) | bVe (c)), \
(mOp | mX2a | mVe)
#define OpX2aVeR3a(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bR3a (d)), \
(mOp | mX2a | mVe | mR3a)
#define OpX2aVeImm14(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bImm14 (d)), \
(mOp | mX2a | mVe | mImm14)
#define OpX2aVeX4(a,b,c,d) (bOp (a) | bX2a (b) | bVe (c) | bX4 (d)), \
(mOp | mX2a | mVe | mX4)
#define OpX2aVeX4X2b(a,b,c,d,e) \
(bOp (a) | bX2a (b) | bVe (c) | bX4 (d) | bX2b (e)), \
(mOp | mX2a | mVe | mX4 | mX2b)
#define OpX2TbTaC(a,b,c,d,e) \
(bOp (a) | bX2 (b) | bTb (c) | bTa (d) | bC (e)), \
(mOp | mX2 | mTb | mTa | mC)
#define OpX2TaC(a,b,c,d) (bOp (a) | bX2 (b) | bTa (c) | bC (d)), \
(mOp | mX2 | mTa | mC)
#define OpX2aZaZbX4(a,b,c,d,e) \
(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e)), \
(mOp | mX2a | mZa | mZb | mX4)
#define OpX2aZaZbX4X2b(a,b,c,d,e,f) \
(bOp (a) | bX2a (b) | bZa (c) | bZb (d) | bX4 (e) | bX2b (f)), \
(mOp | mX2a | mZa | mZb | mX4 | mX2b)
struct ia64_opcode ia64_opcodes_a[] =
{
/* A-type instruction encodings (sorted according to major opcode) */
{"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 0), {R1, R2, R3}},
{"add", A, OpX2aVeX4X2b (8, 0, 0, 0, 1), {R1, R2, R3, C1}},
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 1), {R1, R2, R3}},
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 1, 0), {R1, R2, R3, C1}},
{"addp4", A, OpX2aVeX4X2b (8, 0, 0, 2, 0), {R1, R2, R3}},
{"and", A, OpX2aVeX4X2b (8, 0, 0, 3, 0), {R1, R2, R3}},
{"andcm", A, OpX2aVeX4X2b (8, 0, 0, 3, 1), {R1, R2, R3}},
{"or", A, OpX2aVeX4X2b (8, 0, 0, 3, 2), {R1, R2, R3}},
{"xor", A, OpX2aVeX4X2b (8, 0, 0, 3, 3), {R1, R2, R3}},
{"shladd", A, OpX2aVeX4 (8, 0, 0, 4), {R1, R2, CNT2a, R3}},
{"shladdp4", A, OpX2aVeX4 (8, 0, 0, 6), {R1, R2, CNT2a, R3}},
{"sub", A, OpX2aVeX4X2b (8, 0, 0, 9, 1), {R1, IMM8, R3}},
{"and", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 0), {R1, IMM8, R3}},
{"andcm", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 1), {R1, IMM8, R3}},
{"or", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 2), {R1, IMM8, R3}},
{"xor", A, OpX2aVeX4X2b (8, 0, 0, 0xb, 3), {R1, IMM8, R3}},
{"mov", A, OpX2aVeImm14 (8, 2, 0, 0), {R1, R3}},
{"mov", A, OpX2aVeR3a (8, 2, 0, 0), {R1, IMM14}, PSEUDO},
{"adds", A, OpX2aVe (8, 2, 0), {R1, IMM14, R3}},
{"addp4", A, OpX2aVe (8, 3, 0), {R1, IMM14, R3}},
{"padd1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 0), {R1, R2, R3}},
{"padd2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 0), {R1, R2, R3}},
{"padd4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 0, 0), {R1, R2, R3}},
{"padd1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 1), {R1, R2, R3}},
{"padd2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 1), {R1, R2, R3}},
{"padd1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 2), {R1, R2, R3}},
{"padd2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 2), {R1, R2, R3}},
{"padd1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 0, 3), {R1, R2, R3}},
{"padd2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 0, 3), {R1, R2, R3}},
{"psub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 0), {R1, R2, R3}},
{"psub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 0), {R1, R2, R3}},
{"psub4", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 1, 0), {R1, R2, R3}},
{"psub1.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 1), {R1, R2, R3}},
{"psub2.sss", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 1), {R1, R2, R3}},
{"psub1.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 2), {R1, R2, R3}},
{"psub2.uuu", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 2), {R1, R2, R3}},
{"psub1.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 1, 3), {R1, R2, R3}},
{"psub2.uus", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 1, 3), {R1, R2, R3}},
{"pavg1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 2), {R1, R2, R3}},
{"pavg2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 2), {R1, R2, R3}},
{"pavg1.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 2, 3), {R1, R2, R3}},
{"pavg2.raz", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 2, 3), {R1, R2, R3}},
{"pavgsub1", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 3, 2), {R1, R2, R3}},
{"pavgsub2", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 3, 2), {R1, R2, R3}},
{"pcmp1.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 0), {R1, R2, R3}},
{"pcmp2.eq", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 0), {R1, R2, R3}},
{"pcmp4.eq", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 0), {R1, R2, R3}},
{"pcmp1.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 0, 9, 1), {R1, R2, R3}},
{"pcmp2.gt", A, OpX2aZaZbX4X2b (8, 1, 0, 1, 9, 1), {R1, R2, R3}},
{"pcmp4.gt", A, OpX2aZaZbX4X2b (8, 1, 1, 0, 9, 1), {R1, R2, R3}},
{"pshladd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 4), {R1, R2, CNT2b, R3}},
{"pshradd2", A, OpX2aZaZbX4 (8, 1, 0, 1, 6), {R1, R2, CNT2b, R3}},
{"mov", A, OpR3b (9, 0), {R1, IMM22}, PSEUDO},
{"addl", A, Op (9), {R1, IMM22, R3_2}},
{"cmp.lt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp.le", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp.gt", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp.ge", A2, OpX2TbTaC (0xc, 0, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp.lt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp.le.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp.gt.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp.ge.unc", A2, OpX2TbTaC (0xc, 0, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp.eq.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp.ne.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp.ne.and", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp.eq.andcm", A2, OpX2TbTaC (0xc, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.lt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp4.le", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp4.gt", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp4.ge", A2, OpX2TbTaC (0xc, 1, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp4.lt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp4.le.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp4.gt.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp4.ge.unc", A2, OpX2TbTaC (0xc, 1, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp4.eq.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp4.ne.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.ne.and", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp4.eq.andcm", A2, OpX2TbTaC (0xc, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.ge.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp.le.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.lt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.gt.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.lt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp.gt.and", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.ge.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.le.andcm", A2, OpX2TbTaC (0xc, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.ge.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp4.le.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.lt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.gt.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.lt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp4.gt.and", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.ge.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.le.andcm", A2, OpX2TbTaC (0xc, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.lt", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8, R3}},
{"cmp.le", A2, OpX2TaC (0xc, 2, 0, 0), {P1, P2, IMM8M1, R3}},
{"cmp.gt", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8M1, R3}},
{"cmp.ge", A2, OpX2TaC (0xc, 2, 0, 0), {P2, P1, IMM8, R3}},
{"cmp.lt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8, R3}},
{"cmp.le.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P1, P2, IMM8M1, R3}},
{"cmp.gt.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8M1, R3}},
{"cmp.ge.unc", A2, OpX2TaC (0xc, 2, 0, 1), {P2, P1, IMM8, R3}},
{"cmp.eq.and", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}},
{"cmp.ne.andcm", A2, OpX2TaC (0xc, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.ne.and", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}},
{"cmp.eq.andcm", A2, OpX2TaC (0xc, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.lt", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8, R3}},
{"cmp4.le", A2, OpX2TaC (0xc, 3, 0, 0), {P1, P2, IMM8M1, R3}},
{"cmp4.gt", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8M1, R3}},
{"cmp4.ge", A2, OpX2TaC (0xc, 3, 0, 0), {P2, P1, IMM8, R3}},
{"cmp4.lt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8, R3}},
{"cmp4.le.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P1, P2, IMM8M1, R3}},
{"cmp4.gt.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8M1, R3}},
{"cmp4.ge.unc", A2, OpX2TaC (0xc, 3, 0, 1), {P2, P1, IMM8, R3}},
{"cmp4.eq.and", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne.andcm", A2, OpX2TaC (0xc, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.ne.and", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}},
{"cmp4.eq.andcm", A2, OpX2TaC (0xc, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.ltu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp.leu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp.gtu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp.geu", A2, OpX2TbTaC (0xd, 0, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp.ltu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp.leu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp.gtu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp.geu.unc", A2, OpX2TbTaC (0xd, 0, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp.eq.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp.ne.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp.ne.or", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp.eq.orcm", A2, OpX2TbTaC (0xd, 0, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.ltu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp4.leu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R3, R2}},
{"cmp4.gtu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P1, P2, R3, R2}},
{"cmp4.geu", A2, OpX2TbTaC (0xd, 1, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp4.ltu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp4.leu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R3, R2}},
{"cmp4.gtu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P1, P2, R3, R2}},
{"cmp4.geu.unc", A2, OpX2TbTaC (0xd, 1, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp4.eq.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp4.ne.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 0), {P1, P2, R2, R3}, PSEUDO},
{"cmp4.ne.or", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp4.eq.orcm", A2, OpX2TbTaC (0xd, 1, 0, 1, 1), {P1, P2, R2, R3}, PSEUDO},
{"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.ge.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp.le.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.lt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.gt.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.lt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp.gt.or", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.ge.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp.le.orcm", A2, OpX2TbTaC (0xd, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.ge.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp4.le.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.lt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.gt.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.lt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp4.gt.or", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.ge.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, GR0, R3}, PSEUDO},
{"cmp4.le.orcm", A2, OpX2TbTaC (0xd, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.ltu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8, R3}},
{"cmp.leu", A2, OpX2TaC (0xd, 2, 0, 0), {P1, P2, IMM8M1U8, R3}},
{"cmp.gtu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8M1U8, R3}},
{"cmp.geu", A2, OpX2TaC (0xd, 2, 0, 0), {P2, P1, IMM8, R3}},
{"cmp.ltu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8, R3}},
{"cmp.leu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P1, P2, IMM8M1U8, R3}},
{"cmp.gtu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8M1U8, R3}},
{"cmp.geu.unc", A2, OpX2TaC (0xd, 2, 0, 1), {P2, P1, IMM8, R3}},
{"cmp.eq.or", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}},
{"cmp.ne.orcm", A2, OpX2TaC (0xd, 2, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.ne.or", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}},
{"cmp.eq.orcm", A2, OpX2TaC (0xd, 2, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.ltu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8U4, R3}},
{"cmp4.leu", A2, OpX2TaC (0xd, 3, 0, 0), {P1, P2, IMM8M1U4, R3}},
{"cmp4.gtu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8M1U4, R3}},
{"cmp4.geu", A2, OpX2TaC (0xd, 3, 0, 0), {P2, P1, IMM8U4, R3}},
{"cmp4.ltu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8U4, R3}},
{"cmp4.leu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P1, P2, IMM8M1U4, R3}},
{"cmp4.gtu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8M1U4, R3}},
{"cmp4.geu.unc", A2, OpX2TaC (0xd, 3, 0, 1), {P2, P1, IMM8U4, R3}},
{"cmp4.eq.or", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne.orcm", A2, OpX2TaC (0xd, 3, 1, 0), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp4.ne.or", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}},
{"cmp4.eq.orcm", A2, OpX2TaC (0xd, 3, 1, 1), {P1, P2, IMM8, R3}, PSEUDO},
{"cmp.eq", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp.ne", A2, OpX2TbTaC (0xe, 0, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp.eq.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp.ne.unc", A2, OpX2TbTaC (0xe, 0, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp.eq.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp.ne.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
{"cmp.ne.or.andcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp.eq.and.orcm", A2, OpX2TbTaC (0xe, 0, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
{"cmp4.eq", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P1, P2, R2, R3}},
{"cmp4.ne", A2, OpX2TbTaC (0xe, 1, 0, 0, 0), {P2, P1, R2, R3}},
{"cmp4.eq.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P1, P2, R2, R3}},
{"cmp4.ne.unc", A2, OpX2TbTaC (0xe, 1, 0, 0, 1), {P2, P1, R2, R3}},
{"cmp4.eq.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P1, P2, R2, R3}},
{"cmp4.ne.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 0), {P2, P1, R2, R3}, PSEUDO},
{"cmp4.ne.or.andcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P1, P2, R2, R3}},
{"cmp4.eq.and.orcm", A2, OpX2TbTaC (0xe, 1, 0, 1, 1), {P2, P1, R2, R3}, PSEUDO},
{"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO},
{"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO},
{"cmp.ge.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp.le.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.lt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.gt.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO},
{"cmp.lt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp.gt.or.andcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp.ge.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp.le.and.orcm", A2, OpX2TbTaC (0xe, 0, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO},
{"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, GR0, R3}},
{"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 0), {P2, P1, R3, GR0}, PSEUDO},
{"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, GR0, R3}},
{"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 0, 1), {P2, P1, R3, GR0}, PSEUDO},
{"cmp4.ge.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, GR0, R3}},
{"cmp4.le.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.lt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.gt.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 0), {P2, P1, R3, GR0}, PSEUDO},
{"cmp4.lt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, GR0, R3}},
{"cmp4.gt.or.andcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P1, P2, R3, GR0}, PSEUDO},
{"cmp4.ge.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, GR0, R3}, PSEUDO},
{"cmp4.le.and.orcm", A2, OpX2TbTaC (0xe, 1, 1, 1, 1), {P2, P1, R3, GR0}, PSEUDO},
{"cmp.eq", A2, OpX2TaC (0xe, 2, 0, 0), {P1, P2, IMM8, R3}},
{"cmp.ne", A2, OpX2TaC (0xe, 2, 0, 0), {P2, P1, IMM8, R3}},
{"cmp.eq.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P1, P2, IMM8, R3}},
{"cmp.ne.unc", A2, OpX2TaC (0xe, 2, 0, 1), {P2, P1, IMM8, R3}},
{"cmp.eq.or.andcm", A2, OpX2TaC (0xe, 2, 1, 0), {P1, P2, IMM8, R3}},
{"cmp.ne.and.orcm", A2, OpX2TaC (0xe, 2, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
{"cmp.ne.or.andcm", A2, OpX2TaC (0xe, 2, 1, 1), {P1, P2, IMM8, R3}},
{"cmp.eq.and.orcm", A2, OpX2TaC (0xe, 2, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
{"cmp4.eq", A2, OpX2TaC (0xe, 3, 0, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne", A2, OpX2TaC (0xe, 3, 0, 0), {P2, P1, IMM8, R3}},
{"cmp4.eq.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P1, P2, IMM8, R3}},
{"cmp4.ne.unc", A2, OpX2TaC (0xe, 3, 0, 1), {P2, P1, IMM8, R3}},
{"cmp4.eq.or.andcm", A2, OpX2TaC (0xe, 3, 1, 0), {P1, P2, IMM8, R3}},
{"cmp4.ne.and.orcm", A2, OpX2TaC (0xe, 3, 1, 0), {P2, P1, IMM8, R3}, PSEUDO},
{"cmp4.ne.or.andcm", A2, OpX2TaC (0xe, 3, 1, 1), {P1, P2, IMM8, R3}},
{"cmp4.eq.and.orcm", A2, OpX2TaC (0xe, 3, 1, 1), {P2, P1, IMM8, R3}, PSEUDO},
{0}
};
#undef A
#undef A2
#undef bC
#undef bImm14
#undef bR3a
#undef bR3b
#undef bTa
#undef bTb
#undef bVe
#undef bX
#undef bX2
#undef bX2a
#undef bX2b
#undef bX4
#undef bZa
#undef bZb
#undef mC
#undef mImm14
#undef mR3a
#undef mR3b
#undef mTa
#undef mTb
#undef mVe
#undef mX
#undef mX2
#undef mX2a
#undef mX2b
#undef mX4
#undef mZa
#undef mZb
#undef OpR3a
#undef OpR3b
#undef OpX2aVe
#undef OpX2aVeImm14
#undef OpX2aVeX4
#undef OpX2aVeX4X2b
#undef OpX2TbTaC
#undef OpX2TaC
#undef OpX2aZaZbX4
#undef OpX2aZaZbX4X2b

489
contrib/binutils/opcodes/ia64-opc-b.c Normal file
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@ -0,0 +1,489 @@
/* ia64-opc-b.c -- IA-64 `B' opcode table.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
#define B0 IA64_TYPE_B, 0
#define B IA64_TYPE_B, 1
/* instruction bit fields: */
#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 35)
#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
#define bWhb(x) (((ia64_insn) ((x) & 0x3)) << 3)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define mBtype bBtype (-1)
#define mD bD (-1)
#define mIh bIh (-1)
#define mPa bPa (-1)
#define mPr bPr (-1)
#define mWha bWha (-1)
#define mWhb bWhb (-1)
#define mX6 bX6 (-1)
#define OpX6(a,b) (bOp (a) | bX6 (b)), (mOp | mX6)
#define OpPaWhaD(a,b,c,d) \
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
#define OpBtypePaWhaD(a,b,c,d,e) \
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
(mOp | mBtype | mPa | mWha | mD)
#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
(mOp | mBtype | mPa | mWha | mD | mPr)
#define OpX6BtypePaWhaD(a,b,c,d,e,f) \
(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f)), \
(mOp | mX6 | mBtype | mPa | mWha | mD)
#define OpX6BtypePaWhaDPr(a,b,c,d,e,f,g) \
(bOp (a) | bX6 (b) | bBtype (c) | bPa (d) | bWha (e) | bD (f) | bPr (g)), \
(mOp | mX6 | mBtype | mPa | mWha | mD | mPr)
#define OpIhWhb(a,b,c) \
(bOp (a) | bIh (b) | bWhb (c)), \
(mOp | mIh | mWhb)
#define OpX6IhWhb(a,b,c,d) \
(bOp (a) | bX6 (b) | bIh (c) | bWhb (d)), \
(mOp | mX6 | mIh | mWhb)
struct ia64_opcode ia64_opcodes_b[] =
{
/* B-type instruction encodings (sorted according to major opcode) */
#define BR(a,b) \
B0, OpX6BtypePaWhaDPr (0, 0x20, 0, a, 0, b, 0), {B2}, PSEUDO
{"br.few", BR (0, 0)},
{"br", BR (0, 0)},
{"br.few.clr", BR (0, 1)},
{"br.clr", BR (0, 1)},
{"br.many", BR (1, 0)},
{"br.many.clr", BR (1, 1)},
#undef BR
#define BR(a,b,c,d,e) B0, OpX6BtypePaWhaD (0, a, b, c, d, e), {B2}
{"br.cond.sptk.few", BR (0x20, 0, 0, 0, 0)},
{"br.cond.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO},
{"br.cond.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
{"br.cond.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO},
{"br.cond.spnt.few", BR (0x20, 0, 0, 1, 0)},
{"br.cond.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO},
{"br.cond.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
{"br.cond.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO},
{"br.cond.dptk.few", BR (0x20, 0, 0, 2, 0)},
{"br.cond.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO},
{"br.cond.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
{"br.cond.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO},
{"br.cond.dpnt.few", BR (0x20, 0, 0, 3, 0)},
{"br.cond.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO},
{"br.cond.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
{"br.cond.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO},
{"br.cond.sptk.many", BR (0x20, 0, 1, 0, 0)},
{"br.cond.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
{"br.cond.spnt.many", BR (0x20, 0, 1, 1, 0)},
{"br.cond.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
{"br.cond.dptk.many", BR (0x20, 0, 1, 2, 0)},
{"br.cond.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
{"br.cond.dpnt.many", BR (0x20, 0, 1, 3, 0)},
{"br.cond.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
{"br.sptk.few", BR (0x20, 0, 0, 0, 0)},
{"br.sptk", BR (0x20, 0, 0, 0, 0), PSEUDO},
{"br.sptk.few.clr", BR (0x20, 0, 0, 0, 1)},
{"br.sptk.clr", BR (0x20, 0, 0, 0, 1), PSEUDO},
{"br.spnt.few", BR (0x20, 0, 0, 1, 0)},
{"br.spnt", BR (0x20, 0, 0, 1, 0), PSEUDO},
{"br.spnt.few.clr", BR (0x20, 0, 0, 1, 1)},
{"br.spnt.clr", BR (0x20, 0, 0, 1, 1), PSEUDO},
{"br.dptk.few", BR (0x20, 0, 0, 2, 0)},
{"br.dptk", BR (0x20, 0, 0, 2, 0), PSEUDO},
{"br.dptk.few.clr", BR (0x20, 0, 0, 2, 1)},
{"br.dptk.clr", BR (0x20, 0, 0, 2, 1), PSEUDO},
{"br.dpnt.few", BR (0x20, 0, 0, 3, 0)},
{"br.dpnt", BR (0x20, 0, 0, 3, 0), PSEUDO},
{"br.dpnt.few.clr", BR (0x20, 0, 0, 3, 1)},
{"br.dpnt.clr", BR (0x20, 0, 0, 3, 1), PSEUDO},
{"br.sptk.many", BR (0x20, 0, 1, 0, 0)},
{"br.sptk.many.clr", BR (0x20, 0, 1, 0, 1)},
{"br.spnt.many", BR (0x20, 0, 1, 1, 0)},
{"br.spnt.many.clr", BR (0x20, 0, 1, 1, 1)},
{"br.dptk.many", BR (0x20, 0, 1, 2, 0)},
{"br.dptk.many.clr", BR (0x20, 0, 1, 2, 1)},
{"br.dpnt.many", BR (0x20, 0, 1, 3, 0)},
{"br.dpnt.many.clr", BR (0x20, 0, 1, 3, 1)},
{"br.ia.sptk.few", BR (0x20, 1, 0, 0, 0)},
{"br.ia.sptk", BR (0x20, 1, 0, 0, 0), PSEUDO},
{"br.ia.sptk.few.clr", BR (0x20, 1, 0, 0, 1)},
{"br.ia.sptk.clr", BR (0x20, 1, 0, 0, 1), PSEUDO},
{"br.ia.spnt.few", BR (0x20, 1, 0, 1, 0)},
{"br.ia.spnt", BR (0x20, 1, 0, 1, 0), PSEUDO},
{"br.ia.spnt.few.clr", BR (0x20, 1, 0, 1, 1)},
{"br.ia.spnt.clr", BR (0x20, 1, 0, 1, 1), PSEUDO},
{"br.ia.dptk.few", BR (0x20, 1, 0, 2, 0)},
{"br.ia.dptk", BR (0x20, 1, 0, 2, 0), PSEUDO},
{"br.ia.dptk.few.clr", BR (0x20, 1, 0, 2, 1)},
{"br.ia.dptk.clr", BR (0x20, 1, 0, 2, 1), PSEUDO},
{"br.ia.dpnt.few", BR (0x20, 1, 0, 3, 0)},
{"br.ia.dpnt", BR (0x20, 1, 0, 3, 0), PSEUDO},
{"br.ia.dpnt.few.clr", BR (0x20, 1, 0, 3, 1)},
{"br.ia.dpnt.clr", BR (0x20, 1, 0, 3, 1), PSEUDO},
{"br.ia.sptk.many", BR (0x20, 1, 1, 0, 0)},
{"br.ia.sptk.many.clr", BR (0x20, 1, 1, 0, 1)},
{"br.ia.spnt.many", BR (0x20, 1, 1, 1, 0)},
{"br.ia.spnt.many.clr", BR (0x20, 1, 1, 1, 1)},
{"br.ia.dptk.many", BR (0x20, 1, 1, 2, 0)},
{"br.ia.dptk.many.clr", BR (0x20, 1, 1, 2, 1)},
{"br.ia.dpnt.many", BR (0x20, 1, 1, 3, 0)},
{"br.ia.dpnt.many.clr", BR (0x20, 1, 1, 3, 1)},
{"br.ret.sptk.few", BR (0x21, 4, 0, 0, 0), MOD_RRBS},
{"br.ret.sptk", BR (0x21, 4, 0, 0, 0), PSEUDO | MOD_RRBS},
{"br.ret.sptk.few.clr", BR (0x21, 4, 0, 0, 1), MOD_RRBS},
{"br.ret.sptk.clr", BR (0x21, 4, 0, 0, 1), PSEUDO | MOD_RRBS},
{"br.ret.spnt.few", BR (0x21, 4, 0, 1, 0), MOD_RRBS},
{"br.ret.spnt", BR (0x21, 4, 0, 1, 0), PSEUDO | MOD_RRBS},
{"br.ret.spnt.few.clr", BR (0x21, 4, 0, 1, 1), MOD_RRBS},
{"br.ret.spnt.clr", BR (0x21, 4, 0, 1, 1), PSEUDO | MOD_RRBS},
{"br.ret.dptk.few", BR (0x21, 4, 0, 2, 0), MOD_RRBS},
{"br.ret.dptk", BR (0x21, 4, 0, 2, 0), PSEUDO | MOD_RRBS},
{"br.ret.dptk.few.clr", BR (0x21, 4, 0, 2, 1), MOD_RRBS},
{"br.ret.dptk.clr", BR (0x21, 4, 0, 2, 1), PSEUDO | MOD_RRBS},
{"br.ret.dpnt.few", BR (0x21, 4, 0, 3, 0), MOD_RRBS},
{"br.ret.dpnt", BR (0x21, 4, 0, 3, 0), PSEUDO | MOD_RRBS},
{"br.ret.dpnt.few.clr", BR (0x21, 4, 0, 3, 1), MOD_RRBS},
{"br.ret.dpnt.clr", BR (0x21, 4, 0, 3, 1), PSEUDO | MOD_RRBS},
{"br.ret.sptk.many", BR (0x21, 4, 1, 0, 0), MOD_RRBS},
{"br.ret.sptk.many.clr", BR (0x21, 4, 1, 0, 1), MOD_RRBS},
{"br.ret.spnt.many", BR (0x21, 4, 1, 1, 0), MOD_RRBS},
{"br.ret.spnt.many.clr", BR (0x21, 4, 1, 1, 1), MOD_RRBS},
{"br.ret.dptk.many", BR (0x21, 4, 1, 2, 0), MOD_RRBS},
{"br.ret.dptk.many.clr", BR (0x21, 4, 1, 2, 1), MOD_RRBS},
{"br.ret.dpnt.many", BR (0x21, 4, 1, 3, 0), MOD_RRBS},
{"br.ret.dpnt.many.clr", BR (0x21, 4, 1, 3, 1), MOD_RRBS},
#undef BR
{"cover", B0, OpX6 (0, 0x02), {0, }, NO_PRED | LAST | MOD_RRBS},
{"clrrrb", B0, OpX6 (0, 0x04), {0, }, NO_PRED | LAST | MOD_RRBS},
{"clrrrb.pr", B0, OpX6 (0, 0x05), {0, }, NO_PRED | LAST | MOD_RRBS},
{"rfi", B0, OpX6 (0, 0x08), {0, }, NO_PRED | LAST | PRIV | MOD_RRBS},
{"bsw.0", B0, OpX6 (0, 0x0c), {0, }, NO_PRED | LAST | PRIV},
{"bsw.1", B0, OpX6 (0, 0x0d), {0, }, NO_PRED | LAST | PRIV},
{"epc", B0, OpX6 (0, 0x10), {0, }, NO_PRED},
{"break.b", B0, OpX6 (0, 0x00), {IMMU21}},
{"br.call.sptk.few", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}},
{"br.call.sptk", B, OpPaWhaD (1, 0, 0, 0), {B1, B2}, PSEUDO},
{"br.call.sptk.few.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}},
{"br.call.sptk.clr", B, OpPaWhaD (1, 0, 0, 1), {B1, B2}, PSEUDO},
{"br.call.spnt.few", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}},
{"br.call.spnt", B, OpPaWhaD (1, 0, 1, 0), {B1, B2}, PSEUDO},
{"br.call.spnt.few.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}},
{"br.call.spnt.clr", B, OpPaWhaD (1, 0, 1, 1), {B1, B2}, PSEUDO},
{"br.call.dptk.few", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}},
{"br.call.dptk", B, OpPaWhaD (1, 0, 2, 0), {B1, B2}, PSEUDO},
{"br.call.dptk.few.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}},
{"br.call.dptk.clr", B, OpPaWhaD (1, 0, 2, 1), {B1, B2}, PSEUDO},
{"br.call.dpnt.few", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}},
{"br.call.dpnt", B, OpPaWhaD (1, 0, 3, 0), {B1, B2}, PSEUDO},
{"br.call.dpnt.few.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}},
{"br.call.dpnt.clr", B, OpPaWhaD (1, 0, 3, 1), {B1, B2}, PSEUDO},
{"br.call.sptk.many", B, OpPaWhaD (1, 1, 0, 0), {B1, B2}},
{"br.call.sptk.many.clr", B, OpPaWhaD (1, 1, 0, 1), {B1, B2}},
{"br.call.spnt.many", B, OpPaWhaD (1, 1, 1, 0), {B1, B2}},
{"br.call.spnt.many.clr", B, OpPaWhaD (1, 1, 1, 1), {B1, B2}},
{"br.call.dptk.many", B, OpPaWhaD (1, 1, 2, 0), {B1, B2}},
{"br.call.dptk.many.clr", B, OpPaWhaD (1, 1, 2, 1), {B1, B2}},
{"br.call.dpnt.many", B, OpPaWhaD (1, 1, 3, 0), {B1, B2}},
{"br.call.dpnt.many.clr", B, OpPaWhaD (1, 1, 3, 1), {B1, B2}},
#define BRP(a,b,c) \
B0, OpX6IhWhb (2, a, b, c), {B2, TAG13}, NO_PRED
{"brp.sptk", BRP (0x10, 0, 0)},
{"brp.dptk", BRP (0x10, 0, 2)},
{"brp.sptk.imp", BRP (0x10, 1, 0)},
{"brp.dptk.imp", BRP (0x10, 1, 2)},
{"brp.ret.sptk", BRP (0x11, 0, 0)},
{"brp.ret.dptk", BRP (0x11, 0, 2)},
{"brp.ret.sptk.imp", BRP (0x11, 1, 0)},
{"brp.ret.dptk.imp", BRP (0x11, 1, 2)},
#undef BRP
{"nop.b", B0, OpX6 (2, 0x00), {IMMU21}},
#define BR(a,b) \
B0, OpBtypePaWhaDPr (4, 0, a, 0, b, 0), {TGT25c}, PSEUDO
{"br.few", BR (0, 0)},
{"br", BR (0, 0)},
{"br.few.clr", BR (0, 1)},
{"br.clr", BR (0, 1)},
{"br.many", BR (1, 0)},
{"br.many.clr", BR (1, 1)},
#undef BR
#define BR(a,b,c) \
B0, OpBtypePaWhaD (4, 0, a, b, c), {TGT25c}
{"br.cond.sptk.few", BR (0, 0, 0)},
{"br.cond.sptk", BR (0, 0, 0), PSEUDO},
{"br.cond.sptk.few.clr", BR (0, 0, 1)},
{"br.cond.sptk.clr", BR (0, 0, 1), PSEUDO},
{"br.cond.spnt.few", BR (0, 1, 0)},
{"br.cond.spnt", BR (0, 1, 0), PSEUDO},
{"br.cond.spnt.few.clr", BR (0, 1, 1)},
{"br.cond.spnt.clr", BR (0, 1, 1), PSEUDO},
{"br.cond.dptk.few", BR (0, 2, 0)},
{"br.cond.dptk", BR (0, 2, 0), PSEUDO},
{"br.cond.dptk.few.clr", BR (0, 2, 1)},
{"br.cond.dptk.clr", BR (0, 2, 1), PSEUDO},
{"br.cond.dpnt.few", BR (0, 3, 0)},
{"br.cond.dpnt", BR (0, 3, 0), PSEUDO},
{"br.cond.dpnt.few.clr", BR (0, 3, 1)},
{"br.cond.dpnt.clr", BR (0, 3, 1), PSEUDO},
{"br.cond.sptk.many", BR (1, 0, 0)},
{"br.cond.sptk.many.clr", BR (1, 0, 1)},
{"br.cond.spnt.many", BR (1, 1, 0)},
{"br.cond.spnt.many.clr", BR (1, 1, 1)},
{"br.cond.dptk.many", BR (1, 2, 0)},
{"br.cond.dptk.many.clr", BR (1, 2, 1)},
{"br.cond.dpnt.many", BR (1, 3, 0)},
{"br.cond.dpnt.many.clr", BR (1, 3, 1)},
{"br.sptk.few", BR (0, 0, 0)},
{"br.sptk", BR (0, 0, 0), PSEUDO},
{"br.sptk.few.clr", BR (0, 0, 1)},
{"br.sptk.clr", BR (0, 0, 1), PSEUDO},
{"br.spnt.few", BR (0, 1, 0)},
{"br.spnt", BR (0, 1, 0), PSEUDO},
{"br.spnt.few.clr", BR (0, 1, 1)},
{"br.spnt.clr", BR (0, 1, 1), PSEUDO},
{"br.dptk.few", BR (0, 2, 0)},
{"br.dptk", BR (0, 2, 0), PSEUDO},
{"br.dptk.few.clr", BR (0, 2, 1)},
{"br.dptk.clr", BR (0, 2, 1), PSEUDO},
{"br.dpnt.few", BR (0, 3, 0)},
{"br.dpnt", BR (0, 3, 0), PSEUDO},
{"br.dpnt.few.clr", BR (0, 3, 1)},
{"br.dpnt.clr", BR (0, 3, 1), PSEUDO},
{"br.sptk.many", BR (1, 0, 0)},
{"br.sptk.many.clr", BR (1, 0, 1)},
{"br.spnt.many", BR (1, 1, 0)},
{"br.spnt.many.clr", BR (1, 1, 1)},
{"br.dptk.many", BR (1, 2, 0)},
{"br.dptk.many.clr", BR (1, 2, 1)},
{"br.dpnt.many", BR (1, 3, 0)},
{"br.dpnt.many.clr", BR (1, 3, 1)},
#undef BR
#define BR(a,b,c,d) \
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
{"br.wexit.sptk.few", BR (2, 0, 0, 0) | MOD_RRBS},
{"br.wexit.sptk", BR (2, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.sptk.few.clr", BR (2, 0, 0, 1) | MOD_RRBS},
{"br.wexit.sptk.clr", BR (2, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.spnt.few", BR (2, 0, 1, 0) | MOD_RRBS},
{"br.wexit.spnt", BR (2, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.spnt.few.clr", BR (2, 0, 1, 1) | MOD_RRBS},
{"br.wexit.spnt.clr", BR (2, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.dptk.few", BR (2, 0, 2, 0) | MOD_RRBS},
{"br.wexit.dptk", BR (2, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.dptk.few.clr", BR (2, 0, 2, 1) | MOD_RRBS},
{"br.wexit.dptk.clr", BR (2, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.dpnt.few", BR (2, 0, 3, 0) | MOD_RRBS},
{"br.wexit.dpnt", BR (2, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.wexit.dpnt.few.clr", BR (2, 0, 3, 1) | MOD_RRBS},
{"br.wexit.dpnt.clr", BR (2, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.wexit.sptk.many", BR (2, 1, 0, 0) | MOD_RRBS},
{"br.wexit.sptk.many.clr", BR (2, 1, 0, 1) | MOD_RRBS},
{"br.wexit.spnt.many", BR (2, 1, 1, 0) | MOD_RRBS},
{"br.wexit.spnt.many.clr", BR (2, 1, 1, 1) | MOD_RRBS},
{"br.wexit.dptk.many", BR (2, 1, 2, 0) | MOD_RRBS},
{"br.wexit.dptk.many.clr", BR (2, 1, 2, 1) | MOD_RRBS},
{"br.wexit.dpnt.many", BR (2, 1, 3, 0) | MOD_RRBS},
{"br.wexit.dpnt.many.clr", BR (2, 1, 3, 1) | MOD_RRBS},
{"br.wtop.sptk.few", BR (3, 0, 0, 0) | MOD_RRBS},
{"br.wtop.sptk", BR (3, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.sptk.few.clr", BR (3, 0, 0, 1) | MOD_RRBS},
{"br.wtop.sptk.clr", BR (3, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.spnt.few", BR (3, 0, 1, 0) | MOD_RRBS},
{"br.wtop.spnt", BR (3, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.spnt.few.clr", BR (3, 0, 1, 1) | MOD_RRBS},
{"br.wtop.spnt.clr", BR (3, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.dptk.few", BR (3, 0, 2, 0) | MOD_RRBS},
{"br.wtop.dptk", BR (3, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.dptk.few.clr", BR (3, 0, 2, 1) | MOD_RRBS},
{"br.wtop.dptk.clr", BR (3, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.dpnt.few", BR (3, 0, 3, 0) | MOD_RRBS},
{"br.wtop.dpnt", BR (3, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.wtop.dpnt.few.clr", BR (3, 0, 3, 1) | MOD_RRBS},
{"br.wtop.dpnt.clr", BR (3, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.wtop.sptk.many", BR (3, 1, 0, 0) | MOD_RRBS},
{"br.wtop.sptk.many.clr", BR (3, 1, 0, 1) | MOD_RRBS},
{"br.wtop.spnt.many", BR (3, 1, 1, 0) | MOD_RRBS},
{"br.wtop.spnt.many.clr", BR (3, 1, 1, 1) | MOD_RRBS},
{"br.wtop.dptk.many", BR (3, 1, 2, 0) | MOD_RRBS},
{"br.wtop.dptk.many.clr", BR (3, 1, 2, 1) | MOD_RRBS},
{"br.wtop.dpnt.many", BR (3, 1, 3, 0) | MOD_RRBS},
{"br.wtop.dpnt.many.clr", BR (3, 1, 3, 1) | MOD_RRBS},
#undef BR
#define BR(a,b,c,d) \
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2 | NO_PRED
{"br.cloop.sptk.few", BR (5, 0, 0, 0)},
{"br.cloop.sptk", BR (5, 0, 0, 0) | PSEUDO},
{"br.cloop.sptk.few.clr", BR (5, 0, 0, 1)},
{"br.cloop.sptk.clr", BR (5, 0, 0, 1) | PSEUDO},
{"br.cloop.spnt.few", BR (5, 0, 1, 0)},
{"br.cloop.spnt", BR (5, 0, 1, 0) | PSEUDO},
{"br.cloop.spnt.few.clr", BR (5, 0, 1, 1)},
{"br.cloop.spnt.clr", BR (5, 0, 1, 1) | PSEUDO},
{"br.cloop.dptk.few", BR (5, 0, 2, 0)},
{"br.cloop.dptk", BR (5, 0, 2, 0) | PSEUDO},
{"br.cloop.dptk.few.clr", BR (5, 0, 2, 1)},
{"br.cloop.dptk.clr", BR (5, 0, 2, 1) | PSEUDO},
{"br.cloop.dpnt.few", BR (5, 0, 3, 0)},
{"br.cloop.dpnt", BR (5, 0, 3, 0) | PSEUDO},
{"br.cloop.dpnt.few.clr", BR (5, 0, 3, 1)},
{"br.cloop.dpnt.clr", BR (5, 0, 3, 1) | PSEUDO},
{"br.cloop.sptk.many", BR (5, 1, 0, 0)},
{"br.cloop.sptk.many.clr", BR (5, 1, 0, 1)},
{"br.cloop.spnt.many", BR (5, 1, 1, 0)},
{"br.cloop.spnt.many.clr", BR (5, 1, 1, 1)},
{"br.cloop.dptk.many", BR (5, 1, 2, 0)},
{"br.cloop.dptk.many.clr", BR (5, 1, 2, 1)},
{"br.cloop.dpnt.many", BR (5, 1, 3, 0)},
{"br.cloop.dpnt.many.clr", BR (5, 1, 3, 1)},
{"br.cexit.sptk.few", BR (6, 0, 0, 0) | MOD_RRBS},
{"br.cexit.sptk", BR (6, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.sptk.few.clr", BR (6, 0, 0, 1) | MOD_RRBS},
{"br.cexit.sptk.clr", BR (6, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.spnt.few", BR (6, 0, 1, 0) | MOD_RRBS},
{"br.cexit.spnt", BR (6, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.spnt.few.clr", BR (6, 0, 1, 1) | MOD_RRBS},
{"br.cexit.spnt.clr", BR (6, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.dptk.few", BR (6, 0, 2, 0) | MOD_RRBS},
{"br.cexit.dptk", BR (6, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.dptk.few.clr", BR (6, 0, 2, 1) | MOD_RRBS},
{"br.cexit.dptk.clr", BR (6, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.dpnt.few", BR (6, 0, 3, 0) | MOD_RRBS},
{"br.cexit.dpnt", BR (6, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.cexit.dpnt.few.clr", BR (6, 0, 3, 1) | MOD_RRBS},
{"br.cexit.dpnt.clr", BR (6, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.cexit.sptk.many", BR (6, 1, 0, 0) | MOD_RRBS},
{"br.cexit.sptk.many.clr", BR (6, 1, 0, 1) | MOD_RRBS},
{"br.cexit.spnt.many", BR (6, 1, 1, 0) | MOD_RRBS},
{"br.cexit.spnt.many.clr", BR (6, 1, 1, 1) | MOD_RRBS},
{"br.cexit.dptk.many", BR (6, 1, 2, 0) | MOD_RRBS},
{"br.cexit.dptk.many.clr", BR (6, 1, 2, 1) | MOD_RRBS},
{"br.cexit.dpnt.many", BR (6, 1, 3, 0) | MOD_RRBS},
{"br.cexit.dpnt.many.clr", BR (6, 1, 3, 1) | MOD_RRBS},
{"br.ctop.sptk.few", BR (7, 0, 0, 0) | MOD_RRBS},
{"br.ctop.sptk", BR (7, 0, 0, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.sptk.few.clr", BR (7, 0, 0, 1) | MOD_RRBS},
{"br.ctop.sptk.clr", BR (7, 0, 0, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.spnt.few", BR (7, 0, 1, 0) | MOD_RRBS},
{"br.ctop.spnt", BR (7, 0, 1, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.spnt.few.clr", BR (7, 0, 1, 1) | MOD_RRBS},
{"br.ctop.spnt.clr", BR (7, 0, 1, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.dptk.few", BR (7, 0, 2, 0) | MOD_RRBS},
{"br.ctop.dptk", BR (7, 0, 2, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.dptk.few.clr", BR (7, 0, 2, 1) | MOD_RRBS},
{"br.ctop.dptk.clr", BR (7, 0, 2, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.dpnt.few", BR (7, 0, 3, 0) | MOD_RRBS},
{"br.ctop.dpnt", BR (7, 0, 3, 0) | PSEUDO | MOD_RRBS},
{"br.ctop.dpnt.few.clr", BR (7, 0, 3, 1) | MOD_RRBS},
{"br.ctop.dpnt.clr", BR (7, 0, 3, 1) | PSEUDO | MOD_RRBS},
{"br.ctop.sptk.many", BR (7, 1, 0, 0) | MOD_RRBS},
{"br.ctop.sptk.many.clr", BR (7, 1, 0, 1) | MOD_RRBS},
{"br.ctop.spnt.many", BR (7, 1, 1, 0) | MOD_RRBS},
{"br.ctop.spnt.many.clr", BR (7, 1, 1, 1) | MOD_RRBS},
{"br.ctop.dptk.many", BR (7, 1, 2, 0) | MOD_RRBS},
{"br.ctop.dptk.many.clr", BR (7, 1, 2, 1) | MOD_RRBS},
{"br.ctop.dpnt.many", BR (7, 1, 3, 0) | MOD_RRBS},
{"br.ctop.dpnt.many.clr", BR (7, 1, 3, 1) | MOD_RRBS},
#undef BR
#define BR(a,b,c,d) \
B0, OpBtypePaWhaD (4, a, b, c, d), {TGT25c}, SLOT2
{"br.call.sptk.few", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}},
{"br.call.sptk", B, OpPaWhaD (5, 0, 0, 0), {B1, TGT25c}, PSEUDO},
{"br.call.sptk.few.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}},
{"br.call.sptk.clr", B, OpPaWhaD (5, 0, 0, 1), {B1, TGT25c}, PSEUDO},
{"br.call.spnt.few", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}},
{"br.call.spnt", B, OpPaWhaD (5, 0, 1, 0), {B1, TGT25c}, PSEUDO},
{"br.call.spnt.few.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}},
{"br.call.spnt.clr", B, OpPaWhaD (5, 0, 1, 1), {B1, TGT25c}, PSEUDO},
{"br.call.dptk.few", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}},
{"br.call.dptk", B, OpPaWhaD (5, 0, 2, 0), {B1, TGT25c}, PSEUDO},
{"br.call.dptk.few.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}},
{"br.call.dptk.clr", B, OpPaWhaD (5, 0, 2, 1), {B1, TGT25c}, PSEUDO},
{"br.call.dpnt.few", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}},
{"br.call.dpnt", B, OpPaWhaD (5, 0, 3, 0), {B1, TGT25c}, PSEUDO},
{"br.call.dpnt.few.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}},
{"br.call.dpnt.clr", B, OpPaWhaD (5, 0, 3, 1), {B1, TGT25c}, PSEUDO},
{"br.call.sptk.many", B, OpPaWhaD (5, 1, 0, 0), {B1, TGT25c}},
{"br.call.sptk.many.clr", B, OpPaWhaD (5, 1, 0, 1), {B1, TGT25c}},
{"br.call.spnt.many", B, OpPaWhaD (5, 1, 1, 0), {B1, TGT25c}},
{"br.call.spnt.many.clr", B, OpPaWhaD (5, 1, 1, 1), {B1, TGT25c}},
{"br.call.dptk.many", B, OpPaWhaD (5, 1, 2, 0), {B1, TGT25c}},
{"br.call.dptk.many.clr", B, OpPaWhaD (5, 1, 2, 1), {B1, TGT25c}},
{"br.call.dpnt.many", B, OpPaWhaD (5, 1, 3, 0), {B1, TGT25c}},
{"br.call.dpnt.many.clr", B, OpPaWhaD (5, 1, 3, 1), {B1, TGT25c}},
#undef BR
/* branch predict */
#define BRP(a,b) \
B0, OpIhWhb (7, a, b), {TGT25c, TAG13}, NO_PRED
{"brp.sptk", BRP (0, 0)},
{"brp.loop", BRP (0, 1)},
{"brp.dptk", BRP (0, 2)},
{"brp.exit", BRP (0, 3)},
{"brp.sptk.imp", BRP (1, 0)},
{"brp.loop.imp", BRP (1, 1)},
{"brp.dptk.imp", BRP (1, 2)},
{"brp.exit.imp", BRP (1, 3)},
#undef BRP
{0}
};
#undef B0
#undef B
#undef bBtype
#undef bD
#undef bIh
#undef bPa
#undef bPr
#undef bWha
#undef bWhb
#undef bX6
#undef mBtype
#undef mD
#undef mIh
#undef mPa
#undef mPr
#undef mWha
#undef mWhb
#undef mX6
#undef OpX6
#undef OpPaWhaD
#undef OpBtypePaWhaD
#undef OpBtypePaWhaDPr
#undef OpX6BtypePaWhaD
#undef OpX6BtypePaWhaDPr
#undef OpIhWhb
#undef OpX6IhWhb

14
contrib/binutils/opcodes/ia64-opc-d.c Normal file
View File

@ -0,0 +1,14 @@
struct ia64_opcode ia64_opcodes_d[] =
{
{"add", IA64_TYPE_DYN, 1, 0, 0,
{IA64_OPND_R1, IA64_OPND_IMM22, IA64_OPND_R3_2}},
{"add", IA64_TYPE_DYN, 1, 0, 0,
{IA64_OPND_R1, IA64_OPND_IMM14, IA64_OPND_R3}},
{"break", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}},
{"chk.s", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_R2, IA64_OPND_TGT25b}},
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_R1, IA64_OPND_AR3}},
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_IMM8}},
{"mov", IA64_TYPE_DYN, 1, 0, 0, {IA64_OPND_AR3, IA64_OPND_R2}},
{"nop", IA64_TYPE_DYN, 0, 0, 0, {IA64_OPND_IMMU21}},
{0}
};

646
contrib/binutils/opcodes/ia64-opc-f.c Normal file
View File

@ -0,0 +1,646 @@
/* ia64-opc-f.c -- IA-64 `F' opcode table.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
#define f0 IA64_TYPE_F, 0
#define f IA64_TYPE_F, 1
#define f2 IA64_TYPE_F, 2
#define bF2(x) (((ia64_insn) ((x) & 0x7f)) << 13)
#define bF4(x) (((ia64_insn) ((x) & 0x7f)) << 27)
#define bQ(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bRa(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bRb(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bSf(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bXa(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define mF2 bF2 (-1)
#define mF4 bF4 (-1)
#define mQ bQ (-1)
#define mRa bRa (-1)
#define mRb bRb (-1)
#define mSf bSf (-1)
#define mTa bTa (-1)
#define mXa bXa (-1)
#define mXb bXb (-1)
#define mX2 bX2 (-1)
#define mX6 bX6 (-1)
#define OpXa(a,b) (bOp (a) | bXa (b)), (mOp | mXa)
#define OpXaSf(a,b,c) (bOp (a) | bXa (b) | bSf (c)), (mOp | mXa | mSf)
#define OpXaSfF2(a,b,c,d) \
(bOp (a) | bXa (b) | bSf (c) | bF2 (d)), (mOp | mXa | mSf | mF2)
#define OpXaSfF4(a,b,c,d) \
(bOp (a) | bXa (b) | bSf (c) | bF4 (d)), (mOp | mXa | mSf | mF4)
#define OpXaSfF2F4(a,b,c,d,e) \
(bOp (a) | bXa (b) | bSf (c) | bF2 (d) | bF4 (e)), \
(mOp | mXa | mSf | mF2 | mF4)
#define OpXaX2(a,b,c) (bOp (a) | bXa (b) | bX2 (c)), (mOp | mXa | mX2)
#define OpXaX2F2(a,b,c,d) \
(bOp (a) | bXa (b) | bX2 (c) | bF2 (d)), (mOp | mXa | mX2 | mF2)
#define OpRaRbTaSf(a,b,c,d,e) \
(bOp (a) | bRa (b) | bRb (c) | bTa (d) | bSf (e)), \
(mOp | mRa | mRb | mTa | mSf)
#define OpTa(a,b) (bOp (a) | bTa (b)), (mOp | mTa)
#define OpXbQSf(a,b,c,d) \
(bOp (a) | bXb (b) | bQ (c) | bSf (d)), (mOp | mXb | mQ | mSf)
#define OpXbX6(a,b,c) \
(bOp (a) | bXb (b) | bX6 (c)), (mOp | mXb | mX6)
#define OpXbX6F2(a,b,c,d) \
(bOp (a) | bXb (b) | bX6 (c) | bF2 (d)), (mOp | mXb | mX6 | mF2)
#define OpXbX6Sf(a,b,c,d) \
(bOp (a) | bXb (b) | bX6 (c) | bSf (d)), (mOp | mXb | mX6 | mSf)
struct ia64_opcode ia64_opcodes_f[] =
{
/* F-type instruction encodings (sorted according to major opcode) */
{"frcpa.s0", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}},
{"frcpa", f2, OpXbQSf (0, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO},
{"frcpa.s1", f2, OpXbQSf (0, 1, 0, 1), {F1, P2, F2, F3}},
{"frcpa.s2", f2, OpXbQSf (0, 1, 0, 2), {F1, P2, F2, F3}},
{"frcpa.s3", f2, OpXbQSf (0, 1, 0, 3), {F1, P2, F2, F3}},
{"frsqrta.s0", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}},
{"frsqrta", f2, OpXbQSf (0, 1, 1, 0), {F1, P2, F3}, PSEUDO},
{"frsqrta.s1", f2, OpXbQSf (0, 1, 1, 1), {F1, P2, F3}},
{"frsqrta.s2", f2, OpXbQSf (0, 1, 1, 2), {F1, P2, F3}},
{"frsqrta.s3", f2, OpXbQSf (0, 1, 1, 3), {F1, P2, F3}},
{"fmin.s0", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}},
{"fmin", f, OpXbX6Sf (0, 0, 0x14, 0), {F1, F2, F3}, PSEUDO},
{"fmin.s1", f, OpXbX6Sf (0, 0, 0x14, 1), {F1, F2, F3}},
{"fmin.s2", f, OpXbX6Sf (0, 0, 0x14, 2), {F1, F2, F3}},
{"fmin.s3", f, OpXbX6Sf (0, 0, 0x14, 3), {F1, F2, F3}},
{"fmax.s0", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}},
{"fmax", f, OpXbX6Sf (0, 0, 0x15, 0), {F1, F2, F3}, PSEUDO},
{"fmax.s1", f, OpXbX6Sf (0, 0, 0x15, 1), {F1, F2, F3}},
{"fmax.s2", f, OpXbX6Sf (0, 0, 0x15, 2), {F1, F2, F3}},
{"fmax.s3", f, OpXbX6Sf (0, 0, 0x15, 3), {F1, F2, F3}},
{"famin.s0", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}},
{"famin", f, OpXbX6Sf (0, 0, 0x16, 0), {F1, F2, F3}, PSEUDO},
{"famin.s1", f, OpXbX6Sf (0, 0, 0x16, 1), {F1, F2, F3}},
{"famin.s2", f, OpXbX6Sf (0, 0, 0x16, 2), {F1, F2, F3}},
{"famin.s3", f, OpXbX6Sf (0, 0, 0x16, 3), {F1, F2, F3}},
{"famax.s0", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}},
{"famax", f, OpXbX6Sf (0, 0, 0x17, 0), {F1, F2, F3}, PSEUDO},
{"famax.s1", f, OpXbX6Sf (0, 0, 0x17, 1), {F1, F2, F3}},
{"famax.s2", f, OpXbX6Sf (0, 0, 0x17, 2), {F1, F2, F3}},
{"famax.s3", f, OpXbX6Sf (0, 0, 0x17, 3), {F1, F2, F3}},
{"mov", f, OpXbX6 (0, 0, 0x10), {F1, F3}, PSEUDO | F2_EQ_F3},
{"fabs", f, OpXbX6F2 (0, 0, 0x10, 0), {F1, F3}, PSEUDO},
{"fneg", f, OpXbX6 (0, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3},
{"fnegabs", f, OpXbX6F2 (0, 0, 0x11, 0), {F1, F3}, PSEUDO},
{"fmerge.s", f, OpXbX6 (0, 0, 0x10), {F1, F2, F3}},
{"fmerge.ns", f, OpXbX6 (0, 0, 0x11), {F1, F2, F3}},
{"fmerge.se", f, OpXbX6 (0, 0, 0x12), {F1, F2, F3}},
{"fmix.lr", f, OpXbX6 (0, 0, 0x39), {F1, F2, F3}},
{"fmix.r", f, OpXbX6 (0, 0, 0x3a), {F1, F2, F3}},
{"fmix.l", f, OpXbX6 (0, 0, 0x3b), {F1, F2, F3}},
{"fsxt.r", f, OpXbX6 (0, 0, 0x3c), {F1, F2, F3}},
{"fsxt.l", f, OpXbX6 (0, 0, 0x3d), {F1, F2, F3}},
{"fpack", f, OpXbX6 (0, 0, 0x28), {F1, F2, F3}},
{"fswap", f, OpXbX6 (0, 0, 0x34), {F1, F2, F3}},
{"fswap.nl", f, OpXbX6 (0, 0, 0x35), {F1, F2, F3}},
{"fswap.nr", f, OpXbX6 (0, 0, 0x36), {F1, F2, F3}},
{"fand", f, OpXbX6 (0, 0, 0x2c), {F1, F2, F3}},
{"fandcm", f, OpXbX6 (0, 0, 0x2d), {F1, F2, F3}},
{"for", f, OpXbX6 (0, 0, 0x2e), {F1, F2, F3}},
{"fxor", f, OpXbX6 (0, 0, 0x2f), {F1, F2, F3}},
{"fcvt.fx.s0", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}},
{"fcvt.fx", f, OpXbX6Sf (0, 0, 0x18, 0), {F1, F2}, PSEUDO},
{"fcvt.fx.s1", f, OpXbX6Sf (0, 0, 0x18, 1), {F1, F2}},
{"fcvt.fx.s2", f, OpXbX6Sf (0, 0, 0x18, 2), {F1, F2}},
{"fcvt.fx.s3", f, OpXbX6Sf (0, 0, 0x18, 3), {F1, F2}},
{"fcvt.fxu.s0", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}},
{"fcvt.fxu", f, OpXbX6Sf (0, 0, 0x19, 0), {F1, F2}, PSEUDO},
{"fcvt.fxu.s1", f, OpXbX6Sf (0, 0, 0x19, 1), {F1, F2}},
{"fcvt.fxu.s2", f, OpXbX6Sf (0, 0, 0x19, 2), {F1, F2}},
{"fcvt.fxu.s3", f, OpXbX6Sf (0, 0, 0x19, 3), {F1, F2}},
{"fcvt.fx.trunc.s0", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}},
{"fcvt.fx.trunc", f, OpXbX6Sf (0, 0, 0x1a, 0), {F1, F2}, PSEUDO},
{"fcvt.fx.trunc.s1", f, OpXbX6Sf (0, 0, 0x1a, 1), {F1, F2}},
{"fcvt.fx.trunc.s2", f, OpXbX6Sf (0, 0, 0x1a, 2), {F1, F2}},
{"fcvt.fx.trunc.s3", f, OpXbX6Sf (0, 0, 0x1a, 3), {F1, F2}},
{"fcvt.fxu.trunc.s0", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}},
{"fcvt.fxu.trunc", f, OpXbX6Sf (0, 0, 0x1b, 0), {F1, F2}, PSEUDO},
{"fcvt.fxu.trunc.s1", f, OpXbX6Sf (0, 0, 0x1b, 1), {F1, F2}},
{"fcvt.fxu.trunc.s2", f, OpXbX6Sf (0, 0, 0x1b, 2), {F1, F2}},
{"fcvt.fxu.trunc.s3", f, OpXbX6Sf (0, 0, 0x1b, 3), {F1, F2}},
{"fcvt.xf", f, OpXbX6 (0, 0, 0x1c), {F1, F2}},
{"fsetc.s0", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}},
{"fsetc", f0, OpXbX6Sf (0, 0, 0x04, 0), {IMMU7a, IMMU7b}, PSEUDO},
{"fsetc.s1", f0, OpXbX6Sf (0, 0, 0x04, 1), {IMMU7a, IMMU7b}},
{"fsetc.s2", f0, OpXbX6Sf (0, 0, 0x04, 2), {IMMU7a, IMMU7b}},
{"fsetc.s3", f0, OpXbX6Sf (0, 0, 0x04, 3), {IMMU7a, IMMU7b}},
{"fclrf.s0", f0, OpXbX6Sf (0, 0, 0x05, 0)},
{"fclrf", f0, OpXbX6Sf (0, 0, 0x05, 0), {0}, PSEUDO},
{"fclrf.s1", f0, OpXbX6Sf (0, 0, 0x05, 1)},
{"fclrf.s2", f0, OpXbX6Sf (0, 0, 0x05, 2)},
{"fclrf.s3", f0, OpXbX6Sf (0, 0, 0x05, 3)},
{"fchkf.s0", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}},
{"fchkf", f0, OpXbX6Sf (0, 0, 0x08, 0), {TGT25}, PSEUDO},
{"fchkf.s1", f0, OpXbX6Sf (0, 0, 0x08, 1), {TGT25}},
{"fchkf.s2", f0, OpXbX6Sf (0, 0, 0x08, 2), {TGT25}},
{"fchkf.s3", f0, OpXbX6Sf (0, 0, 0x08, 3), {TGT25}},
{"break.f", f0, OpXbX6 (0, 0, 0x00), {IMMU21}},
{"nop.f", f0, OpXbX6 (0, 0, 0x01), {IMMU21}},
{"fprcpa.s0", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}},
{"fprcpa", f2, OpXbQSf (1, 1, 0, 0), {F1, P2, F2, F3}, PSEUDO},
{"fprcpa.s1", f2, OpXbQSf (1, 1, 0, 1), {F1, P2, F2, F3}},
{"fprcpa.s2", f2, OpXbQSf (1, 1, 0, 2), {F1, P2, F2, F3}},
{"fprcpa.s3", f2, OpXbQSf (1, 1, 0, 3), {F1, P2, F2, F3}},
{"fprsqrta.s0", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}},
{"fprsqrta", f2, OpXbQSf (1, 1, 1, 0), {F1, P2, F3}, PSEUDO},
{"fprsqrta.s1", f2, OpXbQSf (1, 1, 1, 1), {F1, P2, F3}},
{"fprsqrta.s2", f2, OpXbQSf (1, 1, 1, 2), {F1, P2, F3}},
{"fprsqrta.s3", f2, OpXbQSf (1, 1, 1, 3), {F1, P2, F3}},
{"fpmin.s0", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}},
{"fpmin", f, OpXbX6Sf (1, 0, 0x14, 0), {F1, F2, F3}, PSEUDO},
{"fpmin.s1", f, OpXbX6Sf (1, 0, 0x14, 1), {F1, F2, F3}},
{"fpmin.s2", f, OpXbX6Sf (1, 0, 0x14, 2), {F1, F2, F3}},
{"fpmin.s3", f, OpXbX6Sf (1, 0, 0x14, 3), {F1, F2, F3}},
{"fpmax.s0", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}},
{"fpmax", f, OpXbX6Sf (1, 0, 0x15, 0), {F1, F2, F3}, PSEUDO},
{"fpmax.s1", f, OpXbX6Sf (1, 0, 0x15, 1), {F1, F2, F3}},
{"fpmax.s2", f, OpXbX6Sf (1, 0, 0x15, 2), {F1, F2, F3}},
{"fpmax.s3", f, OpXbX6Sf (1, 0, 0x15, 3), {F1, F2, F3}},
{"fpamin.s0", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}},
{"fpamin", f, OpXbX6Sf (1, 0, 0x16, 0), {F1, F2, F3}, PSEUDO},
{"fpamin.s1", f, OpXbX6Sf (1, 0, 0x16, 1), {F1, F2, F3}},
{"fpamin.s2", f, OpXbX6Sf (1, 0, 0x16, 2), {F1, F2, F3}},
{"fpamin.s3", f, OpXbX6Sf (1, 0, 0x16, 3), {F1, F2, F3}},
{"fpamax.s0", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}},
{"fpamax", f, OpXbX6Sf (1, 0, 0x17, 0), {F1, F2, F3}, PSEUDO},
{"fpamax.s1", f, OpXbX6Sf (1, 0, 0x17, 1), {F1, F2, F3}},
{"fpamax.s2", f, OpXbX6Sf (1, 0, 0x17, 2), {F1, F2, F3}},
{"fpamax.s3", f, OpXbX6Sf (1, 0, 0x17, 3), {F1, F2, F3}},
{"fpcmp.eq.s0", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}},
{"fpcmp.eq", f, OpXbX6Sf (1, 0, 0x30, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.eq.s1", f, OpXbX6Sf (1, 0, 0x30, 1), {F1, F2, F3}},
{"fpcmp.eq.s2", f, OpXbX6Sf (1, 0, 0x30, 2), {F1, F2, F3}},
{"fpcmp.eq.s3", f, OpXbX6Sf (1, 0, 0x30, 3), {F1, F2, F3}},
{"fpcmp.lt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}},
{"fpcmp.lt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.lt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F2, F3}},
{"fpcmp.lt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F2, F3}},
{"fpcmp.lt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F2, F3}},
{"fpcmp.le.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}},
{"fpcmp.le", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.le.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F2, F3}},
{"fpcmp.le.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F2, F3}},
{"fpcmp.le.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F2, F3}},
{"fpcmp.gt.s0", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.gt", f, OpXbX6Sf (1, 0, 0x31, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.gt.s1", f, OpXbX6Sf (1, 0, 0x31, 1), {F1, F3, F2}, PSEUDO},
{"fpcmp.gt.s2", f, OpXbX6Sf (1, 0, 0x31, 2), {F1, F3, F2}, PSEUDO},
{"fpcmp.gt.s3", f, OpXbX6Sf (1, 0, 0x31, 3), {F1, F3, F2}, PSEUDO},
{"fpcmp.ge.s0", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.ge", f, OpXbX6Sf (1, 0, 0x32, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.ge.s1", f, OpXbX6Sf (1, 0, 0x32, 1), {F1, F3, F2}, PSEUDO},
{"fpcmp.ge.s2", f, OpXbX6Sf (1, 0, 0x32, 2), {F1, F3, F2}, PSEUDO},
{"fpcmp.ge.s3", f, OpXbX6Sf (1, 0, 0x32, 3), {F1, F3, F2}, PSEUDO},
{"fpcmp.unord.s0", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}},
{"fpcmp.unord", f, OpXbX6Sf (1, 0, 0x33, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.unord.s1", f, OpXbX6Sf (1, 0, 0x33, 1), {F1, F2, F3}},
{"fpcmp.unord.s2", f, OpXbX6Sf (1, 0, 0x33, 2), {F1, F2, F3}},
{"fpcmp.unord.s3", f, OpXbX6Sf (1, 0, 0x33, 3), {F1, F2, F3}},
{"fpcmp.neq.s0", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}},
{"fpcmp.neq", f, OpXbX6Sf (1, 0, 0x34, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.neq.s1", f, OpXbX6Sf (1, 0, 0x34, 1), {F1, F2, F3}},
{"fpcmp.neq.s2", f, OpXbX6Sf (1, 0, 0x34, 2), {F1, F2, F3}},
{"fpcmp.neq.s3", f, OpXbX6Sf (1, 0, 0x34, 3), {F1, F2, F3}},
{"fpcmp.nlt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}},
{"fpcmp.nlt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.nlt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F2, F3}},
{"fpcmp.nlt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F2, F3}},
{"fpcmp.nlt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F2, F3}},
{"fpcmp.nle.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}},
{"fpcmp.nle", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.nle.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F2, F3}},
{"fpcmp.nle.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F2, F3}},
{"fpcmp.nle.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F2, F3}},
{"fpcmp.ngt.s0", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.ngt", f, OpXbX6Sf (1, 0, 0x35, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.ngt.s1", f, OpXbX6Sf (1, 0, 0x35, 1), {F1, F3, F2}, PSEUDO},
{"fpcmp.ngt.s2", f, OpXbX6Sf (1, 0, 0x35, 2), {F1, F3, F2}, PSEUDO},
{"fpcmp.ngt.s3", f, OpXbX6Sf (1, 0, 0x35, 3), {F1, F3, F2}, PSEUDO},
{"fpcmp.nge.s0", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.nge", f, OpXbX6Sf (1, 0, 0x36, 0), {F1, F3, F2}, PSEUDO},
{"fpcmp.nge.s1", f, OpXbX6Sf (1, 0, 0x36, 1), {F1, F3, F2}, PSEUDO},
{"fpcmp.nge.s2", f, OpXbX6Sf (1, 0, 0x36, 2), {F1, F3, F2}, PSEUDO},
{"fpcmp.nge.s3", f, OpXbX6Sf (1, 0, 0x36, 3), {F1, F3, F2}, PSEUDO},
{"fpcmp.ord.s0", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}},
{"fpcmp.ord", f, OpXbX6Sf (1, 0, 0x37, 0), {F1, F2, F3}, PSEUDO},
{"fpcmp.ord.s1", f, OpXbX6Sf (1, 0, 0x37, 1), {F1, F2, F3}},
{"fpcmp.ord.s2", f, OpXbX6Sf (1, 0, 0x37, 2), {F1, F2, F3}},
{"fpcmp.ord.s3", f, OpXbX6Sf (1, 0, 0x37, 3), {F1, F2, F3}},
{"fpabs", f, OpXbX6F2 (1, 0, 0x10, 0), {F1, F3}, PSEUDO},
{"fpneg", f, OpXbX6 (1, 0, 0x11), {F1, F3}, PSEUDO | F2_EQ_F3},
{"fpnegabs", f, OpXbX6F2 (1, 0, 0x11, 0), {F1, F3}, PSEUDO},
{"fpmerge.s", f, OpXbX6 (1, 0, 0x10), {F1, F2, F3}},
{"fpmerge.ns", f, OpXbX6 (1, 0, 0x11), {F1, F2, F3}},
{"fpmerge.se", f, OpXbX6 (1, 0, 0x12), {F1, F2, F3}},
{"fpcvt.fx.s0", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}},
{"fpcvt.fx", f, OpXbX6Sf (1, 0, 0x18, 0), {F1, F2}, PSEUDO},
{"fpcvt.fx.s1", f, OpXbX6Sf (1, 0, 0x18, 1), {F1, F2}},
{"fpcvt.fx.s2", f, OpXbX6Sf (1, 0, 0x18, 2), {F1, F2}},
{"fpcvt.fx.s3", f, OpXbX6Sf (1, 0, 0x18, 3), {F1, F2}},
{"fpcvt.fxu.s0", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}},
{"fpcvt.fxu", f, OpXbX6Sf (1, 0, 0x19, 0), {F1, F2}, PSEUDO},
{"fpcvt.fxu.s1", f, OpXbX6Sf (1, 0, 0x19, 1), {F1, F2}},
{"fpcvt.fxu.s2", f, OpXbX6Sf (1, 0, 0x19, 2), {F1, F2}},
{"fpcvt.fxu.s3", f, OpXbX6Sf (1, 0, 0x19, 3), {F1, F2}},
{"fpcvt.fx.trunc.s0", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}},
{"fpcvt.fx.trunc", f, OpXbX6Sf (1, 0, 0x1a, 0), {F1, F2}, PSEUDO},
{"fpcvt.fx.trunc.s1", f, OpXbX6Sf (1, 0, 0x1a, 1), {F1, F2}},
{"fpcvt.fx.trunc.s2", f, OpXbX6Sf (1, 0, 0x1a, 2), {F1, F2}},
{"fpcvt.fx.trunc.s3", f, OpXbX6Sf (1, 0, 0x1a, 3), {F1, F2}},
{"fpcvt.fxu.trunc.s0", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}},
{"fpcvt.fxu.trunc", f, OpXbX6Sf (1, 0, 0x1b, 0), {F1, F2}, PSEUDO},
{"fpcvt.fxu.trunc.s1", f, OpXbX6Sf (1, 0, 0x1b, 1), {F1, F2}},
{"fpcvt.fxu.trunc.s2", f, OpXbX6Sf (1, 0, 0x1b, 2), {F1, F2}},
{"fpcvt.fxu.trunc.s3", f, OpXbX6Sf (1, 0, 0x1b, 3), {F1, F2}},
{"fcmp.eq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}},
{"fcmp.eq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.eq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P1, P2, F2, F3}},
{"fcmp.eq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P1, P2, F2, F3}},
{"fcmp.eq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P1, P2, F2, F3}},
{"fcmp.lt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}},
{"fcmp.lt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.lt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F2, F3}},
{"fcmp.lt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F2, F3}},
{"fcmp.lt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F2, F3}},
{"fcmp.le.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}},
{"fcmp.le", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.le.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F2, F3}},
{"fcmp.le.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F2, F3}},
{"fcmp.le.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F2, F3}},
{"fcmp.unord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}},
{"fcmp.unord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.unord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P1, P2, F2, F3}},
{"fcmp.unord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P1, P2, F2, F3}},
{"fcmp.unord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P1, P2, F2, F3}},
{"fcmp.eq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}},
{"fcmp.eq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.eq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P1, P2, F2, F3}},
{"fcmp.eq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P1, P2, F2, F3}},
{"fcmp.eq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P1, P2, F2, F3}},
{"fcmp.lt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}},
{"fcmp.lt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.lt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F2, F3}},
{"fcmp.lt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F2, F3}},
{"fcmp.lt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F2, F3}},
{"fcmp.le.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}},
{"fcmp.le.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.le.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F2, F3}},
{"fcmp.le.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F2, F3}},
{"fcmp.le.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F2, F3}},
{"fcmp.unord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}},
{"fcmp.unord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P1, P2, F2, F3}, PSEUDO},
{"fcmp.unord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P1, P2, F2, F3}},
{"fcmp.unord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P1, P2, F2, F3}},
{"fcmp.unord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P1, P2, F2, F3}},
/* pseudo-ops of the above */
{"fcmp.gt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}},
{"fcmp.gt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P1, P2, F3, F2}, PSEUDO},
{"fcmp.gt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P1, P2, F3, F2}},
{"fcmp.gt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P1, P2, F3, F2}},
{"fcmp.gt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P1, P2, F3, F2}},
{"fcmp.ge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}},
{"fcmp.ge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P1, P2, F3, F2}, PSEUDO},
{"fcmp.ge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P1, P2, F3, F2}},
{"fcmp.ge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P1, P2, F3, F2}},
{"fcmp.ge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P1, P2, F3, F2}},
{"fcmp.neq.s0", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}},
{"fcmp.neq", f2, OpRaRbTaSf (4, 0, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.neq.s1", f2, OpRaRbTaSf (4, 0, 0, 0, 1), {P2, P1, F2, F3}},
{"fcmp.neq.s2", f2, OpRaRbTaSf (4, 0, 0, 0, 2), {P2, P1, F2, F3}},
{"fcmp.neq.s3", f2, OpRaRbTaSf (4, 0, 0, 0, 3), {P2, P1, F2, F3}},
{"fcmp.nlt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}},
{"fcmp.nlt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.nlt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F2, F3}},
{"fcmp.nlt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F2, F3}},
{"fcmp.nlt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F2, F3}},
{"fcmp.nle.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}},
{"fcmp.nle", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.nle.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F2, F3}},
{"fcmp.nle.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F2, F3}},
{"fcmp.nle.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F2, F3}},
{"fcmp.ngt.s0", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}},
{"fcmp.ngt", f2, OpRaRbTaSf (4, 0, 1, 0, 0), {P2, P1, F3, F2}, PSEUDO},
{"fcmp.ngt.s1", f2, OpRaRbTaSf (4, 0, 1, 0, 1), {P2, P1, F3, F2}},
{"fcmp.ngt.s2", f2, OpRaRbTaSf (4, 0, 1, 0, 2), {P2, P1, F3, F2}},
{"fcmp.ngt.s3", f2, OpRaRbTaSf (4, 0, 1, 0, 3), {P2, P1, F3, F2}},
{"fcmp.nge.s0", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}},
{"fcmp.nge", f2, OpRaRbTaSf (4, 1, 0, 0, 0), {P2, P1, F3, F2}, PSEUDO},
{"fcmp.nge.s1", f2, OpRaRbTaSf (4, 1, 0, 0, 1), {P2, P1, F3, F2}},
{"fcmp.nge.s2", f2, OpRaRbTaSf (4, 1, 0, 0, 2), {P2, P1, F3, F2}},
{"fcmp.nge.s3", f2, OpRaRbTaSf (4, 1, 0, 0, 3), {P2, P1, F3, F2}},
{"fcmp.ord.s0", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}},
{"fcmp.ord", f2, OpRaRbTaSf (4, 1, 1, 0, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.ord.s1", f2, OpRaRbTaSf (4, 1, 1, 0, 1), {P2, P1, F2, F3}},
{"fcmp.ord.s2", f2, OpRaRbTaSf (4, 1, 1, 0, 2), {P2, P1, F2, F3}},
{"fcmp.ord.s3", f2, OpRaRbTaSf (4, 1, 1, 0, 3), {P2, P1, F2, F3}},
{"fcmp.gt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}},
{"fcmp.gt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P1, P2, F3, F2}, PSEUDO},
{"fcmp.gt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P1, P2, F3, F2}},
{"fcmp.gt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P1, P2, F3, F2}},
{"fcmp.gt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P1, P2, F3, F2}},
{"fcmp.ge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}},
{"fcmp.ge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P1, P2, F3, F2}, PSEUDO},
{"fcmp.ge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P1, P2, F3, F2}},
{"fcmp.ge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P1, P2, F3, F2}},
{"fcmp.ge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P1, P2, F3, F2}},
{"fcmp.neq.unc.s0", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}},
{"fcmp.neq.unc", f2, OpRaRbTaSf (4, 0, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.neq.unc.s1", f2, OpRaRbTaSf (4, 0, 0, 1, 1), {P2, P1, F2, F3}},
{"fcmp.neq.unc.s2", f2, OpRaRbTaSf (4, 0, 0, 1, 2), {P2, P1, F2, F3}},
{"fcmp.neq.unc.s3", f2, OpRaRbTaSf (4, 0, 0, 1, 3), {P2, P1, F2, F3}},
{"fcmp.nlt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}},
{"fcmp.nlt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.nlt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F2, F3}},
{"fcmp.nlt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F2, F3}},
{"fcmp.nlt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F2, F3}},
{"fcmp.nle.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}},
{"fcmp.nle.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.nle.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F2, F3}},
{"fcmp.nle.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F2, F3}},
{"fcmp.nle.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F2, F3}},
{"fcmp.ngt.unc.s0", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}},
{"fcmp.ngt.unc", f2, OpRaRbTaSf (4, 0, 1, 1, 0), {P2, P1, F3, F2}, PSEUDO},
{"fcmp.ngt.unc.s1", f2, OpRaRbTaSf (4, 0, 1, 1, 1), {P2, P1, F3, F2}},
{"fcmp.ngt.unc.s2", f2, OpRaRbTaSf (4, 0, 1, 1, 2), {P2, P1, F3, F2}},
{"fcmp.ngt.unc.s3", f2, OpRaRbTaSf (4, 0, 1, 1, 3), {P2, P1, F3, F2}},
{"fcmp.nge.unc.s0", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}},
{"fcmp.nge.unc", f2, OpRaRbTaSf (4, 1, 0, 1, 0), {P2, P1, F3, F2}, PSEUDO},
{"fcmp.nge.unc.s1", f2, OpRaRbTaSf (4, 1, 0, 1, 1), {P2, P1, F3, F2}},
{"fcmp.nge.unc.s2", f2, OpRaRbTaSf (4, 1, 0, 1, 2), {P2, P1, F3, F2}},
{"fcmp.nge.unc.s3", f2, OpRaRbTaSf (4, 1, 0, 1, 3), {P2, P1, F3, F2}},
{"fcmp.ord.unc.s0", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}},
{"fcmp.ord.unc", f2, OpRaRbTaSf (4, 1, 1, 1, 0), {P2, P1, F2, F3}, PSEUDO},
{"fcmp.ord.unc.s1", f2, OpRaRbTaSf (4, 1, 1, 1, 1), {P2, P1, F2, F3}},
{"fcmp.ord.unc.s2", f2, OpRaRbTaSf (4, 1, 1, 1, 2), {P2, P1, F2, F3}},
{"fcmp.ord.unc.s3", f2, OpRaRbTaSf (4, 1, 1, 1, 3), {P2, P1, F2, F3}},
{"fclass.m", f2, OpTa (5, 0), {P1, P2, F2, IMMU9}},
{"fclass.nm", f2, OpTa (5, 0), {P2, P1, F2, IMMU9}, PSEUDO},
{"fclass.m.unc", f2, OpTa (5, 1), {P1, P2, F2, IMMU9}},
{"fclass.nm.unc", f2, OpTa (5, 1), {P2, P1, F2, IMMU9}, PSEUDO},
/* note: fnorm and fcvt.xuf have identical encodings! */
{"fnorm.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fnorm", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s0", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf", f, OpXaSfF2F4 (0x8, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s1", f, OpXaSfF2F4 (0x8, 0, 1, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s2", f, OpXaSfF2F4 (0x8, 0, 2, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s3", f, OpXaSfF2F4 (0x8, 0, 3, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s.s0", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s", f, OpXaSfF2F4 (0x8, 1, 0, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s.s1", f, OpXaSfF2F4 (0x8, 1, 1, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s.s2", f, OpXaSfF2F4 (0x8, 1, 2, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.s.s3", f, OpXaSfF2F4 (0x8, 1, 3, 0, 1), {F1, F3}, PSEUDO},
{"fadd.s0", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fadd", f, OpXaSfF4 (0x8, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s1", f, OpXaSfF4 (0x8, 0, 1, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s2", f, OpXaSfF4 (0x8, 0, 2, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s3", f, OpXaSfF4 (0x8, 0, 3, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s.s0", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s", f, OpXaSfF4 (0x8, 1, 0, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s.s1", f, OpXaSfF4 (0x8, 1, 1, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s.s2", f, OpXaSfF4 (0x8, 1, 2, 1), {F1, F3, F2}, PSEUDO},
{"fadd.s.s3", f, OpXaSfF4 (0x8, 1, 3, 1), {F1, F3, F2}, PSEUDO},
{"fmpy.s0", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fmpy", f, OpXaSfF2 (0x8, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s1", f, OpXaSfF2 (0x8, 0, 1, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s2", f, OpXaSfF2 (0x8, 0, 2, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s3", f, OpXaSfF2 (0x8, 0, 3, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s.s0", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s", f, OpXaSfF2 (0x8, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s.s1", f, OpXaSfF2 (0x8, 1, 1, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s.s2", f, OpXaSfF2 (0x8, 1, 2, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.s.s3", f, OpXaSfF2 (0x8, 1, 3, 0), {F1, F3, F4}, PSEUDO},
{"fma.s0", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}},
{"fma", f, OpXaSf (0x8, 0, 0), {F1, F3, F4, F2}, PSEUDO},
{"fma.s1", f, OpXaSf (0x8, 0, 1), {F1, F3, F4, F2}},
{"fma.s2", f, OpXaSf (0x8, 0, 2), {F1, F3, F4, F2}},
{"fma.s3", f, OpXaSf (0x8, 0, 3), {F1, F3, F4, F2}},
{"fma.s.s0", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}},
{"fma.s", f, OpXaSf (0x8, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"fma.s.s1", f, OpXaSf (0x8, 1, 1), {F1, F3, F4, F2}},
{"fma.s.s2", f, OpXaSf (0x8, 1, 2), {F1, F3, F4, F2}},
{"fma.s.s3", f, OpXaSf (0x8, 1, 3), {F1, F3, F4, F2}},
{"fnorm.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO},
{"fnorm.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.d.s0", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.d", f, OpXaSfF2F4 (0x9, 0, 0, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.d.s1", f, OpXaSfF2F4 (0x9, 0, 1, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.d.s2", f, OpXaSfF2F4 (0x9, 0, 2, 0, 1), {F1, F3}, PSEUDO},
{"fcvt.xuf.d.s3", f, OpXaSfF2F4 (0x9, 0, 3, 0, 1), {F1, F3}, PSEUDO},
{"fadd.d.s0", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fadd.d", f, OpXaSfF4 (0x9, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fadd.d.s1", f, OpXaSfF4 (0x9, 0, 1, 1), {F1, F3, F2}, PSEUDO},
{"fadd.d.s2", f, OpXaSfF4 (0x9, 0, 2, 1), {F1, F3, F2}, PSEUDO},
{"fadd.d.s3", f, OpXaSfF4 (0x9, 0, 3, 1), {F1, F3, F2}, PSEUDO},
{"fmpy.d.s0", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.d", f, OpXaSfF2 (0x9, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.d.s1", f, OpXaSfF2 (0x9, 0, 1, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.d.s2", f, OpXaSfF2 (0x9, 0, 2, 0), {F1, F3, F4}, PSEUDO},
{"fmpy.d.s3", f, OpXaSfF2 (0x9, 0, 3, 0), {F1, F3, F4}, PSEUDO},
{"fma.d.s0", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}},
{"fma.d", f, OpXaSf (0x9, 0, 0), {F1, F3, F4, F2}, PSEUDO},
{"fma.d.s1", f, OpXaSf (0x9, 0, 1), {F1, F3, F4, F2}},
{"fma.d.s2", f, OpXaSf (0x9, 0, 2), {F1, F3, F4, F2}},
{"fma.d.s3", f, OpXaSf (0x9, 0, 3), {F1, F3, F4, F2}},
{"fpmpy.s0", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fpmpy", f, OpXaSfF2 (0x9, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fpmpy.s1", f, OpXaSfF2 (0x9, 1, 1, 0), {F1, F3, F4}, PSEUDO},
{"fpmpy.s2", f, OpXaSfF2 (0x9, 1, 2, 0), {F1, F3, F4}, PSEUDO},
{"fpmpy.s3", f, OpXaSfF2 (0x9, 1, 3, 0), {F1, F3, F4}, PSEUDO},
{"fpma.s0", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}},
{"fpma", f, OpXaSf (0x9, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"fpma.s1", f, OpXaSf (0x9, 1, 1), {F1, F3, F4, F2}},
{"fpma.s2", f, OpXaSf (0x9, 1, 2), {F1, F3, F4, F2}},
{"fpma.s3", f, OpXaSf (0x9, 1, 3), {F1, F3, F4, F2}},
{"fsub.s0", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fsub", f, OpXaSfF4 (0xa, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s1", f, OpXaSfF4 (0xa, 0, 1, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s2", f, OpXaSfF4 (0xa, 0, 2, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s3", f, OpXaSfF4 (0xa, 0, 3, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s.s0", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s", f, OpXaSfF4 (0xa, 1, 0, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s.s1", f, OpXaSfF4 (0xa, 1, 1, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s.s2", f, OpXaSfF4 (0xa, 1, 2, 1), {F1, F3, F2}, PSEUDO},
{"fsub.s.s3", f, OpXaSfF4 (0xa, 1, 3, 1), {F1, F3, F2}, PSEUDO},
{"fms.s0", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}},
{"fms", f, OpXaSf (0xa, 0, 0), {F1, F3, F4, F2}, PSEUDO},
{"fms.s1", f, OpXaSf (0xa, 0, 1), {F1, F3, F4, F2}},
{"fms.s2", f, OpXaSf (0xa, 0, 2), {F1, F3, F4, F2}},
{"fms.s3", f, OpXaSf (0xa, 0, 3), {F1, F3, F4, F2}},
{"fms.s.s0", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}},
{"fms.s", f, OpXaSf (0xa, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"fms.s.s1", f, OpXaSf (0xa, 1, 1), {F1, F3, F4, F2}},
{"fms.s.s2", f, OpXaSf (0xa, 1, 2), {F1, F3, F4, F2}},
{"fms.s.s3", f, OpXaSf (0xa, 1, 3), {F1, F3, F4, F2}},
{"fsub.d.s0", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fsub.d", f, OpXaSfF4 (0xb, 0, 0, 1), {F1, F3, F2}, PSEUDO},
{"fsub.d.s1", f, OpXaSfF4 (0xb, 0, 1, 1), {F1, F3, F2}, PSEUDO},
{"fsub.d.s2", f, OpXaSfF4 (0xb, 0, 2, 1), {F1, F3, F2}, PSEUDO},
{"fsub.d.s3", f, OpXaSfF4 (0xb, 0, 3, 1), {F1, F3, F2}, PSEUDO},
{"fms.d.s0", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}},
{"fms.d", f, OpXaSf (0xb, 0, 0), {F1, F3, F4, F2}, PSEUDO},
{"fms.d.s1", f, OpXaSf (0xb, 0, 1), {F1, F3, F4, F2}},
{"fms.d.s2", f, OpXaSf (0xb, 0, 2), {F1, F3, F4, F2}},
{"fms.d.s3", f, OpXaSf (0xb, 0, 3), {F1, F3, F4, F2}},
{"fpms.s0", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}},
{"fpms", f, OpXaSf (0xb, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"fpms.s1", f, OpXaSf (0xb, 1, 1), {F1, F3, F4, F2}},
{"fpms.s2", f, OpXaSf (0xb, 1, 2), {F1, F3, F4, F2}},
{"fpms.s3", f, OpXaSf (0xb, 1, 3), {F1, F3, F4, F2}},
{"fnmpy.s0", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy", f, OpXaSfF2 (0xc, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s1", f, OpXaSfF2 (0xc, 0, 1, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s2", f, OpXaSfF2 (0xc, 0, 2, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s3", f, OpXaSfF2 (0xc, 0, 3, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s.s0", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s", f, OpXaSfF2 (0xc, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s.s1", f, OpXaSfF2 (0xc, 1, 1, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s.s2", f, OpXaSfF2 (0xc, 1, 2, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.s.s3", f, OpXaSfF2 (0xc, 1, 3, 0), {F1, F3, F4}, PSEUDO},
{"fnma.s0", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}},
{"fnma", f, OpXaSf (0xc, 0, 0), {F1, F3, F4, F2}, PSEUDO},
{"fnma.s1", f, OpXaSf (0xc, 0, 1), {F1, F3, F4, F2}},
{"fnma.s2", f, OpXaSf (0xc, 0, 2), {F1, F3, F4, F2}},
{"fnma.s3", f, OpXaSf (0xc, 0, 3), {F1, F3, F4, F2}},
{"fnma.s.s0", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}},
{"fnma.s", f, OpXaSf (0xc, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"fnma.s.s1", f, OpXaSf (0xc, 1, 1), {F1, F3, F4, F2}},
{"fnma.s.s2", f, OpXaSf (0xc, 1, 2), {F1, F3, F4, F2}},
{"fnma.s.s3", f, OpXaSf (0xc, 1, 3), {F1, F3, F4, F2}},
{"fnmpy.d.s0", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.d", f, OpXaSfF2 (0xd, 0, 0, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.d.s1", f, OpXaSfF2 (0xd, 0, 1, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.d.s2", f, OpXaSfF2 (0xd, 0, 2, 0), {F1, F3, F4}, PSEUDO},
{"fnmpy.d.s3", f, OpXaSfF2 (0xd, 0, 3, 0), {F1, F3, F4}, PSEUDO},
{"fnma.d.s0", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}},
{"fnma.d", f, OpXaSf (0xd, 0, 0), {F1, F3, F4, F2}, PSEUDO},
{"fnma.d.s1", f, OpXaSf (0xd, 0, 1), {F1, F3, F4, F2}},
{"fnma.d.s2", f, OpXaSf (0xd, 0, 2), {F1, F3, F4, F2}},
{"fnma.d.s3", f, OpXaSf (0xd, 0, 3), {F1, F3, F4, F2}},
{"fpnmpy.s0", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fpnmpy", f, OpXaSfF2 (0xd, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"fpnmpy.s1", f, OpXaSfF2 (0xd, 1, 1, 0), {F1, F3, F4}, PSEUDO},
{"fpnmpy.s2", f, OpXaSfF2 (0xd, 1, 2, 0), {F1, F3, F4}, PSEUDO},
{"fpnmpy.s3", f, OpXaSfF2 (0xd, 1, 3, 0), {F1, F3, F4}, PSEUDO},
{"fpnma.s0", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}},
{"fpnma", f, OpXaSf (0xd, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"fpnma.s1", f, OpXaSf (0xd, 1, 1), {F1, F3, F4, F2}},
{"fpnma.s2", f, OpXaSf (0xd, 1, 2), {F1, F3, F4, F2}},
{"fpnma.s3", f, OpXaSf (0xd, 1, 3), {F1, F3, F4, F2}},
{"xmpy.l", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"xmpy.lu", f, OpXaX2F2 (0xe, 1, 0, 0), {F1, F3, F4}, PSEUDO},
{"xmpy.h", f, OpXaX2F2 (0xe, 1, 3, 0), {F1, F3, F4}, PSEUDO},
{"xmpy.hu", f, OpXaX2F2 (0xe, 1, 2, 0), {F1, F3, F4}, PSEUDO},
{"xma.l", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}},
{"xma.lu", f, OpXaX2 (0xe, 1, 0), {F1, F3, F4, F2}, PSEUDO},
{"xma.h", f, OpXaX2 (0xe, 1, 3), {F1, F3, F4, F2}},
{"xma.hu", f, OpXaX2 (0xe, 1, 2), {F1, F3, F4, F2}},
{"fselect", f, OpXa (0xe, 0), {F1, F3, F4, F2}},
{0}
};
#undef f0
#undef f
#undef f2
#undef bF2
#undef bF4
#undef bQ
#undef bRa
#undef bRb
#undef bSf
#undef bTa
#undef bXa
#undef bXb
#undef bX2
#undef bX6
#undef mF2
#undef mF4
#undef mQ
#undef mRa
#undef mRb
#undef mSf
#undef mTa
#undef mXa
#undef mXb
#undef mX2
#undef mX6
#undef OpXa
#undef OpXaSf
#undef OpXaSfF2
#undef OpXaSfF4
#undef OpXaSfF2F4
#undef OpXaX2
#undef OpRaRbTaSf
#undef OpTa
#undef OpXbQSf
#undef OpXbX6
#undef OpXbX6F2
#undef OpXbX6Sf

296
contrib/binutils/opcodes/ia64-opc-i.c Normal file
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@ -0,0 +1,296 @@
/* ia64-opc-i.c -- IA-64 `I' opcode table.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
#define I0 IA64_TYPE_I, 0
#define I IA64_TYPE_I, 1
#define I2 IA64_TYPE_I, 2
/* instruction bit fields: */
#define bC(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bIh(x) (((ia64_insn) ((x) & 0x1)) << 23)
#define bTa(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bTag13(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bTb(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
#define bVe(x) (((ia64_insn) ((x) & 0x1)) << 32)
#define bWh(x) (((ia64_insn) ((x) & 0x3)) << 20)
#define bX(x) (((ia64_insn) ((x) & 0x1)) << 33)
#define bXb(x) (((ia64_insn) ((x) & 0x1)) << 22)
#define bX2(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2a(x) (((ia64_insn) ((x) & 0x3)) << 34)
#define bX2b(x) (((ia64_insn) ((x) & 0x3)) << 28)
#define bX2c(x) (((ia64_insn) ((x) & 0x3)) << 30)
#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define bYa(x) (((ia64_insn) ((x) & 0x1)) << 13)
#define bYb(x) (((ia64_insn) ((x) & 0x1)) << 26)
#define bZa(x) (((ia64_insn) ((x) & 0x1)) << 36)
#define bZb(x) (((ia64_insn) ((x) & 0x1)) << 33)
/* instruction bit masks: */
#define mC bC (-1)
#define mIh bIh (-1)
#define mTa bTa (-1)
#define mTag13 bTag13 (-1)
#define mTb bTb (-1)
#define mVc bVc (-1)
#define mVe bVe (-1)
#define mWh bWh (-1)
#define mX bX (-1)
#define mXb bXb (-1)
#define mX2 bX2 (-1)
#define mX2a bX2a (-1)
#define mX2b bX2b (-1)
#define mX2c bX2c (-1)
#define mX3 bX3 (-1)
#define mX6 bX6 (-1)
#define mYa bYa (-1)
#define mYb bYb (-1)
#define mZa bZa (-1)
#define mZb bZb (-1)
#define OpZaZbVeX2aX2b(a,b,c,d,e,f) \
(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f)), \
(mOp | mZa | mZb | mVe | mX2a | mX2b)
#define OpZaZbVeX2aX2bX2c(a,b,c,d,e,f,g) \
(bOp (a) | bZa (b) | bZb (c) | bVe (d) | bX2a (e) | bX2b (f) | bX2c (g)), \
(mOp | mZa | mZb | mVe | mX2a | mX2b | mX2c)
#define OpX2X(a,b,c) (bOp (a) | bX2 (b) | bX (c)), (mOp | mX2 | mX)
#define OpX2XYa(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYa (d)), \
(mOp | mX2 | mX | mYa)
#define OpX2XYb(a,b,c,d) (bOp (a) | bX2 (b) | bX (c) | bYb (d)), \
(mOp | mX2 | mX | mYb)
#define OpX2TaTbYaC(a,b,c,d,e,f) \
(bOp (a) | bX2 (b) | bTa (c) | bTb (d) | bYa (e) | bC (f)), \
(mOp | mX2 | mTa | mTb | mYa | mC)
#define OpX3(a,b) (bOp (a) | bX3 (b)), (mOp | mX3)
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
(mOp | mX3 | mX6)
#define OpX3XbIhWh(a,b,c,d,e) \
(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e)), \
(mOp | mX3 | mXb | mIh | mWh)
#define OpX3XbIhWhTag13(a,b,c,d,e,f) \
(bOp (a) | bX3 (b) | bXb (c) | bIh (d) | bWh (e) | bTag13 (f)), \
(mOp | mX3 | mXb | mIh | mWh | mTag13)
struct ia64_opcode ia64_opcodes_i[] =
{
/* I-type instruction encodings (sorted according to major opcode) */
{"break.i", I0, OpX3X6 (0, 0, 0x00), {IMMU21}, X_IN_MLX},
{"nop.i", I0, OpX3X6 (0, 0, 0x01), {IMMU21}, X_IN_MLX},
{"chk.s.i", I0, OpX3 (0, 1), {R2, TGT25b}},
{"mov", I, OpX3XbIhWhTag13 (0, 7, 0, 0, 1, 0), {B1, R2}, PSEUDO},
#define MOV(a,b,c,d) \
I, OpX3XbIhWh (0, a, b, c, d), {B1, R2, TAG13b}
{"mov.sptk", MOV (7, 0, 0, 0)},
{"mov.sptk.imp", MOV (7, 0, 1, 0)},
{"mov", MOV (7, 0, 0, 1)},
{"mov.imp", MOV (7, 0, 1, 1)},
{"mov.dptk", MOV (7, 0, 0, 2)},
{"mov.dptk.imp", MOV (7, 0, 1, 2)},
{"mov.ret.sptk", MOV (7, 1, 0, 0)},
{"mov.ret.sptk.imp", MOV (7, 1, 1, 0)},
{"mov.ret", MOV (7, 1, 0, 1)},
{"mov.ret.imp", MOV (7, 1, 1, 1)},
{"mov.ret.dptk", MOV (7, 1, 0, 2)},
{"mov.ret.dptk.imp", MOV (7, 1, 1, 2)},
#undef MOV
{"mov", I, OpX3X6 (0, 0, 0x31), {R1, B2}},
{"mov", I, OpX3 (0, 3), {PR, R2, IMM17}},
{"mov", I, OpX3 (0, 2), {PR_ROT, IMM44}},
{"mov", I, OpX3X6 (0, 0, 0x30), {R1, IP}},
{"mov", I, OpX3X6 (0, 0, 0x33), {R1, PR}},
{"mov.i", I, OpX3X6 (0, 0, 0x2a), {AR3, R2}},
{"mov.i", I, OpX3X6 (0, 0, 0x0a), {AR3, IMM8}},
{"mov.i", I, OpX3X6 (0, 0, 0x32), {R1, AR3}},
{"zxt1", I, OpX3X6 (0, 0, 0x10), {R1, R3}},
{"zxt2", I, OpX3X6 (0, 0, 0x11), {R1, R3}},
{"zxt4", I, OpX3X6 (0, 0, 0x12), {R1, R3}},
{"sxt1", I, OpX3X6 (0, 0, 0x14), {R1, R3}},
{"sxt2", I, OpX3X6 (0, 0, 0x15), {R1, R3}},
{"sxt4", I, OpX3X6 (0, 0, 0x16), {R1, R3}},
{"czx1.l", I, OpX3X6 (0, 0, 0x18), {R1, R3}},
{"czx2.l", I, OpX3X6 (0, 0, 0x19), {R1, R3}},
{"czx1.r", I, OpX3X6 (0, 0, 0x1c), {R1, R3}},
{"czx2.r", I, OpX3X6 (0, 0, 0x1d), {R1, R3}},
{"dep", I, Op (4), {R1, R2, R3, CPOS6c, LEN4}},
{"shrp", I, OpX2X (5, 3, 0), {R1, R2, R3, CNT6}},
{"shr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6},
PSEUDO | LEN_EQ_64MCNT},
{"extr.u", I, OpX2XYa (5, 1, 0, 0), {R1, R3, POS6, LEN6}},
{"shr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6},
PSEUDO | LEN_EQ_64MCNT},
{"extr", I, OpX2XYa (5, 1, 0, 1), {R1, R3, POS6, LEN6}},
{"shl", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a},
PSEUDO | LEN_EQ_64MCNT},
{"dep.z", I, OpX2XYb (5, 1, 1, 0), {R1, R2, CPOS6a, LEN6}},
{"dep.z", I, OpX2XYb (5, 1, 1, 1), {R1, IMM8, CPOS6a, LEN6}},
{"dep", I, OpX2X (5, 3, 1), {R1, IMM1, R3, CPOS6b, LEN6}},
#define TBIT(a,b,c,d) \
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3, POS6}
#define TBITCM(a,b,c,d) \
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3, POS6}, PSEUDO
{"tbit.z", TBIT (0, 0, 0, 0)},
{"tbit.nz", TBITCM (0, 0, 0, 0)},
{"tbit.z.unc", TBIT (0, 0, 0, 1)},
{"tbit.nz.unc", TBITCM (0, 0, 0, 1)},
{"tbit.z.and", TBIT (0, 1, 0, 0)},
{"tbit.nz.andcm", TBITCM (0, 1, 0, 0)},
{"tbit.nz.and", TBIT (0, 1, 0, 1)},
{"tbit.z.andcm", TBITCM (0, 1, 0, 1)},
{"tbit.z.or", TBIT (1, 0, 0, 0)},
{"tbit.nz.orcm", TBITCM (1, 0, 0, 0)},
{"tbit.nz.or", TBIT (1, 0, 0, 1)},
{"tbit.z.orcm", TBITCM (1, 0, 0, 1)},
{"tbit.z.or.andcm", TBIT (1, 1, 0, 0)},
{"tbit.nz.and.orcm", TBITCM (1, 1, 0, 0)},
{"tbit.nz.or.andcm", TBIT (1, 1, 0, 1)},
{"tbit.z.and.orcm", TBITCM (1, 1, 0, 1)},
#undef TBIT
#define TNAT(a,b,c,d) \
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P1, P2, R3}
#define TNATCM(a,b,c,d) \
I2, OpX2TaTbYaC (5, 0, a, b, c, d), {P2, P1, R3}, PSEUDO
{"tnat.z", TNAT (0, 0, 1, 0)},
{"tnat.nz", TNATCM (0, 0, 1, 0)},
{"tnat.z.unc", TNAT (0, 0, 1, 1)},
{"tnat.nz.unc", TNATCM (0, 0, 1, 1)},
{"tnat.z.and", TNAT (0, 1, 1, 0)},
{"tnat.nz.andcm", TNATCM (0, 1, 1, 0)},
{"tnat.nz.and", TNAT (0, 1, 1, 1)},
{"tnat.z.andcm", TNATCM (0, 1, 1, 1)},
{"tnat.z.or", TNAT (1, 0, 1, 0)},
{"tnat.nz.orcm", TNATCM (1, 0, 1, 0)},
{"tnat.nz.or", TNAT (1, 0, 1, 1)},
{"tnat.z.orcm", TNATCM (1, 0, 1, 1)},
{"tnat.z.or.andcm", TNAT (1, 1, 1, 0)},
{"tnat.nz.and.orcm", TNATCM (1, 1, 1, 0)},
{"tnat.nz.or.andcm", TNAT (1, 1, 1, 1)},
{"tnat.z.and.orcm", TNATCM (1, 1, 1, 1)},
#undef TNAT
{"pmpyshr2", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 3), {R1, R2, R3, CNT2c}},
{"pmpyshr2.u", I, OpZaZbVeX2aX2b (7, 0, 1, 0, 0, 1), {R1, R2, R3, CNT2c}},
{"pmpy2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 1, 3), {R1, R2, R3}},
{"pmpy2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 3), {R1, R2, R3}},
{"mix1.r", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 2), {R1, R2, R3}},
{"mix2.r", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 2), {R1, R2, R3}},
{"mix4.r", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 2), {R1, R2, R3}},
{"mix1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 2), {R1, R2, R3}},
{"mix2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 2), {R1, R2, R3}},
{"mix4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 2), {R1, R2, R3}},
{"pack2.uss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 0), {R1, R2, R3}},
{"pack2.sss", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 0), {R1, R2, R3}},
{"pack4.sss", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 0), {R1, R2, R3}},
{"unpack1.h", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 0, 1), {R1, R2, R3}},
{"unpack2.h", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 0, 1), {R1, R2, R3}},
{"unpack4.h", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 0, 1), {R1, R2, R3}},
{"unpack1.l", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 2, 1), {R1, R2, R3}},
{"unpack2.l", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 2, 1), {R1, R2, R3}},
{"unpack4.l", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 2, 2, 1), {R1, R2, R3}},
{"pmin1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 0), {R1, R2, R3}},
{"pmax1.u", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 1, 1), {R1, R2, R3}},
{"pmin2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 0), {R1, R2, R3}},
{"pmax2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 2, 3, 1), {R1, R2, R3}},
{"psad1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 2, 3, 2), {R1, R2, R3}},
{"mux1", I, OpZaZbVeX2aX2bX2c (7, 0, 0, 0, 3, 2, 2), {R1, R2, MBTYPE4}},
{"mux2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 2, 2), {R1, R2, MHTYPE8}},
{"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 2, 0), {R1, R3, R2}},
{"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 2, 0), {R1, R3, R2}},
{"shr", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 2, 0), {R1, R3, R2}},
{"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 0), {R1, R3, R2}},
{"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 0), {R1, R3, R2}},
{"shr.u", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 0), {R1, R3, R2}},
{"pshr2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 3, 0), {R1, R3, CNT5}},
{"pshr4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 3, 0), {R1, R3, CNT5}},
{"pshr2.u", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 0), {R1, R3, CNT5}},
{"pshr4.u", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 1, 1, 0), {R1, R3, CNT5}},
{"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 0, 0, 1), {R1, R2, R3}},
{"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 0, 0, 1), {R1, R2, R3}},
{"shl", I, OpZaZbVeX2aX2bX2c (7, 1, 1, 0, 0, 0, 1), {R1, R2, R3}},
{"pshl2", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 3, 1, 1), {R1, R2, CCNT5}},
{"pshl4", I, OpZaZbVeX2aX2bX2c (7, 1, 0, 0, 3, 1, 1), {R1, R2, CCNT5}},
{"popcnt", I, OpZaZbVeX2aX2bX2c (7, 0, 1, 0, 1, 1, 2), {R1, R3}},
{0}
};
#undef I0
#undef I
#undef I2
#undef L
#undef bC
#undef bIh
#undef bTa
#undef bTag13
#undef bTb
#undef bVc
#undef bVe
#undef bWh
#undef bX
#undef bXb
#undef bX2
#undef bX2a
#undef bX2b
#undef bX2c
#undef bX3
#undef bX6
#undef bY
#undef bZa
#undef bZb
#undef mC
#undef mIh
#undef mTa
#undef mTag13
#undef mTb
#undef mVc
#undef mVe
#undef mWh
#undef mX
#undef mXb
#undef mX2
#undef mX2a
#undef mX2b
#undef mX2c
#undef mX3
#undef mX6
#undef mY
#undef mZa
#undef mZb
#undef OpZaZbVeX2aX2b
#undef OpZaZbVeX2aX2bX2c
#undef OpX2X
#undef OpX2XYa
#undef OpX2XYb
#undef OpX2TaTbYaC
#undef OpX3
#undef OpX3X6
#undef OpX3XbIhWh
#undef OpX3XbIhWhTag13

1060
contrib/binutils/opcodes/ia64-opc-m.c Normal file
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/* ia64-opc-x.c -- IA-64 `X' opcode table.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by Timothy Wall <twall@cygnus.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ia64-opc.h"
/* identify the specific X-unit type */
#define X0 IA64_TYPE_X, 0
#define X IA64_TYPE_X, 1
/* instruction bit fields: */
#define bBtype(x) (((ia64_insn) ((x) & 0x7)) << 6)
#define bD(x) (((ia64_insn) ((x) & 0x1)) << 35)
#define bPa(x) (((ia64_insn) ((x) & 0x1)) << 12)
#define bPr(x) (((ia64_insn) ((x) & 0x3f)) << 0)
#define bVc(x) (((ia64_insn) ((x) & 0x1)) << 20)
#define bWha(x) (((ia64_insn) ((x) & 0x3)) << 33)
#define bX3(x) (((ia64_insn) ((x) & 0x7)) << 33)
#define bX6(x) (((ia64_insn) ((x) & 0x3f)) << 27)
#define mBtype bBtype (-1)
#define mD bD (-1)
#define mPa bPa (-1)
#define mPr bPr (-1)
#define mVc bVc (-1)
#define mWha bWha (-1)
#define mX3 bX3 (-1)
#define mX6 bX6 (-1)
#define OpX3X6(a,b,c) (bOp (a) | bX3 (b) | bX6(c)), \
(mOp | mX3 | mX6)
#define OpVc(a,b) (bOp (a) | bVc (b)), (mOp | mVc)
#define OpPaWhaD(a,b,c,d) \
(bOp (a) | bPa (b) | bWha (c) | bD (d)), (mOp | mPa | mWha | mD)
#define OpBtypePaWhaD(a,b,c,d,e) \
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e)), \
(mOp | mBtype | mPa | mWha | mD)
#define OpBtypePaWhaDPr(a,b,c,d,e,f) \
(bOp (a) | bBtype (b) | bPa (c) | bWha (d) | bD (e) | bPr (f)), \
(mOp | mBtype | mPa | mWha | mD | mPr)
struct ia64_opcode ia64_opcodes_x[] =
{
{"break.x", X0, OpX3X6 (0, 0, 0x00), {IMMU62}},
{"nop.x", X0, OpX3X6 (0, 0, 0x01), {IMMU62}},
{"movl", X, OpVc (6, 0), {R1, IMMU64}},
#define BRL(a,b) \
X0, OpBtypePaWhaDPr (0xC, 0, a, 0, b, 0), {TGT64}, 0
{"brl.few", BRL (0, 0) | PSEUDO},
{"brl", BRL (0, 0) | PSEUDO},
{"brl.few.clr", BRL (0, 1) | PSEUDO},
{"brl.clr", BRL (0, 1) | PSEUDO},
{"brl.many", BRL (1, 0) | PSEUDO},
{"brl.many.clr", BRL (1, 1) | PSEUDO},
#undef BRL
#define BRL(a,b,c) \
X0, OpBtypePaWhaD (0xC, 0, a, b, c), {TGT64}, 0
{"brl.cond.sptk.few", BRL (0, 0, 0)},
{"brl.cond.sptk", BRL (0, 0, 0) | PSEUDO},
{"brl.cond.sptk.few.clr", BRL (0, 0, 1)},
{"brl.cond.sptk.clr", BRL (0, 0, 1) | PSEUDO},
{"brl.cond.spnt.few", BRL (0, 1, 0)},
{"brl.cond.spnt", BRL (0, 1, 0) | PSEUDO},
{"brl.cond.spnt.few.clr", BRL (0, 1, 1)},
{"brl.cond.spnt.clr", BRL (0, 1, 1) | PSEUDO},
{"brl.cond.dptk.few", BRL (0, 2, 0)},
{"brl.cond.dptk", BRL (0, 2, 0) | PSEUDO},
{"brl.cond.dptk.few.clr", BRL (0, 2, 1)},
{"brl.cond.dptk.clr", BRL (0, 2, 1) | PSEUDO},
{"brl.cond.dpnt.few", BRL (0, 3, 0)},
{"brl.cond.dpnt", BRL (0, 3, 0) | PSEUDO},
{"brl.cond.dpnt.few.clr", BRL (0, 3, 1)},
{"brl.cond.dpnt.clr", BRL (0, 3, 1) | PSEUDO},
{"brl.cond.sptk.many", BRL (1, 0, 0)},
{"brl.cond.sptk.many.clr", BRL (1, 0, 1)},
{"brl.cond.spnt.many", BRL (1, 1, 0)},
{"brl.cond.spnt.many.clr", BRL (1, 1, 1)},
{"brl.cond.dptk.many", BRL (1, 2, 0)},
{"brl.cond.dptk.many.clr", BRL (1, 2, 1)},
{"brl.cond.dpnt.many", BRL (1, 3, 0)},
{"brl.cond.dpnt.many.clr", BRL (1, 3, 1)},
{"brl.sptk.few", BRL (0, 0, 0)},
{"brl.sptk", BRL (0, 0, 0) | PSEUDO},
{"brl.sptk.few.clr", BRL (0, 0, 1)},
{"brl.sptk.clr", BRL (0, 0, 1) | PSEUDO},
{"brl.spnt.few", BRL (0, 1, 0)},
{"brl.spnt", BRL (0, 1, 0) | PSEUDO},
{"brl.spnt.few.clr", BRL (0, 1, 1)},
{"brl.spnt.clr", BRL (0, 1, 1) | PSEUDO},
{"brl.dptk.few", BRL (0, 2, 0)},
{"brl.dptk", BRL (0, 2, 0) | PSEUDO},
{"brl.dptk.few.clr", BRL (0, 2, 1)},
{"brl.dptk.clr", BRL (0, 2, 1) | PSEUDO},
{"brl.dpnt.few", BRL (0, 3, 0)},
{"brl.dpnt", BRL (0, 3, 0) | PSEUDO},
{"brl.dpnt.few.clr", BRL (0, 3, 1)},
{"brl.dpnt.clr", BRL (0, 3, 1) | PSEUDO},
{"brl.sptk.many", BRL (1, 0, 0)},
{"brl.sptk.many.clr", BRL (1, 0, 1)},
{"brl.spnt.many", BRL (1, 1, 0)},
{"brl.spnt.many.clr", BRL (1, 1, 1)},
{"brl.dptk.many", BRL (1, 2, 0)},
{"brl.dptk.many.clr", BRL (1, 2, 1)},
{"brl.dpnt.many", BRL (1, 3, 0)},
{"brl.dpnt.many.clr", BRL (1, 3, 1)},
#undef BRL
#define BRL(a,b,c) X, OpPaWhaD (0xD, a, b, c), {B1, TGT64}, 0
{"brl.call.sptk.few", BRL (0, 0, 0)},
{"brl.call.sptk", BRL (0, 0, 0) | PSEUDO},
{"brl.call.sptk.few.clr", BRL (0, 0, 1)},
{"brl.call.sptk.clr", BRL (0, 0, 1) | PSEUDO},
{"brl.call.spnt.few", BRL (0, 1, 0)},
{"brl.call.spnt", BRL (0, 1, 0) | PSEUDO},
{"brl.call.spnt.few.clr", BRL (0, 1, 1)},
{"brl.call.spnt.clr", BRL (0, 1, 1) | PSEUDO},
{"brl.call.dptk.few", BRL (0, 2, 0)},
{"brl.call.dptk", BRL (0, 2, 0) | PSEUDO},
{"brl.call.dptk.few.clr", BRL (0, 2, 1)},
{"brl.call.dptk.clr", BRL (0, 2, 1) | PSEUDO},
{"brl.call.dpnt.few", BRL (0, 3, 0)},
{"brl.call.dpnt", BRL (0, 3, 0) | PSEUDO},
{"brl.call.dpnt.few.clr", BRL (0, 3, 1)},
{"brl.call.dpnt.clr", BRL (0, 3, 1) | PSEUDO},
{"brl.call.sptk.many", BRL (1, 0, 0)},
{"brl.call.sptk.many.clr", BRL (1, 0, 1)},
{"brl.call.spnt.many", BRL (1, 1, 0)},
{"brl.call.spnt.many.clr", BRL (1, 1, 1)},
{"brl.call.dptk.many", BRL (1, 2, 0)},
{"brl.call.dptk.many.clr", BRL (1, 2, 1)},
{"brl.call.dpnt.many", BRL (1, 3, 0)},
{"brl.call.dpnt.many.clr", BRL (1, 3, 1)},
#undef BRL
{0}
};
#undef X0
#undef X
#undef bBtype
#undef bD
#undef bPa
#undef bPr
#undef bVc
#undef bWha
#undef bX3
#undef bX6
#undef mBtype
#undef mD
#undef mPa
#undef mPr
#undef mVc
#undef mWha
#undef mX3
#undef mX6
#undef OpX3X6
#undef OpVc
#undef OpPaWhaD
#undef OpBtypePaWhaD
#undef OpBtypePaWhaDPr

748
contrib/binutils/opcodes/ia64-opc.c Normal file
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@ -0,0 +1,748 @@
/* ia64-opc.c -- Functions to access the compacted opcode table
Copyright 1999, 2000 Free Software Foundation, Inc.
Written by Bob Manson of Cygnus Solutions, <manson@cygnus.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#include "ansidecl.h"
#include "libiberty.h"
#include "sysdep.h"
#include "ia64-asmtab.h"
#include "ia64-asmtab.c"
const struct ia64_templ_desc ia64_templ_desc[16] =
{
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" }, /* 0 */
{ 2, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_I }, "MII" },
{ 0, { IA64_UNIT_M, IA64_UNIT_L, IA64_UNIT_X }, "MLX" },
{ 0, { 0, }, "-3-" },
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" }, /* 4 */
{ 1, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_I }, "MMI" },
{ 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_I }, "MFI" },
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_F }, "MMF" },
{ 0, { IA64_UNIT_M, IA64_UNIT_I, IA64_UNIT_B }, "MIB" }, /* 8 */
{ 0, { IA64_UNIT_M, IA64_UNIT_B, IA64_UNIT_B }, "MBB" },
{ 0, { 0, }, "-a-" },
{ 0, { IA64_UNIT_B, IA64_UNIT_B, IA64_UNIT_B }, "BBB" },
{ 0, { IA64_UNIT_M, IA64_UNIT_M, IA64_UNIT_B }, "MMB" }, /* c */
{ 0, { 0, }, "-d-" },
{ 0, { IA64_UNIT_M, IA64_UNIT_F, IA64_UNIT_B }, "MFB" },
{ 0, { 0, }, "-f-" },
};
/* Copy the prefix contained in *PTR (up to a '.' or a NUL) to DEST.
PTR will be adjusted to point to the start of the next portion
of the opcode, or at the NUL character. */
static void
get_opc_prefix (ptr, dest)
const char **ptr;
char *dest;
{
char *c = strchr (*ptr, '.');
if (c != NULL)
{
memcpy (dest, *ptr, c - *ptr);
dest[c - *ptr] = '\0';
*ptr = c + 1;
}
else
{
int l = strlen (*ptr);
memcpy (dest, *ptr, l);
dest[l] = '\0';
*ptr += l;
}
}
/* Find the index of the entry in the string table corresponding to
STR; return -1 if one does not exist. */
static short
find_string_ent (str)
const char *str;
{
short start = 0;
short end = sizeof (ia64_strings) / sizeof (const char *);
short i = (start + end) / 2;
if (strcmp (str, ia64_strings[end - 1]) > 0)
{
return -1;
}
while (start <= end)
{
int c = strcmp (str, ia64_strings[i]);
if (c < 0)
{
end = i - 1;
}
else if (c == 0)
{
return i;
}
else
{
start = i + 1;
}
i = (start + end) / 2;
}
return -1;
}
/* Find the opcode in the main opcode table whose name is STRINGINDEX, or
return -1 if one does not exist. */
static short
find_main_ent (nameindex)
short nameindex;
{
short start = 0;
short end = sizeof (main_table) / sizeof (struct ia64_main_table);
short i = (start + end) / 2;
if (nameindex < main_table[0].name_index
|| nameindex > main_table[end - 1].name_index)
{
return -1;
}
while (start <= end)
{
if (nameindex < main_table[i].name_index)
{
end = i - 1;
}
else if (nameindex == main_table[i].name_index)
{
while (i > 0 && main_table[i - 1].name_index == nameindex)
{
i--;
}
return i;
}
else
{
start = i + 1;
}
i = (start + end) / 2;
}
return -1;
}
/* Find the index of the entry in the completer table that is part of
MAIN_ENT (starting from PREV_COMPLETER) that matches NAME, or
return -1 if one does not exist. */
static short
find_completer (main_ent, prev_completer, name)
short main_ent;
short prev_completer;
const char *name;
{
short name_index = find_string_ent (name);
if (name_index < 0)
{
return -1;
}
if (prev_completer == -1)
{
prev_completer = main_table[main_ent].completers;
}
else
{
prev_completer = completer_table[prev_completer].subentries;
}
while (prev_completer != -1)
{
if (completer_table[prev_completer].name_index == name_index)
{
return prev_completer;
}
prev_completer = completer_table[prev_completer].alternative;
}
return -1;
}
/* Apply the completer referred to by COMPLETER_INDEX to OPCODE, and
return the result. */
static ia64_insn
apply_completer (opcode, completer_index)
ia64_insn opcode;
int completer_index;
{
ia64_insn mask = completer_table[completer_index].mask;
ia64_insn bits = completer_table[completer_index].bits;
int shiftamt = (completer_table[completer_index].offset & 63);
mask = mask << shiftamt;
bits = bits << shiftamt;
opcode = (opcode & ~mask) | bits;
return opcode;
}
/* Extract BITS number of bits starting from OP_POINTER + BITOFFSET in
the dis_table array, and return its value. (BITOFFSET is numbered
starting from MSB to LSB, so a BITOFFSET of 0 indicates the MSB of the
first byte in OP_POINTER.) */
static int
extract_op_bits (op_pointer, bitoffset, bits)
int op_pointer;
int bitoffset;
int bits;
{
int res = 0;
op_pointer += (bitoffset / 8);
if (bitoffset % 8)
{
unsigned int op = dis_table[op_pointer++];
int numb = 8 - (bitoffset % 8);
int mask = (1 << numb) - 1;
int bata = (bits < numb) ? bits : numb;
int delta = numb - bata;
res = (res << bata) | ((op & mask) >> delta);
bitoffset += bata;
bits -= bata;
}
while (bits >= 8)
{
res = (res << 8) | (dis_table[op_pointer++] & 255);
bits -= 8;
}
if (bits > 0)
{
unsigned int op = (dis_table[op_pointer++] & 255);
res = (res << bits) | (op >> (8 - bits));
}
return res;
}
/* Examine the state machine entry at OP_POINTER in the dis_table
array, and extract its values into OPVAL and OP. The length of the
state entry in bits is returned. */
static int
extract_op (op_pointer, opval, op)
int op_pointer;
int *opval;
unsigned int *op;
{
int oplen = 5;
*op = dis_table[op_pointer];
if ((*op) & 0x40)
{
opval[0] = extract_op_bits (op_pointer, oplen, 5);
oplen += 5;
}
switch ((*op) & 0x30)
{
case 0x10:
{
opval[1] = extract_op_bits (op_pointer, oplen, 8);
oplen += 8;
opval[1] += op_pointer;
break;
}
case 0x20:
{
opval[1] = extract_op_bits (op_pointer, oplen, 16);
if (! (opval[1] & 32768))
{
opval[1] += op_pointer;
}
oplen += 16;
break;
}
case 0x30:
{
oplen--;
opval[2] = extract_op_bits (op_pointer, oplen, 12);
oplen += 12;
opval[2] |= 32768;
break;
}
}
if (((*op) & 0x08) && (((*op) & 0x30) != 0x30))
{
opval[2] = extract_op_bits (op_pointer, oplen, 16);
oplen += 16;
if (! (opval[2] & 32768))
{
opval[2] += op_pointer;
}
}
return oplen;
}
/* Returns a non-zero value if the opcode in the main_table list at
PLACE matches OPCODE and is of type TYPE. */
static int
opcode_verify (opcode, place, type)
ia64_insn opcode;
int place;
enum ia64_insn_type type;
{
if (main_table[place].opcode_type != type)
{
return 0;
}
if (main_table[place].flags
& (IA64_OPCODE_F2_EQ_F3 | IA64_OPCODE_LEN_EQ_64MCNT))
{
const struct ia64_operand *o1, *o2;
ia64_insn f2, f3;
if (main_table[place].flags & IA64_OPCODE_F2_EQ_F3)
{
o1 = elf64_ia64_operands + IA64_OPND_F2;
o2 = elf64_ia64_operands + IA64_OPND_F3;
(*o1->extract) (o1, opcode, &f2);
(*o2->extract) (o2, opcode, &f3);
if (f2 != f3)
return 0;
}
else
{
ia64_insn len, count;
/* length must equal 64-count: */
o1 = elf64_ia64_operands + IA64_OPND_LEN6;
o2 = elf64_ia64_operands + main_table[place].operands[2];
(*o1->extract) (o1, opcode, &len);
(*o2->extract) (o2, opcode, &count);
if (len != 64 - count)
return 0;
}
}
return 1;
}
/* Find an instruction entry in the ia64_dis_names array that matches
opcode OPCODE and is of type TYPE. Returns either a positive index
into the array, or a negative value if an entry for OPCODE could
not be found. Checks all matches and returns the one with the highest
priority. */
static int
locate_opcode_ent (opcode, type)
ia64_insn opcode;
enum ia64_insn_type type;
{
int currtest[41];
int bitpos[41];
int op_ptr[41];
int currstatenum = 0;
short found_disent = -1;
short found_priority = -1;
currtest[currstatenum] = 0;
op_ptr[currstatenum] = 0;
bitpos[currstatenum] = 40;
while (1)
{
int op_pointer = op_ptr[currstatenum];
unsigned int op;
int currbitnum = bitpos[currstatenum];
int oplen;
int opval[3];
int next_op;
int currbit;
oplen = extract_op (op_pointer, opval, &op);
bitpos[currstatenum] = currbitnum;
/* Skip opval[0] bits in the instruction. */
if (op & 0x40)
{
currbitnum -= opval[0];
}
/* The value of the current bit being tested. */
currbit = opcode & (((ia64_insn) 1) << currbitnum) ? 1 : 0;
next_op = -1;
/* We always perform the tests specified in the current state in
a particular order, falling through to the next test if the
previous one failed. */
switch (currtest[currstatenum])
{
case 0:
currtest[currstatenum]++;
if (currbit == 0 && (op & 0x80))
{
/* Check for a zero bit. If this test solely checks for
a zero bit, we can check for up to 8 consecutive zero
bits (the number to check is specified by the lower 3
bits in the state code.)
If the state instruction matches, we go to the very
next state instruction; otherwise, try the next test. */
if ((op & 0xf8) == 0x80)
{
int count = op & 0x7;
int x;
for (x = 0; x <= count; x++)
{
int i =
opcode & (((ia64_insn) 1) << (currbitnum - x)) ? 1 : 0;
if (i)
{
break;
}
}
if (x > count)
{
next_op = op_pointer + ((oplen + 7) / 8);
currbitnum -= count;
break;
}
}
else if (! currbit)
{
next_op = op_pointer + ((oplen + 7) / 8);
break;
}
}
/* FALLTHROUGH */
case 1:
/* If the bit in the instruction is one, go to the state
instruction specified by opval[1]. */
currtest[currstatenum]++;
if (currbit && (op & 0x30) != 0 && ((op & 0x30) != 0x30))
{
next_op = opval[1];
break;
}
/* FALLTHROUGH */
case 2:
/* Don't care. Skip the current bit and go to the state
instruction specified by opval[2].
An encoding of 0x30 is special; this means that a 12-bit
offset into the ia64_dis_names[] array is specified. */
currtest[currstatenum]++;
if ((op & 0x08) || ((op & 0x30) == 0x30))
{
next_op = opval[2];
break;
}
}
/* If bit 15 is set in the address of the next state, an offset
in the ia64_dis_names array was specified instead. We then
check to see if an entry in the list of opcodes matches the
opcode we were given; if so, we have succeeded. */
if ((next_op >= 0) && (next_op & 32768))
{
short disent = next_op & 32767;
short priority = -1;
if (next_op > 65535)
{
abort ();
}
/* Run through the list of opcodes to check, trying to find
one that matches. */
while (disent >= 0)
{
int place = ia64_dis_names[disent].insn_index;
priority = ia64_dis_names[disent].priority;
if (opcode_verify (opcode, place, type)
&& priority > found_priority)
{
break;
}
if (ia64_dis_names[disent].next_flag)
{
disent++;
}
else
{
disent = -1;
}
}
if (disent >= 0)
{
found_disent = disent;
found_priority = priority;
}
/* Try the next test in this state, regardless of whether a match
was found. */
next_op = -2;
}
/* next_op == -1 is "back up to the previous state".
next_op == -2 is "stay in this state and try the next test".
Otherwise, transition to the state indicated by next_op. */
if (next_op == -1)
{
currstatenum--;
if (currstatenum < 0)
{
return found_disent;
}
}
else if (next_op >= 0)
{
currstatenum++;
bitpos[currstatenum] = currbitnum - 1;
op_ptr[currstatenum] = next_op;
currtest[currstatenum] = 0;
}
}
}
/* Construct an ia64_opcode entry based on OPCODE, NAME and PLACE. */
static struct ia64_opcode *
make_ia64_opcode (opcode, name, place, depind)
ia64_insn opcode;
const char *name;
int place;
int depind;
{
struct ia64_opcode *res =
(struct ia64_opcode *) xmalloc (sizeof (struct ia64_opcode));
res->name = xstrdup (name);
res->type = main_table[place].opcode_type;
res->num_outputs = main_table[place].num_outputs;
res->opcode = opcode;
res->mask = main_table[place].mask;
res->operands[0] = main_table[place].operands[0];
res->operands[1] = main_table[place].operands[1];
res->operands[2] = main_table[place].operands[2];
res->operands[3] = main_table[place].operands[3];
res->operands[4] = main_table[place].operands[4];
res->flags = main_table[place].flags;
res->ent_index = place;
res->dependencies = &op_dependencies[depind];
return res;
}
/* Determine the ia64_opcode entry for the opcode specified by INSN
and TYPE. If a valid entry is not found, return NULL. */
struct ia64_opcode *
ia64_dis_opcode (insn, type)
ia64_insn insn;
enum ia64_insn_type type;
{
int disent = locate_opcode_ent (insn, type);
if (disent < 0)
{
return NULL;
}
else
{
unsigned int cb = ia64_dis_names[disent].completer_index;
static char name[128];
int place = ia64_dis_names[disent].insn_index;
int ci = main_table[place].completers;
ia64_insn tinsn = main_table[place].opcode;
strcpy (name, ia64_strings [main_table[place].name_index]);
while (cb)
{
if (cb & 1)
{
int cname = completer_table[ci].name_index;
tinsn = apply_completer (tinsn, ci);
if (ia64_strings[cname][0] != '\0')
{
strcat (name, ".");
strcat (name, ia64_strings[cname]);
}
if (cb != 1)
{
ci = completer_table[ci].subentries;
}
}
else
{
ci = completer_table[ci].alternative;
}
if (ci < 0)
{
abort ();
}
cb = cb >> 1;
}
if (tinsn != (insn & main_table[place].mask))
{
abort ();
}
return make_ia64_opcode (insn, name, place,
completer_table[ci].dependencies);
}
}
/* Search the main_opcode table starting from PLACE for an opcode that
matches NAME. Return NULL if one is not found. */
static struct ia64_opcode *
ia64_find_matching_opcode (name, place)
const char *name;
short place;
{
char op[129];
const char *suffix;
short name_index;
if (strlen (name) > 128)
{
return NULL;
}
suffix = name;
get_opc_prefix (&suffix, op);
name_index = find_string_ent (op);
if (name_index < 0)
{
return NULL;
}
while (main_table[place].name_index == name_index)
{
const char *curr_suffix = suffix;
ia64_insn curr_insn = main_table[place].opcode;
short completer = -1;
do {
if (suffix[0] == '\0')
{
completer = find_completer (place, completer, suffix);
}
else
{
get_opc_prefix (&curr_suffix, op);
completer = find_completer (place, completer, op);
}
if (completer != -1)
{
curr_insn = apply_completer (curr_insn, completer);
}
} while (completer != -1 && curr_suffix[0] != '\0');
if (completer != -1 && curr_suffix[0] == '\0'
&& completer_table[completer].terminal_completer)
{
int depind = completer_table[completer].dependencies;
return make_ia64_opcode (curr_insn, name, place, depind);
}
else
{
place++;
}
}
return NULL;
}
/* Find the next opcode after PREV_ENT that matches PREV_ENT, or return NULL
if one does not exist.
It is the caller's responsibility to invoke ia64_free_opcode () to
release any resources used by the returned entry. */
struct ia64_opcode *
ia64_find_next_opcode (prev_ent)
struct ia64_opcode *prev_ent;
{
return ia64_find_matching_opcode (prev_ent->name,
prev_ent->ent_index + 1);
}
/* Find the first opcode that matches NAME, or return NULL if it does
not exist.
It is the caller's responsibility to invoke ia64_free_opcode () to
release any resources used by the returned entry. */
struct ia64_opcode *
ia64_find_opcode (name)
const char *name;
{
char op[129];
const char *suffix;
short place;
short name_index;
if (strlen (name) > 128)
{
return NULL;
}
suffix = name;
get_opc_prefix (&suffix, op);
name_index = find_string_ent (op);
if (name_index < 0)
{
return NULL;
}
place = find_main_ent (name_index);
if (place < 0)
{
return NULL;
}
return ia64_find_matching_opcode (name, place);
}
/* Free any resources used by ENT. */
void
ia64_free_opcode (ent)
struct ia64_opcode *ent;
{
free ((void *)ent->name);
free (ent);
}
const struct ia64_dependency *
ia64_find_dependency (index)
int index;
{
index = DEP(index);
if (index < 0
|| index >= (int)(sizeof(dependencies) / sizeof(dependencies[0])))
return NULL;
return &dependencies[index];
}

130
contrib/binutils/opcodes/ia64-opc.h Normal file
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@ -0,0 +1,130 @@
/* ia64-opc.h -- IA-64 opcode table.
Copyright 1998, 1999, 2000 Free Software Foundation, Inc.
Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
This file is part of GDB, GAS, and the GNU binutils.
GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.
GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this file; see the file COPYING. If not, write to the
Free Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
#ifndef IA64_OPC_H
#define IA64_OPC_H
#include "opcode/ia64.h"
/* define a couple of abbreviations: */
#define bOp(x) (((ia64_insn) ((x) & 0xf)) << 37)
#define mOp bOp (-1)
#define Op(x) bOp (x), mOp
#define FIRST IA64_OPCODE_FIRST
#define X_IN_MLX IA64_OPCODE_X_IN_MLX
#define LAST IA64_OPCODE_LAST
#define PRIV IA64_OPCODE_PRIV
#define NO_PRED IA64_OPCODE_NO_PRED
#define SLOT2 IA64_OPCODE_SLOT2
#define PSEUDO IA64_OPCODE_PSEUDO
#define F2_EQ_F3 IA64_OPCODE_F2_EQ_F3
#define LEN_EQ_64MCNT IA64_OPCODE_LEN_EQ_64MCNT
#define MOD_RRBS IA64_OPCODE_MOD_RRBS
#define POSTINC IA64_OPCODE_POSTINC
#define AR_CCV IA64_OPND_AR_CCV
#define AR_PFS IA64_OPND_AR_PFS
#define C1 IA64_OPND_C1
#define C8 IA64_OPND_C8
#define C16 IA64_OPND_C16
#define GR0 IA64_OPND_GR0
#define IP IA64_OPND_IP
#define PR IA64_OPND_PR
#define PR_ROT IA64_OPND_PR_ROT
#define PSR IA64_OPND_PSR
#define PSR_L IA64_OPND_PSR_L
#define PSR_UM IA64_OPND_PSR_UM
#define AR3 IA64_OPND_AR3
#define B1 IA64_OPND_B1
#define B2 IA64_OPND_B2
#define CR3 IA64_OPND_CR3
#define F1 IA64_OPND_F1
#define F2 IA64_OPND_F2
#define F3 IA64_OPND_F3
#define F4 IA64_OPND_F4
#define P1 IA64_OPND_P1
#define P2 IA64_OPND_P2
#define R1 IA64_OPND_R1
#define R2 IA64_OPND_R2
#define R3 IA64_OPND_R3
#define R3_2 IA64_OPND_R3_2
#define CPUID_R3 IA64_OPND_CPUID_R3
#define DBR_R3 IA64_OPND_DBR_R3
#define DTR_R3 IA64_OPND_DTR_R3
#define ITR_R3 IA64_OPND_ITR_R3
#define IBR_R3 IA64_OPND_IBR_R3
#define MR3 IA64_OPND_MR3
#define MSR_R3 IA64_OPND_MSR_R3
#define PKR_R3 IA64_OPND_PKR_R3
#define PMC_R3 IA64_OPND_PMC_R3
#define PMD_R3 IA64_OPND_PMD_R3
#define RR_R3 IA64_OPND_RR_R3
#define CCNT5 IA64_OPND_CCNT5
#define CNT2a IA64_OPND_CNT2a
#define CNT2b IA64_OPND_CNT2b
#define CNT2c IA64_OPND_CNT2c
#define CNT5 IA64_OPND_CNT5
#define CNT6 IA64_OPND_CNT6
#define CPOS6a IA64_OPND_CPOS6a
#define CPOS6b IA64_OPND_CPOS6b
#define CPOS6c IA64_OPND_CPOS6c
#define IMM1 IA64_OPND_IMM1
#define IMM14 IA64_OPND_IMM14
#define IMM17 IA64_OPND_IMM17
#define IMM22 IA64_OPND_IMM22
#define IMM44 IA64_OPND_IMM44
#define SOF IA64_OPND_SOF
#define SOL IA64_OPND_SOL
#define SOR IA64_OPND_SOR
#define IMM8 IA64_OPND_IMM8
#define IMM8U4 IA64_OPND_IMM8U4
#define IMM8M1 IA64_OPND_IMM8M1
#define IMM8M1U4 IA64_OPND_IMM8M1U4
#define IMM8M1U8 IA64_OPND_IMM8M1U8
#define IMM9a IA64_OPND_IMM9a
#define IMM9b IA64_OPND_IMM9b
#define IMMU2 IA64_OPND_IMMU2
#define IMMU21 IA64_OPND_IMMU21
#define IMMU24 IA64_OPND_IMMU24
#define IMMU62 IA64_OPND_IMMU62
#define IMMU64 IA64_OPND_IMMU64
#define IMMU7a IA64_OPND_IMMU7a
#define IMMU7b IA64_OPND_IMMU7b
#define IMMU9 IA64_OPND_IMMU9
#define INC3 IA64_OPND_INC3
#define LEN4 IA64_OPND_LEN4
#define LEN6 IA64_OPND_LEN6
#define MBTYPE4 IA64_OPND_MBTYPE4
#define MHTYPE8 IA64_OPND_MHTYPE8
#define POS6 IA64_OPND_POS6
#define TAG13 IA64_OPND_TAG13
#define TAG13b IA64_OPND_TAG13b
#define TGT25 IA64_OPND_TGT25
#define TGT25b IA64_OPND_TGT25b
#define TGT25c IA64_OPND_TGT25c
#define TGT64 IA64_OPND_TGT64
#endif

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contrib/binutils/opcodes/ia64-raw.tbl Normal file
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Resource Name; Writers; Readers; Semantics of Dependency
ALAT; chk.a.clr, IC:mem-readers-alat, IC:mem-writers, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, IC:chk-a, invala.e; none
AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ia, br.ret, cover, flushrs, loadrs, IC:mov-from-AR-BSP, rfi; impliedF
AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, IC:mov-from-AR-BSPSTORE; impliedF
AR[CCV]; IC:mov-to-AR-CCV; br.ia, IC:cmpxchg, IC:mov-from-AR-CCV; impliedF
AR[EC]; IC:mod-sched-brs, br.ret, IC:mov-to-AR-EC; br.call, brl.call, br.ia, IC:mod-sched-brs, IC:mov-from-AR-EC; impliedF
AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; br.ia, IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0, fsetc, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; br.ia, IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; br.ia, IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; br.ia, IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf0.flags; IC:fp-arith-s0, fclrf.s0, IC:fcmp-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; br.ia, fchkf, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf1.flags; IC:fp-arith-s1, fclrf.s1, IC:fcmp-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; br.ia, fchkf.s1, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf2.flags; IC:fp-arith-s2, fclrf.s2, IC:fcmp-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; br.ia, fchkf.s2, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].sf3.flags; IC:fp-arith-s3, fclrf.s3, IC:fcmp-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; br.ia, fchkf.s3, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].traps; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
AR[FPSR].rv; IC:mov-to-AR-FPSR; br.ia, IC:fp-arith, fchkf, fcmp, fpcmp, IC:mov-from-AR-FPSR; impliedF
AR[ITC]; IC:mov-to-AR-ITC; br.ia, IC:mov-from-AR-ITC; impliedF
AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; br.ia, IC:mov-from-AR-K+1; impliedF
AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; br.ia, IC:mod-sched-brs-counted, IC:mov-from-AR-LC; impliedF
AR[PFS]; br.call, brl.call; alloc, br.ia, br.ret, epc, IC:mov-from-AR-PFS; impliedF
AR[PFS]; IC:mov-to-AR-PFS; alloc, br.ia, epc, IC:mov-from-AR-PFS; impliedF
AR[PFS]; IC:mov-to-AR-PFS; br.ret; none
AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RNAT; impliedF
AR[RSC]; IC:mov-to-AR-RSC; alloc, br.ia, flushrs, loadrs, IC:mov-from-AR-RSC, IC:mov-from-AR-BSPSTORE, IC:mov-to-AR-RNAT, IC:mov-from-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF
AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; br.ia, ld8.fill, IC:mov-from-AR-UNAT; impliedF
AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; br.ia, IC:mov-from-AR-rv+1; none
AR%, % in 48-63, 112-127; IC:mov-to-AR-ig+1; br.ia, IC:mov-from-AR-ig+1; impliedF
BR%, % in 0 - 7; br.call+1, brl.call+1; IC:indirect-brs+1, IC:indirect-brp+1, IC:mov-from-BR+1; impliedF
BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brs+1; none
BR%, % in 0 - 7; IC:mov-to-BR+1; IC:indirect-brp+1, IC:mov-from-BR+1; impliedF
CFM; IC:mod-sched-brs; IC:mod-sched-brs; impliedF
CFM; IC:mod-sched-brs; cover, alloc, rfi, loadrs, br.ret, br.call, brl.call; impliedF
CFM; IC:mod-sched-brs; IC:cfm-readers+2; impliedF
CFM; br.call, brl.call, br.ret, clrrrb, cover, rfi; IC:cfm-readers; impliedF
CFM; alloc; IC:cfm-readers; none
CPUID#; IC:none; IC:mov-from-IND-CPUID+3; specific
CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-from-CR-CMCV; data
CR[DCR]; IC:mov-to-CR-DCR; IC:mov-from-CR-DCR, IC:mem-readers-spec; data
CR[EOI]; IC:mov-to-CR-EOI; IC:none; SC Section 10.8.3.4
CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-from-CR-GPTA, thash; data
CR[IFA]; IC:mov-to-CR-IFA; itc.i, itc.d, itr.i, itr.d; implied
CR[IFA]; IC:mov-to-CR-IFA; IC:mov-from-CR-IFA; data
CR[IFS]; IC:mov-to-CR-IFS; IC:mov-from-CR-IFS; data
CR[IFS]; IC:mov-to-CR-IFS; rfi; implied
CR[IFS]; cover; rfi, IC:mov-from-CR-IFS; implied
CR[IHA]; IC:mov-to-CR-IHA; IC:mov-from-CR-IHA; data
CR[IIM]; IC:mov-to-CR-IIM; IC:mov-from-CR-IIM; data
CR[IIP]; IC:mov-to-CR-IIP; IC:mov-from-CR-IIP; data
CR[IIP]; IC:mov-to-CR-IIP; rfi; implied
CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-from-CR-IIPA; data
CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-from-CR-IPSR; data
CR[IPSR]; IC:mov-to-CR-IPSR; rfi; implied
CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IRR+1; data
CR[ISR]; IC:mov-to-CR-ISR; IC:mov-from-CR-ISR; data
CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-from-CR-ITIR; data
CR[ITIR]; IC:mov-to-CR-ITIR; itc.i, itc.d, itr.i, itr.d; implied
CR[ITM]; IC:mov-to-CR-ITM; IC:mov-from-CR-ITM; data
CR[ITV]; IC:mov-to-CR-ITV; IC:mov-from-CR-ITV; data
CR[IVA]; IC:mov-to-CR-IVA; IC:mov-from-CR-IVA; instr
CR[IVR]; IC:none; IC:mov-from-CR-IVR; SC Section 10.8.3.2
CR[LID]; IC:mov-to-CR-LID; IC:mov-from-CR-LID; SC Section 10.8.3.1
CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-from-CR-LRR+1; data
CR[PMV]; IC:mov-to-CR-PMV; IC:mov-from-CR-PMV; data
CR[PTA]; IC:mov-to-CR-PTA; IC:mov-from-CR-PTA, thash; data
CR[TPR]; IC:mov-to-CR-TPR; IC:mov-from-CR-TPR, IC:mov-from-CR-IVR; data
CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-PSR-l, rfi, rsm, ssm; SC Section 10.8.3.3
CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:mov-from-CR-rv+1; none
DBR#; IC:mov-to-IND-DBR+3; IC:mov-from-IND-DBR+3; impliedF
DBR#; IC:mov-to-IND-DBR+3; IC:probe-all, IC:lfetch-all, IC:mem-readers, IC:mem-writers; data
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data
DTC; itc.i, itc.d, itr.i, itr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; impliedF
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF
DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
DTR; itr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data
DTR; itr.d; ptc.g, ptc.ga, ptc.l, ptr.d, itr.d; impliedF
DTR; ptr.d; IC:mem-readers, IC:mem-writers, fc, IC:probe-all, tak, tpa; data
DTR; ptr.d; ptc.g, ptc.ga, ptc.l, ptr.d; none
DTR; ptr.d; itr.d, itc.d; impliedF
FR%, % in 0 - 1; IC:none; IC:fr-readers+1; none
FR%, % in 2 - 127; IC:fr-writers+1\IC:ldf-c+1\IC:ldfp-c+1; IC:fr-readers+1; impliedF
FR%, % in 2 - 127; IC:ldf-c+1, IC:ldfp-c+1; IC:fr-readers+1; none
GR0; IC:none; IC:gr-readers+1; none
GR%, % in 1 - 127; IC:ld-c+1+13; IC:gr-readers+1; none
GR%, % in 1 - 127; IC:gr-writers+1\IC:ld-c+1+13; IC:gr-readers+1; impliedF
IBR#; IC:mov-to-IND-IBR+3; IC:mov-from-IND-IBR+3; impliedF
InService*; IC:mov-to-CR-EOI; IC:mov-from-CR-IVR; data
InService*; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF
InService*; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; impliedF
IP; IC:all; IC:all; none
ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; epc; instr
ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; itc.i, itc.d, itr.i, itr.d; impliedF
ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptr.i, ptr.d, ptc.e, ptc.g, ptc.ga, ptc.l; none
ITC; itc.i, itc.d, itr.i, itr.d; epc; instr
ITC; itc.i, itc.d, itr.i, itr.d; itc.d, itc.i, itr.d, itr.i, ptr.d, ptr.i, ptc.g, ptc.ga, ptc.l; impliedF
ITC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
ITR; itr.i; itr.i, itc.i, ptc.g, ptc.ga, ptc.l, ptr.i; impliedF
ITR; itr.i; epc; instr
ITR; ptr.i; itc.i, itr.i; impliedF
ITR; ptr.i; ptc.g, ptc.ga, ptc.l, ptr.i; none
ITR; ptr.i; epc; instr
memory; IC:mem-writers; IC:mem-readers; none
MSR#; IC:mov-to-IND-MSR+5; IC:mov-from-IND-MSR+5; specific
PKR#; IC:mov-to-IND-PKR+3; IC:mem-readers, IC:mem-writers, IC:mov-from-IND-PKR+4, IC:probe-all; data
PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none
PKR#; IC:mov-to-IND-PKR+3; IC:mov-from-IND-PKR+3; impliedF
PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF
PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMC+3; impliedF
PMC#; IC:mov-to-IND-PMC+3; IC:mov-from-IND-PMD+3; SC+3 Section 12.1.1
PMD#; IC:mov-to-IND-PMD+3; IC:mov-from-IND-PMD+3; impliedF
PR0; IC:pr-writers+1; IC:pr-readers-br+1, IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR+12, IC:mov-to-PR+12; none
PR%, % in 1 - 15; IC:pr-writers+1, IC:mov-to-PR-allreg+7; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF
PR%, % in 1 - 15; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF
PR%, % in 1 - 15; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7; IC:pr-readers-br+1; none
PR%, % in 16 - 62; IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF
PR%, % in 16 - 62; IC:pr-writers-fp+1; IC:pr-readers-br+1; impliedF
PR%, % in 16 - 62; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none
PR63; IC:mod-sched-brs, IC:pr-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-nobr-nomovpr+1, IC:mov-from-PR, IC:mov-to-PR+12; impliedF
PR63; IC:pr-writers-fp+1, IC:mod-sched-brs; IC:pr-readers-br+1; impliedF
PR63; IC:pr-writers-int+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-readers-br+1; none
PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied
PSR.ac; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data
PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF
PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um; IC:mem-readers, IC:mem-writers; implied
PSR.be; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data
PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR, IC:mov-from-PSR-um; impliedF
PSR.bn; bsw, rfi; IC:gr-readers+10, IC:gr-writers+10; impliedF
PSR.cpl; epc, br.ret, rfi; IC:priv-ops, br.call, brl.call, epc, IC:mov-from-AR-ITC, IC:mov-to-AR-ITC, IC:mov-to-AR-RSC, IC:mov-to-AR-K, IC:mov-from-IND-PMD, IC:probe-all, IC:mem-readers, IC:mem-writers, IC:lfetch-all; implied
PSR.da; rfi; IC:mem-readers, IC:lfetch-fault, IC:mem-writers, IC:probe-fault; data
PSR.db; IC:mov-to-PSR-l; IC:mem-readers, IC:mem-writers, IC:probe-fault; data
PSR.db; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
PSR.db; rfi; IC:mem-readers, IC:mem-writers, IC:mov-from-PSR, IC:probe-fault; data
PSR.dd; rfi; IC:mem-readers, IC:probe-fault, IC:mem-writers, IC:lfetch-fault; data
PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-readers+8, IC:fr-writers+8; data
PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:fr-writers+8, IC:fr-readers+8; data
PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; br.ia; data
PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers; data
PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.ed; rfi; IC:lfetch-all, IC:mem-readers-spec; data
PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
PSR.i; rfi; IC:mov-from-PSR; data
PSR.ia; rfi; IC:none; none
PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; cover, itc.i, itc.d, itr.i, itr.d, IC:mov-from-CR-ITIR, IC:mov-from-CR-IFS, IC:mov-from-CR-IIM, IC:mov-from-CR-IIP, IC:mov-from-CR-IPSR, IC:mov-from-CR-ISR, IC:mov-from-CR-IFA, IC:mov-from-CR-IHA, IC:mov-from-CR-IIPA, IC:mov-to-CR-ITIR, IC:mov-to-CR-IFS, IC:mov-to-CR-IIM, IC:mov-to-CR-IIP, IC:mov-to-CR-IPSR, IC:mov-to-CR-ISR, IC:mov-to-CR-IFA, IC:mov-to-CR-IHA, IC:mov-to-CR-IIPA; data
PSR.id; rfi; IC:none; none
PSR.is; br.ia, rfi; IC:none; none
PSR.it; rfi; IC:branches, IC:mov-from-PSR, chk, epc, fchkf; data
PSR.lp; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
PSR.lp; IC:mov-to-PSR-l; br.ret; data
PSR.lp; rfi; IC:mov-from-PSR, br.ret; data
PSR.mc; rfi; IC:mov-from-PSR; none
PSR.mfh; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF
PSR.mfl; IC:fr-writers+9, IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF
PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mem-readers, IC:mem-writers, IC:probe-all; data
PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.ri; rfi; IC:none; none
PSR.rt; IC:mov-to-PSR-l; IC:mov-from-PSR; impliedF
PSR.rt; IC:mov-to-PSR-l; alloc, flushrs, loadrs; data
PSR.rt; rfi; IC:mov-from-PSR, alloc, flushrs, loadrs; data
PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-AR-ITC; data
PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-IND-PMD, IC:mov-to-PSR-um, rum, sum; data
PSR.ss; rfi; IC:all; data
PSR.tb; IC:mov-to-PSR-l, rfi; IC:branches, chk, fchkf; data
PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-from-PSR; impliedF
PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:mov-from-PSR-um, IC:mov-from-PSR; impliedF
RR#; IC:mov-to-IND-RR+6; IC:mem-readers, IC:mem-writers, itc.i, itc.d, itr.i, itr.d, IC:probe-all, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, tak, thash, tpa, ttag; data
RR#; IC:mov-to-IND-RR+6; IC:mov-from-IND-RR+6; impliedF
RSE; IC:rse-writers+14; IC:rse-readers+14; impliedF

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Resource Name; Readers; Writers; Semantics of Dependency
PR63; IC:pr-readers-br+1; IC:mod-sched-brs; stop

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contrib/binutils/opcodes/ia64-waw.tbl Normal file
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Resource Name; Writers; Writers; Semantics of Dependency
ALAT; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; IC:mem-readers-alat, IC:mem-writers, chk.a.clr, IC:invala-all; none
AR[BSP]; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; br.call, brl.call, br.ret, cover, IC:mov-to-AR-BSPSTORE, rfi; impliedF
AR[BSPSTORE]; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; alloc, loadrs, flushrs, IC:mov-to-AR-BSPSTORE; impliedF
AR[CCV]; IC:mov-to-AR-CCV; IC:mov-to-AR-CCV; impliedF
AR[EC]; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; br.ret, IC:mod-sched-brs, IC:mov-to-AR-EC; impliedF
AR[FPSR].sf0.controls; IC:mov-to-AR-FPSR, fsetc.s0; IC:mov-to-AR-FPSR, fsetc.s0; impliedF
AR[FPSR].sf1.controls; IC:mov-to-AR-FPSR, fsetc.s1; IC:mov-to-AR-FPSR, fsetc.s1; impliedF
AR[FPSR].sf2.controls; IC:mov-to-AR-FPSR, fsetc.s2; IC:mov-to-AR-FPSR, fsetc.s2; impliedF
AR[FPSR].sf3.controls; IC:mov-to-AR-FPSR, fsetc.s3; IC:mov-to-AR-FPSR, fsetc.s3; impliedF
AR[FPSR].sf0.flags; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; IC:fp-arith-s0, IC:fcmp-s0, IC:fpcmp-s0; none
AR[FPSR].sf0.flags; fclrf.s0, IC:fcmp-s0, IC:fp-arith-s0, IC:fpcmp-s0, IC:mov-to-AR-FPSR; fclrf.s0, IC:mov-to-AR-FPSR; impliedF
AR[FPSR].sf1.flags; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; IC:fp-arith-s1, IC:fcmp-s1, IC:fpcmp-s1; none
AR[FPSR].sf1.flags; fclrf.s1, IC:fcmp-s1, IC:fp-arith-s1, IC:fpcmp-s1, IC:mov-to-AR-FPSR; fclrf.s1, IC:mov-to-AR-FPSR; impliedF
AR[FPSR].sf2.flags; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; IC:fp-arith-s2, IC:fcmp-s2, IC:fpcmp-s2; none
AR[FPSR].sf2.flags; fclrf.s2, IC:fcmp-s2, IC:fp-arith-s2, IC:fpcmp-s2, IC:mov-to-AR-FPSR; fclrf.s2, IC:mov-to-AR-FPSR; impliedF
AR[FPSR].sf3.flags; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; IC:fp-arith-s3, IC:fcmp-s3, IC:fpcmp-s3; none
AR[FPSR].sf3.flags; fclrf.s3, IC:fcmp-s3, IC:fp-arith-s3, IC:fpcmp-s3, IC:mov-to-AR-FPSR; fclrf.s3, IC:mov-to-AR-FPSR; impliedF
AR[FPSR].rv; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
AR[FPSR].traps; IC:mov-to-AR-FPSR; IC:mov-to-AR-FPSR; impliedF
AR[ITC]; IC:mov-to-AR-ITC; IC:mov-to-AR-ITC; impliedF
AR[K%], % in 0 - 7; IC:mov-to-AR-K+1; IC:mov-to-AR-K+1; impliedF
AR[LC]; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; IC:mod-sched-brs-counted, IC:mov-to-AR-LC; impliedF
AR[PFS]; br.call, brl.call; br.call, brl.call; none
AR[PFS]; br.call, brl.call; IC:mov-to-AR-PFS; impliedF
AR[RNAT]; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; alloc, flushrs, loadrs, IC:mov-to-AR-RNAT, IC:mov-to-AR-BSPSTORE; impliedF
AR[RSC]; IC:mov-to-AR-RSC; IC:mov-to-AR-RSC; impliedF
AR[UNAT]{%}, % in 0 - 63; IC:mov-to-AR-UNAT, st8.spill; IC:mov-to-AR-UNAT, st8.spill; impliedF
AR%, % in 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111; IC:none; IC:none; none
AR%, % in 48 - 63, 112-127; IC:mov-to-AR-ig+1; IC:mov-to-AR-ig+1; impliedF
BR%, % in 0 - 7; br.call+1, brl.call+1; IC:mov-to-BR+1; impliedF
BR%, % in 0 - 7; IC:mov-to-BR+1; IC:mov-to-BR+1; impliedF
BR%, % in 0 - 7; br.call+1, brl.call+1; br.call+1, brl.call+1; none
CFM; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; IC:mod-sched-brs, br.call, brl.call, br.ret, alloc, clrrrb, cover, rfi; impliedF
CPUID#; IC:none; IC:none; none
CR[CMCV]; IC:mov-to-CR-CMCV; IC:mov-to-CR-CMCV; impliedF
CR[DCR]; IC:mov-to-CR-DCR; IC:mov-to-CR-DCR; impliedF
CR[EOI]; IC:mov-to-CR-EOI; IC:mov-to-CR-EOI; SC Section 10.8.3.4
CR[GPTA]; IC:mov-to-CR-GPTA; IC:mov-to-CR-GPTA; impliedF
CR[IFA]; IC:mov-to-CR-IFA; IC:mov-to-CR-IFA; impliedF
CR[IFS]; IC:mov-to-CR-IFS, cover; IC:mov-to-CR-IFS, cover; impliedF
CR[IHA]; IC:mov-to-CR-IHA; IC:mov-to-CR-IHA; impliedF
CR[IIM]; IC:mov-to-CR-IIM; IC:mov-to-CR-IIM; impliedF
CR[IIP]; IC:mov-to-CR-IIP; IC:mov-to-CR-IIP; impliedF
CR[IIPA]; IC:mov-to-CR-IIPA; IC:mov-to-CR-IIPA; impliedF
CR[IPSR]; IC:mov-to-CR-IPSR; IC:mov-to-CR-IPSR; impliedF
CR[IRR%], % in 0 - 3; IC:mov-from-CR-IVR; IC:mov-from-CR-IVR; impliedF
CR[ISR]; IC:mov-to-CR-ISR; IC:mov-to-CR-ISR; impliedF
CR[ITIR]; IC:mov-to-CR-ITIR; IC:mov-to-CR-ITIR; impliedF
CR[ITM]; IC:mov-to-CR-ITM; IC:mov-to-CR-ITM; impliedF
CR[ITV]; IC:mov-to-CR-ITV; IC:mov-to-CR-ITV; impliedF
CR[IVA]; IC:mov-to-CR-IVA; IC:mov-to-CR-IVA; impliedF
CR[IVR]; IC:none; IC:none; SC
CR[LID]; IC:mov-to-CR-LID; IC:mov-to-CR-LID; SC
CR[LRR%], % in 0 - 1; IC:mov-to-CR-LRR+1; IC:mov-to-CR-LRR+1; impliedF
CR[PMV]; IC:mov-to-CR-PMV; IC:mov-to-CR-PMV; impliedF
CR[PTA]; IC:mov-to-CR-PTA; IC:mov-to-CR-PTA; impliedF
CR[TPR]; IC:mov-to-CR-TPR; IC:mov-to-CR-TPR; impliedF
CR%, % in 3-7, 10-15, 18, 26-63, 75-79, 82-127; IC:none; IC:none; none
DBR#; IC:mov-to-IND-DBR+3; IC:mov-to-IND-DBR+3; impliedF
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
DTC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF
DTC_LIMIT*; ptc.g, ptc.ga; ptc.g, ptc.ga; impliedF
DTR; itr.d; itr.d; impliedF
DTR; itr.d; ptr.d; impliedF
DTR; ptr.d; ptr.d; none
FR%, % in 0 - 1; IC:none; IC:none; none
FR%, % in 2 - 127; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; IC:fr-writers+1, IC:ldf-c+1, IC:ldfp-c+1; impliedF
GR0; IC:none; IC:none; none
GR%, % in 1 - 127; IC:ld-c+1, IC:gr-writers+1; IC:ld-c+1, IC:gr-writers+1; impliedF
IBR#; IC:mov-to-IND-IBR+3; IC:mov-to-IND-IBR+3; impliedF
InService*; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; IC:mov-to-CR-EOI, IC:mov-from-CR-IVR; SC
IP; IC:all; IC:all; none
ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d; none
ITC; ptc.e, ptc.g, ptc.ga, ptc.l, ptr.i, ptr.d, itc.i, itc.d, itr.i, itr.d; itc.i, itc.d, itr.i, itr.d; impliedF
ITR; itr.i; itr.i, ptr.i; impliedF
ITR; ptr.i; ptr.i; none
memory; IC:mem-writers; IC:mem-writers; none
MSR#; IC:mov-to-IND-MSR+5; IC:mov-to-IND-MSR+5; SC
PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+4; none
PKR#; IC:mov-to-IND-PKR+3; IC:mov-to-IND-PKR+3; impliedF
PMC#; IC:mov-to-IND-PMC+3; IC:mov-to-IND-PMC+3; impliedF
PMD#; IC:mov-to-IND-PMD+3; IC:mov-to-IND-PMD+3; impliedF
PR0; IC:pr-writers+1; IC:pr-writers+1; none
PR%, % in 1 - 15; IC:pr-and-writers+1; IC:pr-and-writers+1; none
PR%, % in 1 - 15; IC:pr-or-writers+1; IC:pr-or-writers+1; none
PR%, % in 1 - 15; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7; impliedF
PR%, % in 16 - 62; IC:pr-and-writers+1; IC:pr-and-writers+1; none
PR%, % in 16 - 62; IC:pr-or-writers+1; IC:pr-or-writers+1; none
PR%, % in 16 - 62; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF
PR63; IC:pr-and-writers+1; IC:pr-and-writers+1; none
PR63; IC:pr-or-writers+1; IC:pr-or-writers+1; none
PR63; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-and-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; IC:mod-sched-brs, IC:pr-unc-writers-fp+1, IC:pr-unc-writers-int+1, IC:pr-norm-writers-fp+1, IC:pr-norm-writers-int+1, IC:pr-or-writers+1, IC:mov-to-PR-allreg+7, IC:mov-to-PR-rotreg; impliedF
PSR.ac; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.be; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.bn; bsw, rfi; bsw, rfi; impliedF
PSR.cpl; epc, br.ret, rfi; epc, br.ret, rfi; impliedF
PSR.da; rfi; rfi; impliedF
PSR.db; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
PSR.dd; rfi; rfi; impliedF
PSR.dfh; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.dfl; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.di; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.dt; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.ed; rfi; rfi; impliedF
PSR.i; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.ia; rfi; rfi; impliedF
PSR.ic; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.id; rfi; rfi; impliedF
PSR.is; br.ia, rfi; br.ia, rfi; impliedF
PSR.it; rfi; rfi; impliedF
PSR.lp; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
PSR.mc; rfi; rfi; impliedF
PSR.mfh; IC:fr-writers+9; IC:fr-writers+9; none
PSR.mfh; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.mfl; IC:fr-writers+9; IC:fr-writers+9; none
PSR.mfl; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:fr-writers+9, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.pk; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.pp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.ri; rfi; rfi; impliedF
PSR.rt; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
PSR.si; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.sp; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
PSR.ss; rfi; rfi; impliedF
PSR.tb; IC:mov-to-PSR-l, rfi; IC:mov-to-PSR-l, rfi; impliedF
PSR.up; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; IC:user-mask-writers-partial+7, IC:mov-to-PSR-um, IC:sys-mask-writers-partial+7, IC:mov-to-PSR-l, rfi; impliedF
RR#; IC:mov-to-IND-RR+6; IC:mov-to-IND-RR+6; impliedF
RSE; IC:rse-writers+14; IC:rse-writers+14; impliedF