mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-22 15:47:37 +00:00
Implement the first part of the BB read workaround.
The AR5008/AR9001 series NICs have a bug where BB register reads will occasionally be corrupted. This could cause issues with things such as ANI, which adjust operational parameters based on the BB radio register reads. This was introduced in the AR5008 chip and fixed with the first released AR9002 series NIC (AR9280v2.) A followup commit will implement the acutal WAR when reading BB registers. I'm still not sure how I'll implement it - whether it should be done in the osdep layer, or whether it should just live in the AR5416 HAL. Either way, they can use this capability bit to determine whether to implement the WAR or not. Thankyou to various sources inside Atheros who have helped me track down what this particular issue is. Obtained from: Atheros
This commit is contained in:
parent
31a47d8c14
commit
46614948dd
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=226488
sys/dev/ath/ath_hal
@ -659,6 +659,8 @@ ath_hal_getcapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
|
||||
return pCap->halHasRxSelfLinkedTail ? HAL_OK : HAL_ENOTSUPP;
|
||||
case HAL_CAP_LONG_RXDESC_TSF: /* 32 bit TSF in RX descriptor? */
|
||||
return pCap->halHasLongRxDescTsf ? HAL_OK : HAL_ENOTSUPP;
|
||||
case HAL_CAP_BB_READ_WAR: /* Baseband read WAR */
|
||||
return pCap->halHasBBReadWar? HAL_OK : HAL_ENOTSUPP;
|
||||
default:
|
||||
return HAL_EINVAL;
|
||||
}
|
||||
|
@ -149,6 +149,7 @@ typedef enum {
|
||||
HAL_CAP_STREAMS = 239, /* how many 802.11n spatial streams are available */
|
||||
HAL_CAP_RXDESC_SELFLINK = 242, /* support a self-linked tail RX descriptor */
|
||||
HAL_CAP_LONG_RXDESC_TSF = 243, /* hardware supports 32bit TSF in RX descriptor */
|
||||
HAL_CAP_BB_READ_WAR = 244, /* baseband read WAR */
|
||||
} HAL_CAPABILITY_TYPE;
|
||||
|
||||
/*
|
||||
|
@ -209,7 +209,8 @@ typedef struct {
|
||||
hal4kbSplitTransSupport : 1,
|
||||
halHasRxSelfLinkedTail : 1,
|
||||
halSupportsFastClock5GHz : 1, /* Hardware supports 5ghz fast clock; check eeprom/channel before using */
|
||||
halHasLongRxDescTsf : 1;
|
||||
halHasLongRxDescTsf : 1,
|
||||
halHasBBReadWar : 1;
|
||||
uint32_t halWirelessModes;
|
||||
uint16_t halTotalQueues;
|
||||
uint16_t halKeyCacheSize;
|
||||
|
@ -892,6 +892,12 @@ ar5416FillCapabilityInfo(struct ath_hal *ah)
|
||||
pCap->halEnhancedDfsSupport = AH_FALSE;
|
||||
/* Hardware supports 32 bit TSF values in the RX descriptor */
|
||||
pCap->halHasLongRxDescTsf = AH_TRUE;
|
||||
/*
|
||||
* BB Read WAR: this is only for AR5008/AR9001 NICs
|
||||
* It is also set individually in the AR91xx attach functions.
|
||||
*/
|
||||
if (AR_SREV_OWL(ah))
|
||||
pCap->halHasBBReadWar = AH_TRUE;
|
||||
|
||||
if (ath_hal_eepromGetFlag(ah, AR_EEP_RFKILL) &&
|
||||
ath_hal_eepromGet(ah, AR_EEP_RFSILENT, &ahpriv->ah_rfsilent) == HAL_OK) {
|
||||
|
@ -298,6 +298,8 @@ ar9130FillCapabilityInfo(struct ath_hal *ah)
|
||||
*/
|
||||
pCap->halMbssidAggrSupport = AH_FALSE;
|
||||
pCap->hal4AddrAggrSupport = AH_TRUE;
|
||||
/* BB Read WAR */
|
||||
pCap->halHasBBReadWar = AH_TRUE;
|
||||
|
||||
return AH_TRUE;
|
||||
}
|
||||
|
@ -320,6 +320,8 @@ ar9160FillCapabilityInfo(struct ath_hal *ah)
|
||||
pCap->halAutoSleepSupport = AH_FALSE; /* XXX? */
|
||||
pCap->halMbssidAggrSupport = AH_TRUE;
|
||||
pCap->hal4AddrAggrSupport = AH_TRUE;
|
||||
/* BB Read WAR */
|
||||
pCap->halHasBBReadWar = AH_TRUE;
|
||||
|
||||
/* AR9160 is a 2x2 stream device */
|
||||
pCap->halTxStreams = 2;
|
||||
|
Loading…
Reference in New Issue
Block a user