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The EHCI_CAPLENGTH and EHCI_HCIVERSION registers are actually sub-registers

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within the first 4 bytes of the EHCI memory space. For controllers that
use big-endian MMIO, reading them with 1- and 2-byte reads would then
return the wrong values. Instead, read the combined register with a 4-byte
read and mask out the interesting quantities.
This commit is contained in:
Nathan Whitehorn 2010-10-25 15:51:43 +00:00
parent 111044e6c2
commit 495ed64c16
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=214349
3 changed files with 10 additions and 6 deletions
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2
sys/dev/pci/pci.c
View File

@ -2803,7 +2803,7 @@ ehci_early_takeover(device_t self)
"SMM does not respond\n");
}
/* Disable interrupts */
offs = bus_read_1(res, EHCI_CAPLENGTH);
offs = EHCI_CAPLENGTH(bus_read_4(res, EHCI_CAPLEN_HCIVERSION));
bus_write_4(res, offs + EHCI_USBINTR, 0);
}
bus_release_resource(self, SYS_RES_MEMORY, rid, res);

4
sys/dev/usb/controller/ehci.c
View File

@ -270,9 +270,9 @@ ehci_init(ehci_softc_t *sc)
}
#endif
sc->sc_offs = EREAD1(sc, EHCI_CAPLENGTH);
sc->sc_offs = EHCI_CAPLENGTH(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
version = EREAD2(sc, EHCI_HCIVERSION);
version = EHCI_HCIVERSION(EREAD4(sc, EHCI_CAPLEN_HCIVERSION));
device_printf(sc->sc_bus.bdev, "EHCI version %x.%x\n",
version >> 8, version & 0xff);

10
sys/dev/usb/controller/ehcireg.h
View File

@ -54,9 +54,13 @@
#define EHCI_LEGSUP_USBLEGCTLSTS 0x04
/* EHCI capability registers */
#define EHCI_CAPLENGTH 0x00 /* RO Capability register length field */
#define EHCI_RESERVED 0x01 /* Reserved register */
#define EHCI_HCIVERSION 0x02 /* RO Interface version number */
#define EHCI_CAPLEN_HCIVERSION 0x00 /* RO Capability register length
* (least-significant byte) and
* interface version number (two
* most significant)
*/
#define EHCI_CAPLENGTH(x) ((x) & 0xff)
#define EHCI_HCIVERSION(x) (((x) >> 16) & 0xffff)
#define EHCI_HCSPARAMS 0x04 /* RO Structural parameters */
#define EHCI_HCS_DEBUGPORT(x) (((x) >> 20) & 0xf)
#define EHCI_HCS_P_INDICATOR(x) ((x) & 0x10000)