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Added CPU_DIRECT_MAPPED_CACHE option which sets L1 cache in direct
mapped mode on Cyrix 486DLC box.
This commit is contained in:
KATO Takenori
parent
439ff84095
commit
4962d93866
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=26985
@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: initcpu.c,v 1.4 1997/04/26 04:08:45 kato Exp $
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* $Id: initcpu.c,v 1.5 1997/05/31 08:45:24 kato Exp $
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*/
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#include "opt_cpu.h"
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@ -118,6 +118,9 @@ init_486dlc(void)
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ccr0 |= CCR0_NC1 | CCR0_BARB;
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#else
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ccr0 |= CCR0_NC1;
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#endif
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#ifdef CPU_DIRECT_MAPPED_CACHE
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ccr0 |= CCR0_CO; /* Direct mapped mode. */
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#endif
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write_cyrix_reg(CCR0, ccr0);
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.345 1997/06/17 05:58:15 kjc Exp $
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# $Id: LINT,v 1.346 1997/06/22 16:02:55 peter Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -138,6 +138,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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#
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# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
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#
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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@ -146,6 +149,7 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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#
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# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
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# for i386 machines.
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#
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# CPU_IORT defines I/O clock delay time (NOTE 1). Default vaules of
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# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
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# (no clock delay).
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@ -177,6 +181,7 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
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options "CPU_BLUELIGHTNING_3X"
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options "CPU_BTB_EN"
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options "CPU_DIRECT_MAPPED_CACHE"
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options "CPU_DISABLE_5X86_LSSER"
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options "CPU_FASTER_5X86_FPU"
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options "CPU_I486_ON_386"
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.345 1997/06/17 05:58:15 kjc Exp $
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# $Id: LINT,v 1.346 1997/06/22 16:02:55 peter Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -138,6 +138,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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#
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# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
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#
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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@ -146,6 +149,7 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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#
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# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
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# for i386 machines.
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#
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# CPU_IORT defines I/O clock delay time (NOTE 1). Default vaules of
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# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
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# (no clock delay).
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@ -177,6 +181,7 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
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options "CPU_BLUELIGHTNING_3X"
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options "CPU_BTB_EN"
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options "CPU_DIRECT_MAPPED_CACHE"
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options "CPU_DISABLE_5X86_LSSER"
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options "CPU_FASTER_5X86_FPU"
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options "CPU_I486_ON_386"
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.345 1997/06/17 05:58:15 kjc Exp $
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# $Id: LINT,v 1.346 1997/06/22 16:02:55 peter Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -138,6 +138,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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#
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# CPU_BTB_EN enables branch target buffer on Cyrix 5x86 (NOTE 1).
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#
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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@ -146,6 +149,7 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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#
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# CPU_I486_ON_386 enables CPU cache on i486 based CPU upgrade products
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# for i386 machines.
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#
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# CPU_IORT defines I/O clock delay time (NOTE 1). Default vaules of
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# I/O clock delay time on Cyrix 5x86 and 6x86 are 0 and 7,respectively
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# (no clock delay).
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@ -177,6 +181,7 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
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options "CPU_BLUELIGHTNING_3X"
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options "CPU_BTB_EN"
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options "CPU_DIRECT_MAPPED_CACHE"
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options "CPU_DISABLE_5X86_LSSER"
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options "CPU_FASTER_5X86_FPU"
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options "CPU_I486_ON_386"
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@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: initcpu.c,v 1.4 1997/04/26 04:08:45 kato Exp $
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* $Id: initcpu.c,v 1.5 1997/05/31 08:45:24 kato Exp $
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*/
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#include "opt_cpu.h"
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@ -118,6 +118,9 @@ init_486dlc(void)
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ccr0 |= CCR0_NC1 | CCR0_BARB;
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#else
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ccr0 |= CCR0_NC1;
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#endif
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#ifdef CPU_DIRECT_MAPPED_CACHE
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ccr0 |= CCR0_CO; /* Direct mapped mode. */
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#endif
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write_cyrix_reg(CCR0, ccr0);
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