mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-09 13:42:56 +00:00
XLR/XLS network driver (nlge) updates:
- nlge_ioctl handles IFF_UP and IFF_PROMISC flags - Translate table code, to enable flow based CPU assignment added disabled by default (can be enabled by a tunable). - Changed signature of nlge_port_disable to make it consistent with nlge_port_enable - Removed TXCSUM and VLAN_HW_TAGGING from i/f capabilities. Submitted by: Sriram Gorti (srgorti at netlogicmicro dot com)
This commit is contained in:
Jayachandran C.
parent
a5e14d3c15
commit
49f4ceab51
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=213475
@ -155,6 +155,7 @@ static void nlna_config_pde(struct nlna_softc *);
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static void nlna_config_parser(struct nlna_softc *);
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static void nlna_config_classifier(struct nlna_softc *);
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static void nlna_config_fifo_spill_area(struct nlna_softc *sc);
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static void nlna_config_translate_table(struct nlna_softc *sc);
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static void nlna_config_common(struct nlna_softc *);
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static void nlna_disable_ports(struct nlna_softc *sc);
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static void nlna_enable_intr(struct nlna_softc *sc);
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@ -188,7 +189,7 @@ static void nlge_mii_write_internal(xlr_reg_t *mii_base, int phyaddr,
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int regidx, int regval);
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void nlge_msgring_handler(int bucket, int size, int code,
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int stid, struct msgrng_msg *msg, void *data);
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static void nlge_port_disable(int id, xlr_reg_t *base, int port_type);
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static void nlge_port_disable(struct nlge_softc *sc);
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static void nlge_port_enable(struct nlge_softc *sc);
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static void nlge_read_mac_addr(struct nlge_softc *sc);
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static void nlge_sc_init(struct nlge_softc *sc, device_t dev,
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@ -196,6 +197,7 @@ static void nlge_sc_init(struct nlge_softc *sc, device_t dev,
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static void nlge_set_mac_addr(struct nlge_softc *sc);
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static void nlge_set_port_attribs(struct nlge_softc *,
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struct xlr_gmac_port *);
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static void nlge_mac_set_rx_mode(struct nlge_softc *sc);
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static void nlge_sgmii_init(struct nlge_softc *sc);
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static void nlge_start_locked(struct ifnet *ifp, struct nlge_softc *sc);
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@ -303,6 +305,10 @@ DRIVER_MODULE(miibus, nlge, miibus_driver, miibus_devclass, 0, 0);
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static uma_zone_t nl_tx_desc_zone;
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/* Tunables. */
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static int flow_classification = 0;
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TUNABLE_INT("hw.nlge.flow_classification", &flow_classification);
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static __inline void
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atomic_incr_long(unsigned long *addr)
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{
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@ -494,7 +500,7 @@ nlge_probe(device_t dev)
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sc = device_get_softc(dev);
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nlge_sc_init(sc, dev, port_info);
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nlge_port_disable(sc->id, sc->base, sc->port_type);
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nlge_port_disable(sc);
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return (0);
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}
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@ -531,8 +537,7 @@ nlge_detach(device_t dev)
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ifp = sc->nlge_if;
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if (device_is_attached(dev)) {
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ifp->if_drv_flags &= ~(IFF_DRV_OACTIVE | IFF_DRV_RUNNING);
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nlge_port_disable(sc->id, sc->base, sc->port_type);
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nlge_port_disable(sc);
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nlge_irq_fini(sc);
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ether_ifdetach(ifp);
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bus_generic_detach(dev);
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@ -567,7 +572,7 @@ nlge_init(void *addr)
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if (ifp->if_drv_flags & IFF_DRV_RUNNING)
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return;
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nlge_gmac_config_speed(sc, 0);
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nlge_gmac_config_speed(sc, 1);
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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nlge_port_enable(sc);
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@ -590,9 +595,33 @@ nlge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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sc = ifp->if_softc;
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error = 0;
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ifr = (struct ifreq *)data;
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switch(command) {
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case SIOCSIFFLAGS:
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NLGE_LOCK(sc);
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if (ifp->if_flags & IFF_UP) {
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if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
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nlge_init(sc);
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}
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if (ifp->if_flags & IFF_PROMISC &&
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!(sc->if_flags & IFF_PROMISC)) {
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sc->if_flags |= IFF_PROMISC;
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nlge_mac_set_rx_mode(sc);
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} else if (!(ifp->if_flags & IFF_PROMISC) &&
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sc->if_flags & IFF_PROMISC) {
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sc->if_flags &= IFF_PROMISC;
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nlge_mac_set_rx_mode(sc);
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}
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} else {
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if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
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nlge_port_disable(sc);
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}
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}
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sc->if_flags = ifp->if_flags;
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NLGE_UNLOCK(sc);
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error = 0;
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break;
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case SIOCSIFMEDIA:
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case SIOCGIFMEDIA:
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if (sc->mii_bus != NULL) {
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@ -601,9 +630,7 @@ nlge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
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command);
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}
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break;
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case SIOCSIFADDR:
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// intentional fall thru
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case SIOCSIFMTU:
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default:
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error = ether_ioctl(ifp, command, data);
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break;
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@ -805,6 +832,7 @@ nlge_rx(struct nlge_softc *sc, vm_paddr_t paddr, int len)
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}
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ifp = sc->nlge_if;
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/* align the data */
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m->m_data += BYTE_OFFSET;
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m->m_pkthdr.len = m->m_len = len;
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@ -1153,6 +1181,7 @@ nlna_config_pde(struct nlna_softc *sc)
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bucket_map |= (3ULL << bucket);
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}
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}
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NLGE_WRITE(sc->base, R_PDE_CLASS_0, (bucket_map & 0xffffffff));
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NLGE_WRITE(sc->base, R_PDE_CLASS_0 + 1, ((bucket_map >> 32) & 0xffffffff));
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@ -1188,6 +1217,7 @@ nlna_smp_update_pde(void *dummy __unused)
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continue;
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nlna_disable_ports(na_sc[i]);
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nlna_config_pde(na_sc[i]);
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nlna_config_translate_table(na_sc[i]);
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nlna_enable_ports(na_sc[i]);
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}
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}
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@ -1195,23 +1225,95 @@ nlna_smp_update_pde(void *dummy __unused)
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SYSINIT(nlna_smp_update_pde, SI_SUB_SMP, SI_ORDER_ANY, nlna_smp_update_pde,
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NULL);
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static void
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nlna_config_translate_table(struct nlna_softc *sc)
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{
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uint32_t cpu_mask;
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uint32_t val;
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int bkts[32]; /* one bucket is assumed for each cpu */
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int b1, b2, c1, c2, i, j, k;
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int use_bkt;
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if (!flow_classification)
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return;
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use_bkt = 1;
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if (smp_started)
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cpu_mask = xlr_hw_thread_mask;
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else
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return;
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printf("Using %s-based distribution\n", (use_bkt) ? "bucket" : "class");
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j = 0;
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for(i = 0; i < 32; i++) {
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if ((1 << i) & cpu_mask){
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/* for each cpu, mark the 4+threadid bucket */
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bkts[j] = ((i / 4) * 8) + (i % 4);
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j++;
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}
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}
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/*configure the 128 * 9 Translation table to send to available buckets*/
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k = 0;
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c1 = 3;
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c2 = 0;
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for(i = 0; i < 64; i++) {
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/* Get the next 2 pairs of (class, bucket):
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(c1, b1), (c2, b2).
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c1, c2 limited to {0, 1, 2, 3}
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i.e, the 4 classes defined by h/w
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b1, b2 limited to { bkts[i], where 0 <= i < j}
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i.e, the set of buckets computed in the
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above loop.
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*/
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c1 = (c1 + 1) & 3;
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c2 = (c1 + 1) & 3;
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b1 = bkts[k];
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k = (k + 1) % j;
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b2 = bkts[k];
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k = (k + 1) % j;
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PDEBUG("Translation table[%d] b1=%d b2=%d c1=%d c2=%d\n",
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i, b1, b2, c1, c2);
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val = ((c1 << 23) | (b1 << 17) | (use_bkt << 16) |
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(c2 << 7) | (b2 << 1) | (use_bkt << 0));
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NLGE_WRITE(sc->base, R_TRANSLATETABLE + i, val);
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c1 = c2;
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}
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}
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static void
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nlna_config_parser(struct nlna_softc *sc)
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{
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uint32_t val;
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/*
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* Mark it as no classification. The parser extract is gauranteed to
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* be zero with no classfication
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* Mark it as ETHERNET type.
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*/
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NLGE_WRITE(sc->base, R_L2TYPE_0, 0x00);
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NLGE_WRITE(sc->base, R_L2TYPE_0, 0x01);
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if (!flow_classification)
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return;
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/* Use 7bit CRChash for flow classification with 127 as CRC polynomial*/
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NLGE_WRITE(sc->base, R_PARSERCONFIGREG, ((0x7f << 8) | (1 << 1)));
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/* configure the parser : L2 Type is configured in the bootloader */
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/* extract IP: src, dest protocol */
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NLGE_WRITE(sc->base, R_L3CTABLE,
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(9 << 20) | (1 << 19) | (1 << 18) | (0x01 << 16) |
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(0x0800 << 0));
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NLGE_WRITE(sc->base, R_L3CTABLE + 1,
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(12 << 25) | (4 << 21) | (16 << 14) | (4 << 10));
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(9 << 25) | (1 << 21) | (12 << 14) | (4 << 10) | (16 << 4) | 4);
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/* Configure to extract SRC port and Dest port for TCP and UDP pkts */
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NLGE_WRITE(sc->base, R_L4CTABLE, 6);
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NLGE_WRITE(sc->base, R_L4CTABLE+2, 17);
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val = ((0 << 21) | (2 << 17) | (2 << 11) | (2 << 7));
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NLGE_WRITE(sc->base, R_L4CTABLE+1, val);
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NLGE_WRITE(sc->base, R_L4CTABLE+3, val);
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}
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static void
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@ -1352,14 +1454,11 @@ nlna_reset_ports(struct nlna_softc *sc, struct xlr_gmac_block_t *blk)
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static void
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nlna_disable_ports(struct nlna_softc *sc)
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{
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struct xlr_gmac_block_t *blk;
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xlr_reg_t *addr;
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int i;
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blk = device_get_ivars(sc->nlna_dev);
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for (i = 0; i < sc->num_ports; i++) {
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addr = xlr_io_mmio(blk->gmac_port[i].base_addr);
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nlge_port_disable(i, addr, blk->gmac_port[i].type);
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if (sc->child_sc[i] != NULL)
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nlge_port_disable(sc->child_sc[i]);
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}
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}
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@ -1398,9 +1497,17 @@ nlna_get_all_softc(device_t iodi_dev, struct nlna_softc **sc_vec,
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}
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static void
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nlge_port_disable(int id, xlr_reg_t *base, int port_type)
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nlge_port_disable(struct nlge_softc *sc)
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{
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struct ifnet *ifp;
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xlr_reg_t *base;
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uint32_t rd;
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int id, port_type;
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id = sc->id;
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port_type = sc->port_type;
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base = sc->base;
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ifp = sc->nlge_if;
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NLGE_UPDATE(base, R_RX_CONTROL, 0x0, 1 << O_RX_CONTROL__RxEnable);
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do {
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@ -1428,6 +1535,10 @@ nlge_port_disable(int id, xlr_reg_t *base, int port_type)
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default:
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panic("Unknown MAC type on port %d\n", id);
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}
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if (ifp) {
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ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
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}
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}
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static void
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@ -1465,6 +1576,26 @@ nlge_port_enable(struct nlge_softc *sc)
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}
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}
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static void
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nlge_mac_set_rx_mode(struct nlge_softc *sc)
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{
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uint32_t regval;
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regval = NLGE_READ(sc->base, R_MAC_FILTER_CONFIG);
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if (sc->if_flags & IFF_PROMISC) {
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regval |= (1 << O_MAC_FILTER_CONFIG__BROADCAST_EN) |
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(1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_MCAST_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN);
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} else {
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regval &= ~((1 << O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN) |
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(1 << O_MAC_FILTER_CONFIG__ALL_UCAST_EN));
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}
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NLGE_WRITE(sc->base, R_MAC_FILTER_CONFIG, regval);
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}
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static void
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nlge_sgmii_init(struct nlge_softc *sc)
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{
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@ -1559,7 +1690,7 @@ nlge_intr(void *arg)
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if (intr_status & 0x2410) {
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/* update link status for port */
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nlge_gmac_config_speed(port_sc, 0);
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nlge_gmac_config_speed(port_sc, 1);
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} else {
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printf("%s: Unsupported phy interrupt"
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" (0x%08x)\n",
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@ -1745,7 +1876,7 @@ nlge_if_init(struct nlge_softc *sc)
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ifp->if_softc = sc;
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if_initname(ifp, device_get_name(dev), device_get_unit(dev));
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ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
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ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_VLAN_HWTAGGING;
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ifp->if_capabilities = 0;
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ifp->if_capenable = ifp->if_capabilities;
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ifp->if_ioctl = nlge_ioctl;
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ifp->if_start = nlge_start;
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@ -1103,12 +1103,12 @@ struct nlge_port_set {
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* for a set of GMAC ports controlled by an NA is done from here.
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*/
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struct nlna_softc {
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device_t nlna_dev;
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device_t nlna_dev;
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uint32_t num_ports;
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int na_type;
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int mac_type;
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xlr_reg_t *base;
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uint32_t num_ports;
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int na_type;
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int mac_type;
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xlr_reg_t *base;
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struct callout tx_thr;
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struct fr_desc *frin_spill;
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@ -1135,19 +1135,20 @@ struct nlge_softc {
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mii.c:miibus_attach() */
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struct mii_data nlge_mii;
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struct nlge_port_set *mdio_pset;
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device_t nlge_dev;
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device_t nlge_dev;
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device_t mii_bus;
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xlr_reg_t *base;
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xlr_reg_t *mii_base;
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xlr_reg_t *pcs_addr;
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xlr_reg_t *serdes_addr;
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int port_type;
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xlr_reg_t *base;
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xlr_reg_t *mii_base;
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xlr_reg_t *pcs_addr;
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xlr_reg_t *serdes_addr;
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int port_type;
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int if_flags;
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xlr_mac_speed_t speed;
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xlr_mac_duplex_t duplex;
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xlr_mac_link_t link;
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xlr_mac_fc_t flow_ctrl;
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uint32_t id;
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uint32_t instance;
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uint32_t id;
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uint32_t instance;
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uint32_t phy_addr;
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uint32_t tx_bucket_id;
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uint8_t dev_addr[ETHER_ADDR_LEN];
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