mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-19 10:53:58 +00:00
Update llvm, clang, lld and lldb to release_39 branch r288513.
This commit is contained in:
Dimitry Andric
commit
4dcfa14438
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang391-import/; revision=309437
@ -20,11 +20,11 @@
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#include <ciso646> // So we can check the C++ standard lib macros.
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#include <functional>
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// We use std::call_once on all Unix platforms except for NetBSD with
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// libstdc++. That platform has a bug they are working to fix, and they'll
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// remove the NetBSD checks once fixed.
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#if defined(LLVM_ON_UNIX) && \
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!(defined(__NetBSD__) && !defined(_LIBCPP_VERSION)) && !defined(__ppc__)
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// std::call_once from libc++ is used on all Unix platforms. Other
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// implementations like libstdc++ are known to have problems on NetBSD,
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// OpenBSD and PowerPC.
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#if defined(LLVM_ON_UNIX) && (defined(_LIBCPP_VERSION) || \
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!(defined(__NetBSD__) || defined(__OpenBSD__) || defined(__ppc__)))
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#define LLVM_THREADING_USE_STD_CALL_ONCE 1
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#else
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#define LLVM_THREADING_USE_STD_CALL_ONCE 0
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@ -2185,24 +2185,29 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
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// options. This is a trivially-generalized version of the code from
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// Hacker's Delight (itself derived from Knuth's Algorithm M from section
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// 4.3.1).
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SDValue Mask =
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DAG.getConstant(APInt::getLowBitsSet(NVT.getSizeInBits(),
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NVT.getSizeInBits() >> 1), dl, NVT);
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unsigned Bits = NVT.getSizeInBits();
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unsigned HalfBits = Bits >> 1;
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SDValue Mask = DAG.getConstant(APInt::getLowBitsSet(Bits, HalfBits), dl,
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NVT);
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SDValue LLL = DAG.getNode(ISD::AND, dl, NVT, LL, Mask);
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SDValue RLL = DAG.getNode(ISD::AND, dl, NVT, RL, Mask);
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SDValue T = DAG.getNode(ISD::MUL, dl, NVT, LLL, RLL);
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SDValue TL = DAG.getNode(ISD::AND, dl, NVT, T, Mask);
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SDValue Shift =
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DAG.getConstant(NVT.getSizeInBits() >> 1, dl,
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TLI.getShiftAmountTy(NVT, DAG.getDataLayout()));
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EVT ShiftAmtTy = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
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if (APInt::getMaxValue(ShiftAmtTy.getSizeInBits()).ult(HalfBits)) {
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// The type from TLI is too small to fit the shift amount we want.
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// Override it with i32. The shift will have to be legalized.
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ShiftAmtTy = MVT::i32;
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}
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SDValue Shift = DAG.getConstant(HalfBits, dl, ShiftAmtTy);
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SDValue TH = DAG.getNode(ISD::SRL, dl, NVT, T, Shift);
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SDValue LLH = DAG.getNode(ISD::SRL, dl, NVT, LL, Shift);
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SDValue RLH = DAG.getNode(ISD::SRL, dl, NVT, RL, Shift);
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SDValue U = DAG.getNode(ISD::ADD, dl, NVT,
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DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TL);
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DAG.getNode(ISD::MUL, dl, NVT, LLH, RLL), TH);
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SDValue UL = DAG.getNode(ISD::AND, dl, NVT, U, Mask);
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SDValue UH = DAG.getNode(ISD::SRL, dl, NVT, U, Shift);
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@ -2211,14 +2216,14 @@ void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
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SDValue VH = DAG.getNode(ISD::SRL, dl, NVT, V, Shift);
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SDValue W = DAG.getNode(ISD::ADD, dl, NVT,
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DAG.getNode(ISD::MUL, dl, NVT, LL, RL),
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DAG.getNode(ISD::MUL, dl, NVT, LLH, RLH),
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DAG.getNode(ISD::ADD, dl, NVT, UH, VH));
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Lo = DAG.getNode(ISD::ADD, dl, NVT, TH,
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Lo = DAG.getNode(ISD::ADD, dl, NVT, TL,
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DAG.getNode(ISD::SHL, dl, NVT, V, Shift));
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Hi = DAG.getNode(ISD::ADD, dl, NVT, W,
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DAG.getNode(ISD::ADD, dl, NVT,
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DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
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DAG.getNode(ISD::MUL, dl, NVT, RH, LL),
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DAG.getNode(ISD::MUL, dl, NVT, RL, LH)));
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return;
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}
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@ -2203,7 +2203,8 @@ void SIInstrInfo::legalizeOperandsSMRD(MachineRegisterInfo &MRI,
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}
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void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
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MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
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MachineFunction &MF = *MI.getParent()->getParent();
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MachineRegisterInfo &MRI = MF.getRegInfo();
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// Legalize VOP2
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if (isVOP2(MI) || isVOPC(MI)) {
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@ -2321,8 +2322,14 @@ void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
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return;
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}
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// Legalize MIMG
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if (isMIMG(MI)) {
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// Legalize MIMG and MUBUF/MTBUF for shaders.
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//
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// Shaders only generate MUBUF/MTBUF instructions via intrinsics or via
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// scratch memory access. In both cases, the legalization never involves
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// conversion to the addr64 form.
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if (isMIMG(MI) ||
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(AMDGPU::isShader(MF.getFunction()->getCallingConv()) &&
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(isMUBUF(MI) || isMTBUF(MI)))) {
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MachineOperand *SRsrc = getNamedOperand(MI, AMDGPU::OpName::srsrc);
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if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
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unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
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@ -2337,9 +2344,10 @@ void SIInstrInfo::legalizeOperands(MachineInstr &MI) const {
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return;
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}
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// Legalize MUBUF* instructions
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// Legalize MUBUF* instructions by converting to addr64 form.
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// FIXME: If we start using the non-addr64 instructions for compute, we
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// may need to legalize them here.
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// may need to legalize them as above. This especially applies to the
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// buffer_load_format_* variants and variants with idxen (or bothen).
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int SRsrcIdx =
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AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
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if (SRsrcIdx != -1) {
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@ -2029,6 +2029,7 @@ def SI_RETURN : PseudoInstSI <
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let hasSideEffects = 1;
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let SALU = 1;
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let hasNoSchedulingInfo = 1;
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let DisableWQM = 1;
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}
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let Uses = [EXEC], Defs = [EXEC, VCC, M0],
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@ -219,13 +219,6 @@ char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
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markInstruction(MI, Flags, Worklist);
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GlobalFlags |= Flags;
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}
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if (WQMOutputs && MBB.succ_empty()) {
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// This is a prolog shader. Make sure we go back to exact mode at the end.
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Blocks[&MBB].OutNeeds = StateExact;
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Worklist.push_back(&MBB);
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GlobalFlags |= StateExact;
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}
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}
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return GlobalFlags;
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@ -634,7 +634,7 @@ static bool canRewriteGEPAsOffset(Value *Start, Value *Base,
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}
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if (!isa<IntToPtrInst>(V) && !isa<PtrToIntInst>(V) &&
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!isa<GEPOperator>(V) && !isa<PHINode>(V))
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!isa<GetElementPtrInst>(V) && !isa<PHINode>(V))
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// We've found some value that we can't explore which is different from
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// the base. Therefore we can't do this transformation.
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return false;
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@ -579,6 +579,13 @@ static Instruction *unpackLoadToAggregate(InstCombiner &IC, LoadInst &LI) {
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UndefValue::get(T), NewLoad, 0, Name));
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}
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// Bail out if the array is too large. Ideally we would like to optimize
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// arrays of arbitrary size but this has a terrible impact on compile time.
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// The threshold here is chosen arbitrarily, maybe needs a little bit of
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// tuning.
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if (NumElements > 1024)
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return nullptr;
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const DataLayout &DL = IC.getDataLayout();
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auto EltSize = DL.getTypeAllocSize(ET);
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auto Align = LI.getAlignment();
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@ -1081,6 +1088,13 @@ static bool unpackStoreToAggregate(InstCombiner &IC, StoreInst &SI) {
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return true;
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}
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// Bail out if the array is too large. Ideally we would like to optimize
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// arrays of arbitrary size but this has a terrible impact on compile time.
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// The threshold here is chosen arbitrarily, maybe needs a little bit of
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// tuning.
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if (NumElements > 1024)
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return false;
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const DataLayout &DL = IC.getDataLayout();
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auto EltSize = DL.getTypeAllocSize(AT->getElementType());
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auto Align = SI.getAlignment();
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@ -2024,14 +2024,20 @@ static bool FoldTwoEntryPHINode(PHINode *PN, const TargetTransformInfo &TTI,
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// Move all 'aggressive' instructions, which are defined in the
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// conditional parts of the if's up to the dominating block.
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if (IfBlock1)
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if (IfBlock1) {
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for (auto &I : *IfBlock1)
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I.dropUnknownNonDebugMetadata();
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DomBlock->getInstList().splice(InsertPt->getIterator(),
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IfBlock1->getInstList(), IfBlock1->begin(),
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IfBlock1->getTerminator()->getIterator());
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if (IfBlock2)
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}
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if (IfBlock2) {
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for (auto &I : *IfBlock2)
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I.dropUnknownNonDebugMetadata();
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DomBlock->getInstList().splice(InsertPt->getIterator(),
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IfBlock2->getInstList(), IfBlock2->begin(),
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IfBlock2->getTerminator()->getIterator());
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}
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while (PHINode *PN = dyn_cast<PHINode>(BB->begin())) {
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// Change the PHI node into a select instruction.
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@ -7621,6 +7621,8 @@ def err_invalid_neon_type_code : Error<
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"incompatible constant for this __builtin_neon function">;
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def err_argument_invalid_range : Error<
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"argument should be a value from %0 to %1">;
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def err_argument_not_multiple : Error<
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"argument should be a multiple of %0">;
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def warn_neon_vector_initializer_non_portable : Warning<
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"vector initializers are not compatible with NEON intrinsics in big endian "
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"mode">, InGroup<DiagGroup<"nonportable-vector-initialization">>;
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@ -9417,6 +9417,8 @@ class Sema {
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llvm::APSInt &Result);
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bool SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum,
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int Low, int High);
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bool SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum,
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unsigned Multiple);
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bool SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,
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int ArgNum, unsigned ExpectedFieldNum,
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bool AllowName);
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@ -2081,21 +2081,23 @@ class AMDGPUTargetInfo final : public TargetInfo {
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static GPUKind parseAMDGCNName(StringRef Name) {
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return llvm::StringSwitch<GPUKind>(Name)
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.Case("tahiti", GK_SOUTHERN_ISLANDS)
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.Case("pitcairn", GK_SOUTHERN_ISLANDS)
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.Case("verde", GK_SOUTHERN_ISLANDS)
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.Case("oland", GK_SOUTHERN_ISLANDS)
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.Case("hainan", GK_SOUTHERN_ISLANDS)
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.Case("bonaire", GK_SEA_ISLANDS)
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.Case("kabini", GK_SEA_ISLANDS)
|
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.Case("kaveri", GK_SEA_ISLANDS)
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.Case("hawaii", GK_SEA_ISLANDS)
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.Case("mullins", GK_SEA_ISLANDS)
|
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.Case("tonga", GK_VOLCANIC_ISLANDS)
|
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.Case("iceland", GK_VOLCANIC_ISLANDS)
|
||||
.Case("carrizo", GK_VOLCANIC_ISLANDS)
|
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.Case("fiji", GK_VOLCANIC_ISLANDS)
|
||||
.Case("stoney", GK_VOLCANIC_ISLANDS)
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.Case("tahiti", GK_SOUTHERN_ISLANDS)
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.Case("pitcairn", GK_SOUTHERN_ISLANDS)
|
||||
.Case("verde", GK_SOUTHERN_ISLANDS)
|
||||
.Case("oland", GK_SOUTHERN_ISLANDS)
|
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.Case("hainan", GK_SOUTHERN_ISLANDS)
|
||||
.Case("bonaire", GK_SEA_ISLANDS)
|
||||
.Case("kabini", GK_SEA_ISLANDS)
|
||||
.Case("kaveri", GK_SEA_ISLANDS)
|
||||
.Case("hawaii", GK_SEA_ISLANDS)
|
||||
.Case("mullins", GK_SEA_ISLANDS)
|
||||
.Case("tonga", GK_VOLCANIC_ISLANDS)
|
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.Case("iceland", GK_VOLCANIC_ISLANDS)
|
||||
.Case("carrizo", GK_VOLCANIC_ISLANDS)
|
||||
.Case("fiji", GK_VOLCANIC_ISLANDS)
|
||||
.Case("stoney", GK_VOLCANIC_ISLANDS)
|
||||
.Case("polaris10", GK_VOLCANIC_ISLANDS)
|
||||
.Case("polaris11", GK_VOLCANIC_ISLANDS)
|
||||
.Default(GK_NONE);
|
||||
}
|
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|
||||
|
||||
@ -1767,17 +1767,11 @@ void CodeGenFunction::EmitOMPOuterLoop(bool DynamicOrOrdered, bool IsMonotonic,
|
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EmitBlock(LoopExit.getBlock());
|
||||
|
||||
// Tell the runtime we are done.
|
||||
SourceLocation ELoc = S.getLocEnd();
|
||||
auto &&CodeGen = [DynamicOrOrdered, ELoc](CodeGenFunction &CGF) {
|
||||
auto &&CodeGen = [DynamicOrOrdered, &S](CodeGenFunction &CGF) {
|
||||
if (!DynamicOrOrdered)
|
||||
CGF.CGM.getOpenMPRuntime().emitForStaticFinish(CGF, ELoc);
|
||||
CGF.CGM.getOpenMPRuntime().emitForStaticFinish(CGF, S.getLocEnd());
|
||||
};
|
||||
CodeGen(*this);
|
||||
|
||||
OpenMPDirectiveKind DKind = S.getDirectiveKind();
|
||||
if (DKind == OMPD_for || DKind == OMPD_parallel_for ||
|
||||
DKind == OMPD_distribute_parallel_for)
|
||||
OMPCancelStack.back().CodeGen = CodeGen;
|
||||
OMPCancelStack.emitExit(*this, S.getDirectiveKind(), CodeGen);
|
||||
}
|
||||
|
||||
void CodeGenFunction::EmitOMPForOuterLoop(
|
||||
@ -1889,11 +1883,12 @@ void CodeGenFunction::EmitOMPDistributeOuterLoop(
|
||||
void CodeGenFunction::EmitOMPDistributeParallelForDirective(
|
||||
const OMPDistributeParallelForDirective &S) {
|
||||
OMPLexicalScope Scope(*this, S, /*AsInlined=*/true);
|
||||
OMPCancelStackRAII CancelRegion(*this);
|
||||
CGM.getOpenMPRuntime().emitInlinedDirective(
|
||||
*this, OMPD_distribute_parallel_for,
|
||||
[&S](CodeGenFunction &CGF, PrePostActionTy &) {
|
||||
OMPLoopScope PreInitScope(CGF, S);
|
||||
OMPCancelStackRAII CancelRegion(CGF, OMPD_distribute_parallel_for,
|
||||
/*HasCancel=*/false);
|
||||
CGF.EmitStmt(
|
||||
cast<CapturedStmt>(S.getAssociatedStmt())->getCapturedStmt());
|
||||
});
|
||||
@ -2082,15 +2077,10 @@ bool CodeGenFunction::EmitOMPWorksharingLoop(const OMPLoopDirective &S) {
|
||||
[](CodeGenFunction &) {});
|
||||
EmitBlock(LoopExit.getBlock());
|
||||
// Tell the runtime we are done.
|
||||
SourceLocation ELoc = S.getLocEnd();
|
||||
auto &&CodeGen = [ELoc](CodeGenFunction &CGF) {
|
||||
CGF.CGM.getOpenMPRuntime().emitForStaticFinish(CGF, ELoc);
|
||||
auto &&CodeGen = [&S](CodeGenFunction &CGF) {
|
||||
CGF.CGM.getOpenMPRuntime().emitForStaticFinish(CGF, S.getLocEnd());
|
||||
};
|
||||
CodeGen(*this);
|
||||
OpenMPDirectiveKind DKind = S.getDirectiveKind();
|
||||
if (DKind == OMPD_for || DKind == OMPD_parallel_for ||
|
||||
DKind == OMPD_distribute_parallel_for)
|
||||
OMPCancelStack.back().CodeGen = CodeGen;
|
||||
OMPCancelStack.emitExit(*this, S.getDirectiveKind(), CodeGen);
|
||||
} else {
|
||||
const bool IsMonotonic =
|
||||
Ordered || ScheduleKind.Schedule == OMPC_SCHEDULE_static ||
|
||||
@ -2140,11 +2130,11 @@ void CodeGenFunction::EmitOMPForDirective(const OMPForDirective &S) {
|
||||
bool HasLastprivates = false;
|
||||
auto &&CodeGen = [&S, &HasLastprivates](CodeGenFunction &CGF,
|
||||
PrePostActionTy &) {
|
||||
OMPCancelStackRAII CancelRegion(CGF, OMPD_for, S.hasCancel());
|
||||
HasLastprivates = CGF.EmitOMPWorksharingLoop(S);
|
||||
};
|
||||
{
|
||||
OMPLexicalScope Scope(*this, S, /*AsInlined=*/true);
|
||||
OMPCancelStackRAII CancelRegion(*this);
|
||||
CGM.getOpenMPRuntime().emitInlinedDirective(*this, OMPD_for, CodeGen,
|
||||
S.hasCancel());
|
||||
}
|
||||
@ -2187,7 +2177,6 @@ void CodeGenFunction::EmitSections(const OMPExecutableDirective &S) {
|
||||
bool HasLastprivates = false;
|
||||
auto &&CodeGen = [&S, Stmt, CS, &HasLastprivates](CodeGenFunction &CGF,
|
||||
PrePostActionTy &) {
|
||||
OMPCancelStackRAII CancelRegion(CGF);
|
||||
auto &C = CGF.CGM.getContext();
|
||||
auto KmpInt32Ty = C.getIntTypeForBitwidth(/*DestWidth=*/32, /*Signed=*/1);
|
||||
// Emit helper vars inits.
|
||||
@ -2282,12 +2271,10 @@ void CodeGenFunction::EmitSections(const OMPExecutableDirective &S) {
|
||||
CGF.EmitOMPInnerLoop(S, /*RequiresCleanup=*/false, &Cond, &Inc, BodyGen,
|
||||
[](CodeGenFunction &) {});
|
||||
// Tell the runtime we are done.
|
||||
SourceLocation ELoc = S.getLocEnd();
|
||||
auto &&FinalCodeGen = [ELoc](CodeGenFunction &CGF) {
|
||||
CGF.CGM.getOpenMPRuntime().emitForStaticFinish(CGF, ELoc);
|
||||
auto &&CodeGen = [&S](CodeGenFunction &CGF) {
|
||||
CGF.CGM.getOpenMPRuntime().emitForStaticFinish(CGF, S.getLocEnd());
|
||||
};
|
||||
FinalCodeGen(CGF);
|
||||
CGF.OMPCancelStack.back().CodeGen = FinalCodeGen;
|
||||
CGF.OMPCancelStack.emitExit(CGF, S.getDirectiveKind(), CodeGen);
|
||||
CGF.EmitOMPReductionClauseFinal(S);
|
||||
// Emit post-update of the reduction variables if IsLastIter != 0.
|
||||
emitPostUpdateForReductionClause(
|
||||
@ -2309,6 +2296,7 @@ void CodeGenFunction::EmitSections(const OMPExecutableDirective &S) {
|
||||
HasCancel = OSD->hasCancel();
|
||||
else if (auto *OPSD = dyn_cast<OMPParallelSectionsDirective>(&S))
|
||||
HasCancel = OPSD->hasCancel();
|
||||
OMPCancelStackRAII CancelRegion(*this, S.getDirectiveKind(), HasCancel);
|
||||
CGM.getOpenMPRuntime().emitInlinedDirective(*this, OMPD_sections, CodeGen,
|
||||
HasCancel);
|
||||
// Emit barrier for lastprivates only if 'sections' directive has 'nowait'
|
||||
@ -2412,7 +2400,7 @@ void CodeGenFunction::EmitOMPParallelForDirective(
|
||||
// Emit directive as a combined directive that consists of two implicit
|
||||
// directives: 'parallel' with 'for' directive.
|
||||
auto &&CodeGen = [&S](CodeGenFunction &CGF, PrePostActionTy &) {
|
||||
OMPCancelStackRAII CancelRegion(CGF);
|
||||
OMPCancelStackRAII CancelRegion(CGF, OMPD_parallel_for, S.hasCancel());
|
||||
CGF.EmitOMPWorksharingLoop(S);
|
||||
};
|
||||
emitCommonOMPParallelDirective(*this, S, OMPD_for, CodeGen);
|
||||
@ -3412,14 +3400,14 @@ void CodeGenFunction::EmitOMPCancelDirective(const OMPCancelDirective &S) {
|
||||
|
||||
CodeGenFunction::JumpDest
|
||||
CodeGenFunction::getOMPCancelDestination(OpenMPDirectiveKind Kind) {
|
||||
if (Kind == OMPD_parallel || Kind == OMPD_task)
|
||||
if (Kind == OMPD_parallel || Kind == OMPD_task ||
|
||||
Kind == OMPD_target_parallel)
|
||||
return ReturnBlock;
|
||||
assert(Kind == OMPD_for || Kind == OMPD_section || Kind == OMPD_sections ||
|
||||
Kind == OMPD_parallel_sections || Kind == OMPD_parallel_for ||
|
||||
Kind == OMPD_distribute_parallel_for);
|
||||
if (!OMPCancelStack.back().ExitBlock.isValid())
|
||||
OMPCancelStack.back().ExitBlock = getJumpDestInCurrentScope("cancel.exit");
|
||||
return OMPCancelStack.back().ExitBlock;
|
||||
Kind == OMPD_distribute_parallel_for ||
|
||||
Kind == OMPD_target_parallel_for);
|
||||
return OMPCancelStack.getExitBlock();
|
||||
}
|
||||
|
||||
// Generate the instructions for '#pragma omp target data' directive.
|
||||
|
||||
@ -965,33 +965,92 @@ class CodeGenFunction : public CodeGenTypeCache {
|
||||
};
|
||||
SmallVector<BreakContinue, 8> BreakContinueStack;
|
||||
|
||||
/// Data for exit block for proper support of OpenMP cancellation constructs.
|
||||
struct OMPCancel {
|
||||
JumpDest ExitBlock;
|
||||
llvm::function_ref<void(CodeGenFunction &CGF)> CodeGen;
|
||||
OMPCancel() : CodeGen([](CodeGenFunction &CGF) {}) {}
|
||||
/// Handles cancellation exit points in OpenMP-related constructs.
|
||||
class OpenMPCancelExitStack {
|
||||
/// Tracks cancellation exit point and join point for cancel-related exit
|
||||
/// and normal exit.
|
||||
struct CancelExit {
|
||||
CancelExit() = default;
|
||||
CancelExit(OpenMPDirectiveKind Kind, JumpDest ExitBlock,
|
||||
JumpDest ContBlock)
|
||||
: Kind(Kind), ExitBlock(ExitBlock), ContBlock(ContBlock) {}
|
||||
OpenMPDirectiveKind Kind = OMPD_unknown;
|
||||
/// true if the exit block has been emitted already by the special
|
||||
/// emitExit() call, false if the default codegen is used.
|
||||
bool HasBeenEmitted = false;
|
||||
JumpDest ExitBlock;
|
||||
JumpDest ContBlock;
|
||||
};
|
||||
|
||||
SmallVector<CancelExit, 8> Stack;
|
||||
|
||||
public:
|
||||
OpenMPCancelExitStack() : Stack(1) {}
|
||||
~OpenMPCancelExitStack() = default;
|
||||
/// Fetches the exit block for the current OpenMP construct.
|
||||
JumpDest getExitBlock() const { return Stack.back().ExitBlock; }
|
||||
/// Emits exit block with special codegen procedure specific for the related
|
||||
/// OpenMP construct + emits code for normal construct cleanup.
|
||||
void emitExit(CodeGenFunction &CGF, OpenMPDirectiveKind Kind,
|
||||
const llvm::function_ref<void(CodeGenFunction &)> &CodeGen) {
|
||||
if (Stack.back().Kind == Kind && getExitBlock().isValid()) {
|
||||
assert(CGF.getOMPCancelDestination(Kind).isValid());
|
||||
assert(CGF.HaveInsertPoint());
|
||||
assert(!Stack.back().HasBeenEmitted);
|
||||
auto IP = CGF.Builder.saveAndClearIP();
|
||||
CGF.EmitBlock(Stack.back().ExitBlock.getBlock());
|
||||
CodeGen(CGF);
|
||||
CGF.EmitBranchThroughCleanup(Stack.back().ContBlock);
|
||||
CGF.Builder.restoreIP(IP);
|
||||
Stack.back().HasBeenEmitted = true;
|
||||
}
|
||||
CodeGen(CGF);
|
||||
}
|
||||
/// Enter the cancel supporting \a Kind construct.
|
||||
/// \param Kind OpenMP directive that supports cancel constructs.
|
||||
/// \param HasCancel true, if the construct has inner cancel directive,
|
||||
/// false otherwise.
|
||||
void enter(CodeGenFunction &CGF, OpenMPDirectiveKind Kind, bool HasCancel) {
|
||||
Stack.push_back({Kind,
|
||||
HasCancel ? CGF.getJumpDestInCurrentScope("cancel.exit")
|
||||
: JumpDest(),
|
||||
HasCancel ? CGF.getJumpDestInCurrentScope("cancel.cont")
|
||||
: JumpDest()});
|
||||
}
|
||||
/// Emits default exit point for the cancel construct (if the special one
|
||||
/// has not be used) + join point for cancel/normal exits.
|
||||
void exit(CodeGenFunction &CGF) {
|
||||
if (getExitBlock().isValid()) {
|
||||
assert(CGF.getOMPCancelDestination(Stack.back().Kind).isValid());
|
||||
bool HaveIP = CGF.HaveInsertPoint();
|
||||
if (!Stack.back().HasBeenEmitted) {
|
||||
if (HaveIP)
|
||||
CGF.EmitBranchThroughCleanup(Stack.back().ContBlock);
|
||||
CGF.EmitBlock(Stack.back().ExitBlock.getBlock());
|
||||
CGF.EmitBranchThroughCleanup(Stack.back().ContBlock);
|
||||
}
|
||||
CGF.EmitBlock(Stack.back().ContBlock.getBlock());
|
||||
if (!HaveIP) {
|
||||
CGF.Builder.CreateUnreachable();
|
||||
CGF.Builder.ClearInsertionPoint();
|
||||
}
|
||||
}
|
||||
Stack.pop_back();
|
||||
}
|
||||
};
|
||||
SmallVector<OMPCancel, 8> OMPCancelStack;
|
||||
OpenMPCancelExitStack OMPCancelStack;
|
||||
|
||||
/// Controls insertion of cancellation exit blocks in worksharing constructs.
|
||||
class OMPCancelStackRAII {
|
||||
CodeGenFunction &CGF;
|
||||
|
||||
public:
|
||||
OMPCancelStackRAII(CodeGenFunction &CGF) : CGF(CGF) {
|
||||
CGF.OMPCancelStack.push_back({});
|
||||
}
|
||||
~OMPCancelStackRAII() {
|
||||
if (CGF.HaveInsertPoint() &&
|
||||
CGF.OMPCancelStack.back().ExitBlock.isValid()) {
|
||||
auto CJD = CGF.getJumpDestInCurrentScope("cancel.cont");
|
||||
CGF.EmitBranchThroughCleanup(CJD);
|
||||
CGF.EmitBlock(CGF.OMPCancelStack.back().ExitBlock.getBlock());
|
||||
CGF.OMPCancelStack.back().CodeGen(CGF);
|
||||
CGF.EmitBranchThroughCleanup(CJD);
|
||||
CGF.EmitBlock(CJD.getBlock());
|
||||
}
|
||||
OMPCancelStackRAII(CodeGenFunction &CGF, OpenMPDirectiveKind Kind,
|
||||
bool HasCancel)
|
||||
: CGF(CGF) {
|
||||
CGF.OMPCancelStack.enter(CGF, Kind, HasCancel);
|
||||
}
|
||||
~OMPCancelStackRAII() { CGF.OMPCancelStack.exit(CGF); }
|
||||
};
|
||||
|
||||
CodeGenPGO PGO;
|
||||
|
||||
583
contrib/llvm/tools/clang/lib/Headers/msa.h
Normal file
583
contrib/llvm/tools/clang/lib/Headers/msa.h
Normal file
@ -0,0 +1,583 @@
|
||||
/*===---- msa.h - MIPS MSA intrinsics --------------------------------------===
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
* of this software and associated documentation files (the "Software"), to deal
|
||||
* in the Software without restriction, including without limitation the rights
|
||||
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
* copies of the Software, and to permit persons to whom the Software is
|
||||
* furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
|
||||
* THE SOFTWARE.
|
||||
*
|
||||
*===-----------------------------------------------------------------------===
|
||||
*/
|
||||
|
||||
#ifndef _MSA_H
|
||||
#define _MSA_H 1
|
||||
|
||||
#if defined(__mips_msa)
|
||||
typedef signed char v16i8 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef signed char v16i8_b __attribute__((vector_size(16), aligned(1)));
|
||||
typedef unsigned char v16u8 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef unsigned char v16u8_b __attribute__((vector_size(16), aligned(1)));
|
||||
typedef short v8i16 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef short v8i16_h __attribute__((vector_size(16), aligned(2)));
|
||||
typedef unsigned short v8u16 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef unsigned short v8u16_h __attribute__((vector_size(16), aligned(2)));
|
||||
typedef int v4i32 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef int v4i32_w __attribute__((vector_size(16), aligned(4)));
|
||||
typedef unsigned int v4u32 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef unsigned int v4u32_w __attribute__((vector_size(16), aligned(4)));
|
||||
typedef long long v2i64 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef long long v2i64_d __attribute__((vector_size(16), aligned(8)));
|
||||
typedef unsigned long long v2u64 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef unsigned long long v2u64_d __attribute__((vector_size(16), aligned(8)));
|
||||
typedef float v4f32 __attribute__((vector_size(16), aligned(16)));
|
||||
typedef float v4f32_w __attribute__((vector_size(16), aligned(4)));
|
||||
typedef double v2f64 __attribute__ ((vector_size(16), aligned(16)));
|
||||
typedef double v2f64_d __attribute__ ((vector_size(16), aligned(8)));
|
||||
|
||||
#define __msa_sll_b __builtin_msa_sll_b
|
||||
#define __msa_sll_h __builtin_msa_sll_h
|
||||
#define __msa_sll_w __builtin_msa_sll_w
|
||||
#define __msa_sll_d __builtin_msa_sll_d
|
||||
#define __msa_slli_b __builtin_msa_slli_b
|
||||
#define __msa_slli_h __builtin_msa_slli_h
|
||||
#define __msa_slli_w __builtin_msa_slli_w
|
||||
#define __msa_slli_d __builtin_msa_slli_d
|
||||
#define __msa_sra_b __builtin_msa_sra_b
|
||||
#define __msa_sra_h __builtin_msa_sra_h
|
||||
#define __msa_sra_w __builtin_msa_sra_w
|
||||
#define __msa_sra_d __builtin_msa_sra_d
|
||||
#define __msa_srai_b __builtin_msa_srai_b
|
||||
#define __msa_srai_h __builtin_msa_srai_h
|
||||
#define __msa_srai_w __builtin_msa_srai_w
|
||||
#define __msa_srai_d __builtin_msa_srai_d
|
||||
#define __msa_srar_b __builtin_msa_srar_b
|
||||
#define __msa_srar_h __builtin_msa_srar_h
|
||||
#define __msa_srar_w __builtin_msa_srar_w
|
||||
#define __msa_srar_d __builtin_msa_srar_d
|
||||
#define __msa_srari_b __builtin_msa_srari_b
|
||||
#define __msa_srari_h __builtin_msa_srari_h
|
||||
#define __msa_srari_w __builtin_msa_srari_w
|
||||
#define __msa_srari_d __builtin_msa_srari_d
|
||||
#define __msa_srl_b __builtin_msa_srl_b
|
||||
#define __msa_srl_h __builtin_msa_srl_h
|
||||
#define __msa_srl_w __builtin_msa_srl_w
|
||||
#define __msa_srl_d __builtin_msa_srl_d
|
||||
#define __msa_srli_b __builtin_msa_srli_b
|
||||
#define __msa_srli_h __builtin_msa_srli_h
|
||||
#define __msa_srli_w __builtin_msa_srli_w
|
||||
#define __msa_srli_d __builtin_msa_srli_d
|
||||
#define __msa_srlr_b __builtin_msa_srlr_b
|
||||
#define __msa_srlr_h __builtin_msa_srlr_h
|
||||
#define __msa_srlr_w __builtin_msa_srlr_w
|
||||
#define __msa_srlr_d __builtin_msa_srlr_d
|
||||
#define __msa_srlri_b __builtin_msa_srlri_b
|
||||
#define __msa_srlri_h __builtin_msa_srlri_h
|
||||
#define __msa_srlri_w __builtin_msa_srlri_w
|
||||
#define __msa_srlri_d __builtin_msa_srlri_d
|
||||
#define __msa_bclr_b __builtin_msa_bclr_b
|
||||
#define __msa_bclr_h __builtin_msa_bclr_h
|
||||
#define __msa_bclr_w __builtin_msa_bclr_w
|
||||
#define __msa_bclr_d __builtin_msa_bclr_d
|
||||
#define __msa_bclri_b __builtin_msa_bclri_b
|
||||
#define __msa_bclri_h __builtin_msa_bclri_h
|
||||
#define __msa_bclri_w __builtin_msa_bclri_w
|
||||
#define __msa_bclri_d __builtin_msa_bclri_d
|
||||
#define __msa_bset_b __builtin_msa_bset_b
|
||||
#define __msa_bset_h __builtin_msa_bset_h
|
||||
#define __msa_bset_w __builtin_msa_bset_w
|
||||
#define __msa_bset_d __builtin_msa_bset_d
|
||||
#define __msa_bseti_b __builtin_msa_bseti_b
|
||||
#define __msa_bseti_h __builtin_msa_bseti_h
|
||||
#define __msa_bseti_w __builtin_msa_bseti_w
|
||||
#define __msa_bseti_d __builtin_msa_bseti_d
|
||||
#define __msa_bneg_b __builtin_msa_bneg_b
|
||||
#define __msa_bneg_h __builtin_msa_bneg_h
|
||||
#define __msa_bneg_w __builtin_msa_bneg_w
|
||||
#define __msa_bneg_d __builtin_msa_bneg_d
|
||||
#define __msa_bnegi_b __builtin_msa_bnegi_b
|
||||
#define __msa_bnegi_h __builtin_msa_bnegi_h
|
||||
#define __msa_bnegi_w __builtin_msa_bnegi_w
|
||||
#define __msa_bnegi_d __builtin_msa_bnegi_d
|
||||
#define __msa_binsl_b __builtin_msa_binsl_b
|
||||
#define __msa_binsl_h __builtin_msa_binsl_h
|
||||
#define __msa_binsl_w __builtin_msa_binsl_w
|
||||
#define __msa_binsl_d __builtin_msa_binsl_d
|
||||
#define __msa_binsli_b __builtin_msa_binsli_b
|
||||
#define __msa_binsli_h __builtin_msa_binsli_h
|
||||
#define __msa_binsli_w __builtin_msa_binsli_w
|
||||
#define __msa_binsli_d __builtin_msa_binsli_d
|
||||
#define __msa_binsr_b __builtin_msa_binsr_b
|
||||
#define __msa_binsr_h __builtin_msa_binsr_h
|
||||
#define __msa_binsr_w __builtin_msa_binsr_w
|
||||
#define __msa_binsr_d __builtin_msa_binsr_d
|
||||
#define __msa_binsri_b __builtin_msa_binsri_b
|
||||
#define __msa_binsri_h __builtin_msa_binsri_h
|
||||
#define __msa_binsri_w __builtin_msa_binsri_w
|
||||
#define __msa_binsri_d __builtin_msa_binsri_d
|
||||
#define __msa_addv_b __builtin_msa_addv_b
|
||||
#define __msa_addv_h __builtin_msa_addv_h
|
||||
#define __msa_addv_w __builtin_msa_addv_w
|
||||
#define __msa_addv_d __builtin_msa_addv_d
|
||||
#define __msa_addvi_b __builtin_msa_addvi_b
|
||||
#define __msa_addvi_h __builtin_msa_addvi_h
|
||||
#define __msa_addvi_w __builtin_msa_addvi_w
|
||||
#define __msa_addvi_d __builtin_msa_addvi_d
|
||||
#define __msa_subv_b __builtin_msa_subv_b
|
||||
#define __msa_subv_h __builtin_msa_subv_h
|
||||
#define __msa_subv_w __builtin_msa_subv_w
|
||||
#define __msa_subv_d __builtin_msa_subv_d
|
||||
#define __msa_subvi_b __builtin_msa_subvi_b
|
||||
#define __msa_subvi_h __builtin_msa_subvi_h
|
||||
#define __msa_subvi_w __builtin_msa_subvi_w
|
||||
#define __msa_subvi_d __builtin_msa_subvi_d
|
||||
#define __msa_max_s_b __builtin_msa_max_s_b
|
||||
#define __msa_max_s_h __builtin_msa_max_s_h
|
||||
#define __msa_max_s_w __builtin_msa_max_s_w
|
||||
#define __msa_max_s_d __builtin_msa_max_s_d
|
||||
#define __msa_maxi_s_b __builtin_msa_maxi_s_b
|
||||
#define __msa_maxi_s_h __builtin_msa_maxi_s_h
|
||||
#define __msa_maxi_s_w __builtin_msa_maxi_s_w
|
||||
#define __msa_maxi_s_d __builtin_msa_maxi_s_d
|
||||
#define __msa_max_u_b __builtin_msa_max_u_b
|
||||
#define __msa_max_u_h __builtin_msa_max_u_h
|
||||
#define __msa_max_u_w __builtin_msa_max_u_w
|
||||
#define __msa_max_u_d __builtin_msa_max_u_d
|
||||
#define __msa_maxi_u_b __builtin_msa_maxi_u_b
|
||||
#define __msa_maxi_u_h __builtin_msa_maxi_u_h
|
||||
#define __msa_maxi_u_w __builtin_msa_maxi_u_w
|
||||
#define __msa_maxi_u_d __builtin_msa_maxi_u_d
|
||||
#define __msa_min_s_b __builtin_msa_min_s_b
|
||||
#define __msa_min_s_h __builtin_msa_min_s_h
|
||||
#define __msa_min_s_w __builtin_msa_min_s_w
|
||||
#define __msa_min_s_d __builtin_msa_min_s_d
|
||||
#define __msa_mini_s_b __builtin_msa_mini_s_b
|
||||
#define __msa_mini_s_h __builtin_msa_mini_s_h
|
||||
#define __msa_mini_s_w __builtin_msa_mini_s_w
|
||||
#define __msa_mini_s_d __builtin_msa_mini_s_d
|
||||
#define __msa_min_u_b __builtin_msa_min_u_b
|
||||
#define __msa_min_u_h __builtin_msa_min_u_h
|
||||
#define __msa_min_u_w __builtin_msa_min_u_w
|
||||
#define __msa_min_u_d __builtin_msa_min_u_d
|
||||
#define __msa_mini_u_b __builtin_msa_mini_u_b
|
||||
#define __msa_mini_u_h __builtin_msa_mini_u_h
|
||||
#define __msa_mini_u_w __builtin_msa_mini_u_w
|
||||
#define __msa_mini_u_d __builtin_msa_mini_u_d
|
||||
#define __msa_max_a_b __builtin_msa_max_a_b
|
||||
#define __msa_max_a_h __builtin_msa_max_a_h
|
||||
#define __msa_max_a_w __builtin_msa_max_a_w
|
||||
#define __msa_max_a_d __builtin_msa_max_a_d
|
||||
#define __msa_min_a_b __builtin_msa_min_a_b
|
||||
#define __msa_min_a_h __builtin_msa_min_a_h
|
||||
#define __msa_min_a_w __builtin_msa_min_a_w
|
||||
#define __msa_min_a_d __builtin_msa_min_a_d
|
||||
#define __msa_ceq_b __builtin_msa_ceq_b
|
||||
#define __msa_ceq_h __builtin_msa_ceq_h
|
||||
#define __msa_ceq_w __builtin_msa_ceq_w
|
||||
#define __msa_ceq_d __builtin_msa_ceq_d
|
||||
#define __msa_ceqi_b __builtin_msa_ceqi_b
|
||||
#define __msa_ceqi_h __builtin_msa_ceqi_h
|
||||
#define __msa_ceqi_w __builtin_msa_ceqi_w
|
||||
#define __msa_ceqi_d __builtin_msa_ceqi_d
|
||||
#define __msa_clt_s_b __builtin_msa_clt_s_b
|
||||
#define __msa_clt_s_h __builtin_msa_clt_s_h
|
||||
#define __msa_clt_s_w __builtin_msa_clt_s_w
|
||||
#define __msa_clt_s_d __builtin_msa_clt_s_d
|
||||
#define __msa_clti_s_b __builtin_msa_clti_s_b
|
||||
#define __msa_clti_s_h __builtin_msa_clti_s_h
|
||||
#define __msa_clti_s_w __builtin_msa_clti_s_w
|
||||
#define __msa_clti_s_d __builtin_msa_clti_s_d
|
||||
#define __msa_clt_u_b __builtin_msa_clt_u_b
|
||||
#define __msa_clt_u_h __builtin_msa_clt_u_h
|
||||
#define __msa_clt_u_w __builtin_msa_clt_u_w
|
||||
#define __msa_clt_u_d __builtin_msa_clt_u_d
|
||||
#define __msa_clti_u_b __builtin_msa_clti_u_b
|
||||
#define __msa_clti_u_h __builtin_msa_clti_u_h
|
||||
#define __msa_clti_u_w __builtin_msa_clti_u_w
|
||||
#define __msa_clti_u_d __builtin_msa_clti_u_d
|
||||
#define __msa_cle_s_b __builtin_msa_cle_s_b
|
||||
#define __msa_cle_s_h __builtin_msa_cle_s_h
|
||||
#define __msa_cle_s_w __builtin_msa_cle_s_w
|
||||
#define __msa_cle_s_d __builtin_msa_cle_s_d
|
||||
#define __msa_clei_s_b __builtin_msa_clei_s_b
|
||||
#define __msa_clei_s_h __builtin_msa_clei_s_h
|
||||
#define __msa_clei_s_w __builtin_msa_clei_s_w
|
||||
#define __msa_clei_s_d __builtin_msa_clei_s_d
|
||||
#define __msa_cle_u_b __builtin_msa_cle_u_b
|
||||
#define __msa_cle_u_h __builtin_msa_cle_u_h
|
||||
#define __msa_cle_u_w __builtin_msa_cle_u_w
|
||||
#define __msa_cle_u_d __builtin_msa_cle_u_d
|
||||
#define __msa_clei_u_b __builtin_msa_clei_u_b
|
||||
#define __msa_clei_u_h __builtin_msa_clei_u_h
|
||||
#define __msa_clei_u_w __builtin_msa_clei_u_w
|
||||
#define __msa_clei_u_d __builtin_msa_clei_u_d
|
||||
#define __msa_ld_b __builtin_msa_ld_b
|
||||
#define __msa_ld_h __builtin_msa_ld_h
|
||||
#define __msa_ld_w __builtin_msa_ld_w
|
||||
#define __msa_ld_d __builtin_msa_ld_d
|
||||
#define __msa_st_b __builtin_msa_st_b
|
||||
#define __msa_st_h __builtin_msa_st_h
|
||||
#define __msa_st_w __builtin_msa_st_w
|
||||
#define __msa_st_d __builtin_msa_st_d
|
||||
#define __msa_sat_s_b __builtin_msa_sat_s_b
|
||||
#define __msa_sat_s_h __builtin_msa_sat_s_h
|
||||
#define __msa_sat_s_w __builtin_msa_sat_s_w
|
||||
#define __msa_sat_s_d __builtin_msa_sat_s_d
|
||||
#define __msa_sat_u_b __builtin_msa_sat_u_b
|
||||
#define __msa_sat_u_h __builtin_msa_sat_u_h
|
||||
#define __msa_sat_u_w __builtin_msa_sat_u_w
|
||||
#define __msa_sat_u_d __builtin_msa_sat_u_d
|
||||
#define __msa_add_a_b __builtin_msa_add_a_b
|
||||
#define __msa_add_a_h __builtin_msa_add_a_h
|
||||
#define __msa_add_a_w __builtin_msa_add_a_w
|
||||
#define __msa_add_a_d __builtin_msa_add_a_d
|
||||
#define __msa_adds_a_b __builtin_msa_adds_a_b
|
||||
#define __msa_adds_a_h __builtin_msa_adds_a_h
|
||||
#define __msa_adds_a_w __builtin_msa_adds_a_w
|
||||
#define __msa_adds_a_d __builtin_msa_adds_a_d
|
||||
#define __msa_adds_s_b __builtin_msa_adds_s_b
|
||||
#define __msa_adds_s_h __builtin_msa_adds_s_h
|
||||
#define __msa_adds_s_w __builtin_msa_adds_s_w
|
||||
#define __msa_adds_s_d __builtin_msa_adds_s_d
|
||||
#define __msa_adds_u_b __builtin_msa_adds_u_b
|
||||
#define __msa_adds_u_h __builtin_msa_adds_u_h
|
||||
#define __msa_adds_u_w __builtin_msa_adds_u_w
|
||||
#define __msa_adds_u_d __builtin_msa_adds_u_d
|
||||
#define __msa_ave_s_b __builtin_msa_ave_s_b
|
||||
#define __msa_ave_s_h __builtin_msa_ave_s_h
|
||||
#define __msa_ave_s_w __builtin_msa_ave_s_w
|
||||
#define __msa_ave_s_d __builtin_msa_ave_s_d
|
||||
#define __msa_ave_u_b __builtin_msa_ave_u_b
|
||||
#define __msa_ave_u_h __builtin_msa_ave_u_h
|
||||
#define __msa_ave_u_w __builtin_msa_ave_u_w
|
||||
#define __msa_ave_u_d __builtin_msa_ave_u_d
|
||||
#define __msa_aver_s_b __builtin_msa_aver_s_b
|
||||
#define __msa_aver_s_h __builtin_msa_aver_s_h
|
||||
#define __msa_aver_s_w __builtin_msa_aver_s_w
|
||||
#define __msa_aver_s_d __builtin_msa_aver_s_d
|
||||
#define __msa_aver_u_b __builtin_msa_aver_u_b
|
||||
#define __msa_aver_u_h __builtin_msa_aver_u_h
|
||||
#define __msa_aver_u_w __builtin_msa_aver_u_w
|
||||
#define __msa_aver_u_d __builtin_msa_aver_u_d
|
||||
#define __msa_subs_s_b __builtin_msa_subs_s_b
|
||||
#define __msa_subs_s_h __builtin_msa_subs_s_h
|
||||
#define __msa_subs_s_w __builtin_msa_subs_s_w
|
||||
#define __msa_subs_s_d __builtin_msa_subs_s_d
|
||||
#define __msa_subs_u_b __builtin_msa_subs_u_b
|
||||
#define __msa_subs_u_h __builtin_msa_subs_u_h
|
||||
#define __msa_subs_u_w __builtin_msa_subs_u_w
|
||||
#define __msa_subs_u_d __builtin_msa_subs_u_d
|
||||
#define __msa_subsuu_s_b __builtin_msa_subsuu_s_b
|
||||
#define __msa_subsuu_s_h __builtin_msa_subsuu_s_h
|
||||
#define __msa_subsuu_s_w __builtin_msa_subsuu_s_w
|
||||
#define __msa_subsuu_s_d __builtin_msa_subsuu_s_d
|
||||
#define __msa_subsus_u_b __builtin_msa_subsus_u_b
|
||||
#define __msa_subsus_u_h __builtin_msa_subsus_u_h
|
||||
#define __msa_subsus_u_w __builtin_msa_subsus_u_w
|
||||
#define __msa_subsus_u_d __builtin_msa_subsus_u_d
|
||||
#define __msa_asub_s_b __builtin_msa_asub_s_b
|
||||
#define __msa_asub_s_h __builtin_msa_asub_s_h
|
||||
#define __msa_asub_s_w __builtin_msa_asub_s_w
|
||||
#define __msa_asub_s_d __builtin_msa_asub_s_d
|
||||
#define __msa_asub_u_b __builtin_msa_asub_u_b
|
||||
#define __msa_asub_u_h __builtin_msa_asub_u_h
|
||||
#define __msa_asub_u_w __builtin_msa_asub_u_w
|
||||
#define __msa_asub_u_d __builtin_msa_asub_u_d
|
||||
#define __msa_mulv_b __builtin_msa_mulv_b
|
||||
#define __msa_mulv_h __builtin_msa_mulv_h
|
||||
#define __msa_mulv_w __builtin_msa_mulv_w
|
||||
#define __msa_mulv_d __builtin_msa_mulv_d
|
||||
#define __msa_maddv_b __builtin_msa_maddv_b
|
||||
#define __msa_maddv_h __builtin_msa_maddv_h
|
||||
#define __msa_maddv_w __builtin_msa_maddv_w
|
||||
#define __msa_maddv_d __builtin_msa_maddv_d
|
||||
#define __msa_msubv_b __builtin_msa_msubv_b
|
||||
#define __msa_msubv_h __builtin_msa_msubv_h
|
||||
#define __msa_msubv_w __builtin_msa_msubv_w
|
||||
#define __msa_msubv_d __builtin_msa_msubv_d
|
||||
#define __msa_div_s_b __builtin_msa_div_s_b
|
||||
#define __msa_div_s_h __builtin_msa_div_s_h
|
||||
#define __msa_div_s_w __builtin_msa_div_s_w
|
||||
#define __msa_div_s_d __builtin_msa_div_s_d
|
||||
#define __msa_div_u_b __builtin_msa_div_u_b
|
||||
#define __msa_div_u_h __builtin_msa_div_u_h
|
||||
#define __msa_div_u_w __builtin_msa_div_u_w
|
||||
#define __msa_div_u_d __builtin_msa_div_u_d
|
||||
#define __msa_hadd_s_h __builtin_msa_hadd_s_h
|
||||
#define __msa_hadd_s_w __builtin_msa_hadd_s_w
|
||||
#define __msa_hadd_s_d __builtin_msa_hadd_s_d
|
||||
#define __msa_hadd_u_h __builtin_msa_hadd_u_h
|
||||
#define __msa_hadd_u_w __builtin_msa_hadd_u_w
|
||||
#define __msa_hadd_u_d __builtin_msa_hadd_u_d
|
||||
#define __msa_hsub_s_h __builtin_msa_hsub_s_h
|
||||
#define __msa_hsub_s_w __builtin_msa_hsub_s_w
|
||||
#define __msa_hsub_s_d __builtin_msa_hsub_s_d
|
||||
#define __msa_hsub_u_h __builtin_msa_hsub_u_h
|
||||
#define __msa_hsub_u_w __builtin_msa_hsub_u_w
|
||||
#define __msa_hsub_u_d __builtin_msa_hsub_u_d
|
||||
#define __msa_mod_s_b __builtin_msa_mod_s_b
|
||||
#define __msa_mod_s_h __builtin_msa_mod_s_h
|
||||
#define __msa_mod_s_w __builtin_msa_mod_s_w
|
||||
#define __msa_mod_s_d __builtin_msa_mod_s_d
|
||||
#define __msa_mod_u_b __builtin_msa_mod_u_b
|
||||
#define __msa_mod_u_h __builtin_msa_mod_u_h
|
||||
#define __msa_mod_u_w __builtin_msa_mod_u_w
|
||||
#define __msa_mod_u_d __builtin_msa_mod_u_d
|
||||
#define __msa_dotp_s_h __builtin_msa_dotp_s_h
|
||||
#define __msa_dotp_s_w __builtin_msa_dotp_s_w
|
||||
#define __msa_dotp_s_d __builtin_msa_dotp_s_d
|
||||
#define __msa_dotp_u_h __builtin_msa_dotp_u_h
|
||||
#define __msa_dotp_u_w __builtin_msa_dotp_u_w
|
||||
#define __msa_dotp_u_d __builtin_msa_dotp_u_d
|
||||
#define __msa_dpadd_s_h __builtin_msa_dpadd_s_h
|
||||
#define __msa_dpadd_s_w __builtin_msa_dpadd_s_w
|
||||
#define __msa_dpadd_s_d __builtin_msa_dpadd_s_d
|
||||
#define __msa_dpadd_u_h __builtin_msa_dpadd_u_h
|
||||
#define __msa_dpadd_u_w __builtin_msa_dpadd_u_w
|
||||
#define __msa_dpadd_u_d __builtin_msa_dpadd_u_d
|
||||
#define __msa_dpsub_s_h __builtin_msa_dpsub_s_h
|
||||
#define __msa_dpsub_s_w __builtin_msa_dpsub_s_w
|
||||
#define __msa_dpsub_s_d __builtin_msa_dpsub_s_d
|
||||
#define __msa_dpsub_u_h __builtin_msa_dpsub_u_h
|
||||
#define __msa_dpsub_u_w __builtin_msa_dpsub_u_w
|
||||
#define __msa_dpsub_u_d __builtin_msa_dpsub_u_d
|
||||
#define __msa_sld_b __builtin_msa_sld_b
|
||||
#define __msa_sld_h __builtin_msa_sld_h
|
||||
#define __msa_sld_w __builtin_msa_sld_w
|
||||
#define __msa_sld_d __builtin_msa_sld_d
|
||||
#define __msa_sldi_b __builtin_msa_sldi_b
|
||||
#define __msa_sldi_h __builtin_msa_sldi_h
|
||||
#define __msa_sldi_w __builtin_msa_sldi_w
|
||||
#define __msa_sldi_d __builtin_msa_sldi_d
|
||||
#define __msa_splat_b __builtin_msa_splat_b
|
||||
#define __msa_splat_h __builtin_msa_splat_h
|
||||
#define __msa_splat_w __builtin_msa_splat_w
|
||||
#define __msa_splat_d __builtin_msa_splat_d
|
||||
#define __msa_splati_b __builtin_msa_splati_b
|
||||
#define __msa_splati_h __builtin_msa_splati_h
|
||||
#define __msa_splati_w __builtin_msa_splati_w
|
||||
#define __msa_splati_d __builtin_msa_splati_d
|
||||
#define __msa_pckev_b __builtin_msa_pckev_b
|
||||
#define __msa_pckev_h __builtin_msa_pckev_h
|
||||
#define __msa_pckev_w __builtin_msa_pckev_w
|
||||
#define __msa_pckev_d __builtin_msa_pckev_d
|
||||
#define __msa_pckod_b __builtin_msa_pckod_b
|
||||
#define __msa_pckod_h __builtin_msa_pckod_h
|
||||
#define __msa_pckod_w __builtin_msa_pckod_w
|
||||
#define __msa_pckod_d __builtin_msa_pckod_d
|
||||
#define __msa_ilvl_b __builtin_msa_ilvl_b
|
||||
#define __msa_ilvl_h __builtin_msa_ilvl_h
|
||||
#define __msa_ilvl_w __builtin_msa_ilvl_w
|
||||
#define __msa_ilvl_d __builtin_msa_ilvl_d
|
||||
#define __msa_ilvr_b __builtin_msa_ilvr_b
|
||||
#define __msa_ilvr_h __builtin_msa_ilvr_h
|
||||
#define __msa_ilvr_w __builtin_msa_ilvr_w
|
||||
#define __msa_ilvr_d __builtin_msa_ilvr_d
|
||||
#define __msa_ilvev_b __builtin_msa_ilvev_b
|
||||
#define __msa_ilvev_h __builtin_msa_ilvev_h
|
||||
#define __msa_ilvev_w __builtin_msa_ilvev_w
|
||||
#define __msa_ilvev_d __builtin_msa_ilvev_d
|
||||
#define __msa_ilvod_b __builtin_msa_ilvod_b
|
||||
#define __msa_ilvod_h __builtin_msa_ilvod_h
|
||||
#define __msa_ilvod_w __builtin_msa_ilvod_w
|
||||
#define __msa_ilvod_d __builtin_msa_ilvod_d
|
||||
#define __msa_vshf_b __builtin_msa_vshf_b
|
||||
#define __msa_vshf_h __builtin_msa_vshf_h
|
||||
#define __msa_vshf_w __builtin_msa_vshf_w
|
||||
#define __msa_vshf_d __builtin_msa_vshf_d
|
||||
#define __msa_and_v __builtin_msa_and_v
|
||||
#define __msa_andi_b __builtin_msa_andi_b
|
||||
#define __msa_or_v __builtin_msa_or_v
|
||||
#define __msa_ori_b __builtin_msa_ori_b
|
||||
#define __msa_nor_v __builtin_msa_nor_v
|
||||
#define __msa_nori_b __builtin_msa_nori_b
|
||||
#define __msa_xor_v __builtin_msa_xor_v
|
||||
#define __msa_xori_b __builtin_msa_xori_b
|
||||
#define __msa_bmnz_v __builtin_msa_bmnz_v
|
||||
#define __msa_bmnzi_b __builtin_msa_bmnzi_b
|
||||
#define __msa_bmz_v __builtin_msa_bmz_v
|
||||
#define __msa_bmzi_b __builtin_msa_bmzi_b
|
||||
#define __msa_bsel_v __builtin_msa_bsel_v
|
||||
#define __msa_bseli_b __builtin_msa_bseli_b
|
||||
#define __msa_shf_b __builtin_msa_shf_b
|
||||
#define __msa_shf_h __builtin_msa_shf_h
|
||||
#define __msa_shf_w __builtin_msa_shf_w
|
||||
#define __msa_test_bnz_v __builtin_msa_bnz_v
|
||||
#define __msa_test_bz_v __builtin_msa_bz_v
|
||||
#define __msa_fill_b __builtin_msa_fill_b
|
||||
#define __msa_fill_h __builtin_msa_fill_h
|
||||
#define __msa_fill_w __builtin_msa_fill_w
|
||||
#define __msa_fill_d __builtin_msa_fill_d
|
||||
#define __msa_pcnt_b __builtin_msa_pcnt_b
|
||||
#define __msa_pcnt_h __builtin_msa_pcnt_h
|
||||
#define __msa_pcnt_w __builtin_msa_pcnt_w
|
||||
#define __msa_pcnt_d __builtin_msa_pcnt_d
|
||||
#define __msa_nloc_b __builtin_msa_nloc_b
|
||||
#define __msa_nloc_h __builtin_msa_nloc_h
|
||||
#define __msa_nloc_w __builtin_msa_nloc_w
|
||||
#define __msa_nloc_d __builtin_msa_nloc_d
|
||||
#define __msa_nlzc_b __builtin_msa_nlzc_b
|
||||
#define __msa_nlzc_h __builtin_msa_nlzc_h
|
||||
#define __msa_nlzc_w __builtin_msa_nlzc_w
|
||||
#define __msa_nlzc_d __builtin_msa_nlzc_d
|
||||
#define __msa_copy_s_b __builtin_msa_copy_s_b
|
||||
#define __msa_copy_s_h __builtin_msa_copy_s_h
|
||||
#define __msa_copy_s_w __builtin_msa_copy_s_w
|
||||
#define __msa_copy_s_d __builtin_msa_copy_s_d
|
||||
#define __msa_copy_u_b __builtin_msa_copy_u_b
|
||||
#define __msa_copy_u_h __builtin_msa_copy_u_h
|
||||
#define __msa_copy_u_w __builtin_msa_copy_u_w
|
||||
#define __msa_copy_u_d __builtin_msa_copy_u_d
|
||||
#define __msa_insert_b __builtin_msa_insert_b
|
||||
#define __msa_insert_h __builtin_msa_insert_h
|
||||
#define __msa_insert_w __builtin_msa_insert_w
|
||||
#define __msa_insert_d __builtin_msa_insert_d
|
||||
#define __msa_insve_b __builtin_msa_insve_b
|
||||
#define __msa_insve_h __builtin_msa_insve_h
|
||||
#define __msa_insve_w __builtin_msa_insve_w
|
||||
#define __msa_insve_d __builtin_msa_insve_d
|
||||
#define __msa_test_bnz_b __builtin_msa_bnz_b
|
||||
#define __msa_test_bnz_h __builtin_msa_bnz_h
|
||||
#define __msa_test_bnz_w __builtin_msa_bnz_w
|
||||
#define __msa_test_bnz_d __builtin_msa_bnz_d
|
||||
#define __msa_test_bz_b __builtin_msa_bz_b
|
||||
#define __msa_test_bz_h __builtin_msa_bz_h
|
||||
#define __msa_test_bz_w __builtin_msa_bz_w
|
||||
#define __msa_test_bz_d __builtin_msa_bz_d
|
||||
#define __msa_ldi_b __builtin_msa_ldi_b
|
||||
#define __msa_ldi_h __builtin_msa_ldi_h
|
||||
#define __msa_ldi_w __builtin_msa_ldi_w
|
||||
#define __msa_ldi_d __builtin_msa_ldi_d
|
||||
#define __msa_fcaf_w __builtin_msa_fcaf_w
|
||||
#define __msa_fcaf_d __builtin_msa_fcaf_d
|
||||
#define __msa_fcor_w __builtin_msa_fcor_w
|
||||
#define __msa_fcor_d __builtin_msa_fcor_d
|
||||
#define __msa_fcun_w __builtin_msa_fcun_w
|
||||
#define __msa_fcun_d __builtin_msa_fcun_d
|
||||
#define __msa_fcune_w __builtin_msa_fcune_w
|
||||
#define __msa_fcune_d __builtin_msa_fcune_d
|
||||
#define __msa_fcueq_w __builtin_msa_fcueq_w
|
||||
#define __msa_fcueq_d __builtin_msa_fcueq_d
|
||||
#define __msa_fceq_w __builtin_msa_fceq_w
|
||||
#define __msa_fceq_d __builtin_msa_fceq_d
|
||||
#define __msa_fcne_w __builtin_msa_fcne_w
|
||||
#define __msa_fcne_d __builtin_msa_fcne_d
|
||||
#define __msa_fclt_w __builtin_msa_fclt_w
|
||||
#define __msa_fclt_d __builtin_msa_fclt_d
|
||||
#define __msa_fcult_w __builtin_msa_fcult_w
|
||||
#define __msa_fcult_d __builtin_msa_fcult_d
|
||||
#define __msa_fcle_w __builtin_msa_fcle_w
|
||||
#define __msa_fcle_d __builtin_msa_fcle_d
|
||||
#define __msa_fcule_w __builtin_msa_fcule_w
|
||||
#define __msa_fcule_d __builtin_msa_fcule_d
|
||||
#define __msa_fsaf_w __builtin_msa_fsaf_w
|
||||
#define __msa_fsaf_d __builtin_msa_fsaf_d
|
||||
#define __msa_fsor_w __builtin_msa_fsor_w
|
||||
#define __msa_fsor_d __builtin_msa_fsor_d
|
||||
#define __msa_fsun_w __builtin_msa_fsun_w
|
||||
#define __msa_fsun_d __builtin_msa_fsun_d
|
||||
#define __msa_fsune_w __builtin_msa_fsune_w
|
||||
#define __msa_fsune_d __builtin_msa_fsune_d
|
||||
#define __msa_fsueq_w __builtin_msa_fsueq_w
|
||||
#define __msa_fsueq_d __builtin_msa_fsueq_d
|
||||
#define __msa_fseq_w __builtin_msa_fseq_w
|
||||
#define __msa_fseq_d __builtin_msa_fseq_d
|
||||
#define __msa_fsne_w __builtin_msa_fsne_w
|
||||
#define __msa_fsne_d __builtin_msa_fsne_d
|
||||
#define __msa_fslt_w __builtin_msa_fslt_w
|
||||
#define __msa_fslt_d __builtin_msa_fslt_d
|
||||
#define __msa_fsult_w __builtin_msa_fsult_w
|
||||
#define __msa_fsult_d __builtin_msa_fsult_d
|
||||
#define __msa_fsle_w __builtin_msa_fsle_w
|
||||
#define __msa_fsle_d __builtin_msa_fsle_d
|
||||
#define __msa_fsule_w __builtin_msa_fsule_w
|
||||
#define __msa_fsule_d __builtin_msa_fsule_d
|
||||
#define __msa_fadd_w __builtin_msa_fadd_w
|
||||
#define __msa_fadd_d __builtin_msa_fadd_d
|
||||
#define __msa_fsub_w __builtin_msa_fsub_w
|
||||
#define __msa_fsub_d __builtin_msa_fsub_d
|
||||
#define __msa_fmul_w __builtin_msa_fmul_w
|
||||
#define __msa_fmul_d __builtin_msa_fmul_d
|
||||
#define __msa_fdiv_w __builtin_msa_fdiv_w
|
||||
#define __msa_fdiv_d __builtin_msa_fdiv_d
|
||||
#define __msa_fmadd_w __builtin_msa_fmadd_w
|
||||
#define __msa_fmadd_d __builtin_msa_fmadd_d
|
||||
#define __msa_fmsub_w __builtin_msa_fmsub_w
|
||||
#define __msa_fmsub_d __builtin_msa_fmsub_d
|
||||
#define __msa_fexp2_w __builtin_msa_fexp2_w
|
||||
#define __msa_fexp2_d __builtin_msa_fexp2_d
|
||||
#define __msa_fexdo_h __builtin_msa_fexdo_h
|
||||
#define __msa_fexdo_w __builtin_msa_fexdo_w
|
||||
#define __msa_ftq_h __builtin_msa_ftq_h
|
||||
#define __msa_ftq_w __builtin_msa_ftq_w
|
||||
#define __msa_fmin_w __builtin_msa_fmin_w
|
||||
#define __msa_fmin_d __builtin_msa_fmin_d
|
||||
#define __msa_fmin_a_w __builtin_msa_fmin_a_w
|
||||
#define __msa_fmin_a_d __builtin_msa_fmin_a_d
|
||||
#define __msa_fmax_w __builtin_msa_fmax_w
|
||||
#define __msa_fmax_d __builtin_msa_fmax_d
|
||||
#define __msa_fmax_a_w __builtin_msa_fmax_a_w
|
||||
#define __msa_fmax_a_d __builtin_msa_fmax_a_d
|
||||
#define __msa_mul_q_h __builtin_msa_mul_q_h
|
||||
#define __msa_mul_q_w __builtin_msa_mul_q_w
|
||||
#define __msa_mulr_q_h __builtin_msa_mulr_q_h
|
||||
#define __msa_mulr_q_w __builtin_msa_mulr_q_w
|
||||
#define __msa_madd_q_h __builtin_msa_madd_q_h
|
||||
#define __msa_madd_q_w __builtin_msa_madd_q_w
|
||||
#define __msa_maddr_q_h __builtin_msa_maddr_q_h
|
||||
#define __msa_maddr_q_w __builtin_msa_maddr_q_w
|
||||
#define __msa_msub_q_h __builtin_msa_msub_q_h
|
||||
#define __msa_msub_q_w __builtin_msa_msub_q_w
|
||||
#define __msa_msubr_q_h __builtin_msa_msubr_q_h
|
||||
#define __msa_msubr_q_w __builtin_msa_msubr_q_w
|
||||
#define __msa_fclass_w __builtin_msa_fclass_w
|
||||
#define __msa_fclass_d __builtin_msa_fclass_d
|
||||
#define __msa_fsqrt_w __builtin_msa_fsqrt_w
|
||||
#define __msa_fsqrt_d __builtin_msa_fsqrt_d
|
||||
#define __msa_frcp_w __builtin_msa_frcp_w
|
||||
#define __msa_frcp_d __builtin_msa_frcp_d
|
||||
#define __msa_frint_w __builtin_msa_frint_w
|
||||
#define __msa_frint_d __builtin_msa_frint_d
|
||||
#define __msa_frsqrt_w __builtin_msa_frsqrt_w
|
||||
#define __msa_frsqrt_d __builtin_msa_frsqrt_d
|
||||
#define __msa_flog2_w __builtin_msa_flog2_w
|
||||
#define __msa_flog2_d __builtin_msa_flog2_d
|
||||
#define __msa_fexupl_w __builtin_msa_fexupl_w
|
||||
#define __msa_fexupl_d __builtin_msa_fexupl_d
|
||||
#define __msa_fexupr_w __builtin_msa_fexupr_w
|
||||
#define __msa_fexupr_d __builtin_msa_fexupr_d
|
||||
#define __msa_ffql_w __builtin_msa_ffql_w
|
||||
#define __msa_ffql_d __builtin_msa_ffql_d
|
||||
#define __msa_ffqr_w __builtin_msa_ffqr_w
|
||||
#define __msa_ffqr_d __builtin_msa_ffqr_d
|
||||
#define __msa_ftint_s_w __builtin_msa_ftint_s_w
|
||||
#define __msa_ftint_s_d __builtin_msa_ftint_s_d
|
||||
#define __msa_ftint_u_w __builtin_msa_ftint_u_w
|
||||
#define __msa_ftint_u_d __builtin_msa_ftint_u_d
|
||||
#define __msa_ftrunc_s_w __builtin_msa_ftrunc_s_w
|
||||
#define __msa_ftrunc_s_d __builtin_msa_ftrunc_s_d
|
||||
#define __msa_ftrunc_u_w __builtin_msa_ftrunc_u_w
|
||||
#define __msa_ftrunc_u_d __builtin_msa_ftrunc_u_d
|
||||
#define __msa_ffint_s_w __builtin_msa_ffint_s_w
|
||||
#define __msa_ffint_s_d __builtin_msa_ffint_s_d
|
||||
#define __msa_ffint_u_w __builtin_msa_ffint_u_w
|
||||
#define __msa_ffint_u_d __builtin_msa_ffint_u_d
|
||||
#define __msa_cfcmsa __builtin_msa_cfcmsa
|
||||
#define __msa_move_v __builtin_msa_move_v
|
||||
#define __msa_cast_to_vector_float __builtin_msa_cast_to_vector_float
|
||||
#define __msa_cast_to_vector_double __builtin_msa_cast_to_vector_double
|
||||
#define __msa_cast_to_scalar_float __builtin_msa_cast_to_scalar_float
|
||||
#define __msa_cast_to_scalar_double __builtin_msa_cast_to_scalar_double
|
||||
#endif /* defined(__mips_msa) */
|
||||
#endif /* _MSA_H */
|
||||
@ -1454,8 +1454,17 @@ bool Sema::CheckAArch64BuiltinFunctionCall(unsigned BuiltinID,
|
||||
return SemaBuiltinConstantArgRange(TheCall, i, l, u + l);
|
||||
}
|
||||
|
||||
// CheckMipsBuiltinFunctionCall - Checks the constant value passed to the
|
||||
// intrinsic is correct. The switch statement is ordered by DSP, MSA. The
|
||||
// ordering for DSP is unspecified. MSA is ordered by the data format used
|
||||
// by the underlying instruction i.e., df/m, df/n and then by size.
|
||||
//
|
||||
// FIXME: The size tests here should instead be tablegen'd along with the
|
||||
// definitions from include/clang/Basic/BuiltinsMips.def.
|
||||
// FIXME: GCC is strict on signedness for some of these intrinsics, we should
|
||||
// be too.
|
||||
bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
|
||||
unsigned i = 0, l = 0, u = 0;
|
||||
unsigned i = 0, l = 0, u = 0, m = 0;
|
||||
switch (BuiltinID) {
|
||||
default: return false;
|
||||
case Mips::BI__builtin_mips_wrdsp: i = 1; l = 0; u = 63; break;
|
||||
@ -1465,9 +1474,168 @@ bool Sema::CheckMipsBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
|
||||
case Mips::BI__builtin_mips_precr_sra_ph_w: i = 2; l = 0; u = 31; break;
|
||||
case Mips::BI__builtin_mips_precr_sra_r_ph_w: i = 2; l = 0; u = 31; break;
|
||||
case Mips::BI__builtin_mips_prepend: i = 2; l = 0; u = 31; break;
|
||||
// MSA instrinsics. Instructions (which the intrinsics maps to) which use the
|
||||
// df/m field.
|
||||
// These intrinsics take an unsigned 3 bit immediate.
|
||||
case Mips::BI__builtin_msa_bclri_b:
|
||||
case Mips::BI__builtin_msa_bnegi_b:
|
||||
case Mips::BI__builtin_msa_bseti_b:
|
||||
case Mips::BI__builtin_msa_sat_s_b:
|
||||
case Mips::BI__builtin_msa_sat_u_b:
|
||||
case Mips::BI__builtin_msa_slli_b:
|
||||
case Mips::BI__builtin_msa_srai_b:
|
||||
case Mips::BI__builtin_msa_srari_b:
|
||||
case Mips::BI__builtin_msa_srli_b:
|
||||
case Mips::BI__builtin_msa_srlri_b: i = 1; l = 0; u = 7; break;
|
||||
case Mips::BI__builtin_msa_binsli_b:
|
||||
case Mips::BI__builtin_msa_binsri_b: i = 2; l = 0; u = 7; break;
|
||||
// These intrinsics take an unsigned 4 bit immediate.
|
||||
case Mips::BI__builtin_msa_bclri_h:
|
||||
case Mips::BI__builtin_msa_bnegi_h:
|
||||
case Mips::BI__builtin_msa_bseti_h:
|
||||
case Mips::BI__builtin_msa_sat_s_h:
|
||||
case Mips::BI__builtin_msa_sat_u_h:
|
||||
case Mips::BI__builtin_msa_slli_h:
|
||||
case Mips::BI__builtin_msa_srai_h:
|
||||
case Mips::BI__builtin_msa_srari_h:
|
||||
case Mips::BI__builtin_msa_srli_h:
|
||||
case Mips::BI__builtin_msa_srlri_h: i = 1; l = 0; u = 15; break;
|
||||
case Mips::BI__builtin_msa_binsli_h:
|
||||
case Mips::BI__builtin_msa_binsri_h: i = 2; l = 0; u = 15; break;
|
||||
// These intrinsics take an unsigned 5 bit immedate.
|
||||
// The first block of intrinsics actually have an unsigned 5 bit field,
|
||||
// not a df/n field.
|
||||
case Mips::BI__builtin_msa_clei_u_b:
|
||||
case Mips::BI__builtin_msa_clei_u_h:
|
||||
case Mips::BI__builtin_msa_clei_u_w:
|
||||
case Mips::BI__builtin_msa_clei_u_d:
|
||||
case Mips::BI__builtin_msa_clti_u_b:
|
||||
case Mips::BI__builtin_msa_clti_u_h:
|
||||
case Mips::BI__builtin_msa_clti_u_w:
|
||||
case Mips::BI__builtin_msa_clti_u_d:
|
||||
case Mips::BI__builtin_msa_maxi_u_b:
|
||||
case Mips::BI__builtin_msa_maxi_u_h:
|
||||
case Mips::BI__builtin_msa_maxi_u_w:
|
||||
case Mips::BI__builtin_msa_maxi_u_d:
|
||||
case Mips::BI__builtin_msa_mini_u_b:
|
||||
case Mips::BI__builtin_msa_mini_u_h:
|
||||
case Mips::BI__builtin_msa_mini_u_w:
|
||||
case Mips::BI__builtin_msa_mini_u_d:
|
||||
case Mips::BI__builtin_msa_addvi_b:
|
||||
case Mips::BI__builtin_msa_addvi_h:
|
||||
case Mips::BI__builtin_msa_addvi_w:
|
||||
case Mips::BI__builtin_msa_addvi_d:
|
||||
case Mips::BI__builtin_msa_bclri_w:
|
||||
case Mips::BI__builtin_msa_bnegi_w:
|
||||
case Mips::BI__builtin_msa_bseti_w:
|
||||
case Mips::BI__builtin_msa_sat_s_w:
|
||||
case Mips::BI__builtin_msa_sat_u_w:
|
||||
case Mips::BI__builtin_msa_slli_w:
|
||||
case Mips::BI__builtin_msa_srai_w:
|
||||
case Mips::BI__builtin_msa_srari_w:
|
||||
case Mips::BI__builtin_msa_srli_w:
|
||||
case Mips::BI__builtin_msa_srlri_w:
|
||||
case Mips::BI__builtin_msa_subvi_b:
|
||||
case Mips::BI__builtin_msa_subvi_h:
|
||||
case Mips::BI__builtin_msa_subvi_w:
|
||||
case Mips::BI__builtin_msa_subvi_d: i = 1; l = 0; u = 31; break;
|
||||
case Mips::BI__builtin_msa_binsli_w:
|
||||
case Mips::BI__builtin_msa_binsri_w: i = 2; l = 0; u = 31; break;
|
||||
// These intrinsics take an unsigned 6 bit immediate.
|
||||
case Mips::BI__builtin_msa_bclri_d:
|
||||
case Mips::BI__builtin_msa_bnegi_d:
|
||||
case Mips::BI__builtin_msa_bseti_d:
|
||||
case Mips::BI__builtin_msa_sat_s_d:
|
||||
case Mips::BI__builtin_msa_sat_u_d:
|
||||
case Mips::BI__builtin_msa_slli_d:
|
||||
case Mips::BI__builtin_msa_srai_d:
|
||||
case Mips::BI__builtin_msa_srari_d:
|
||||
case Mips::BI__builtin_msa_srli_d:
|
||||
case Mips::BI__builtin_msa_srlri_d: i = 1; l = 0; u = 63; break;
|
||||
case Mips::BI__builtin_msa_binsli_d:
|
||||
case Mips::BI__builtin_msa_binsri_d: i = 2; l = 0; u = 63; break;
|
||||
// These intrinsics take a signed 5 bit immediate.
|
||||
case Mips::BI__builtin_msa_ceqi_b:
|
||||
case Mips::BI__builtin_msa_ceqi_h:
|
||||
case Mips::BI__builtin_msa_ceqi_w:
|
||||
case Mips::BI__builtin_msa_ceqi_d:
|
||||
case Mips::BI__builtin_msa_clti_s_b:
|
||||
case Mips::BI__builtin_msa_clti_s_h:
|
||||
case Mips::BI__builtin_msa_clti_s_w:
|
||||
case Mips::BI__builtin_msa_clti_s_d:
|
||||
case Mips::BI__builtin_msa_clei_s_b:
|
||||
case Mips::BI__builtin_msa_clei_s_h:
|
||||
case Mips::BI__builtin_msa_clei_s_w:
|
||||
case Mips::BI__builtin_msa_clei_s_d:
|
||||
case Mips::BI__builtin_msa_maxi_s_b:
|
||||
case Mips::BI__builtin_msa_maxi_s_h:
|
||||
case Mips::BI__builtin_msa_maxi_s_w:
|
||||
case Mips::BI__builtin_msa_maxi_s_d:
|
||||
case Mips::BI__builtin_msa_mini_s_b:
|
||||
case Mips::BI__builtin_msa_mini_s_h:
|
||||
case Mips::BI__builtin_msa_mini_s_w:
|
||||
case Mips::BI__builtin_msa_mini_s_d: i = 1; l = -16; u = 15; break;
|
||||
// These intrinsics take an unsigned 8 bit immediate.
|
||||
case Mips::BI__builtin_msa_andi_b:
|
||||
case Mips::BI__builtin_msa_nori_b:
|
||||
case Mips::BI__builtin_msa_ori_b:
|
||||
case Mips::BI__builtin_msa_shf_b:
|
||||
case Mips::BI__builtin_msa_shf_h:
|
||||
case Mips::BI__builtin_msa_shf_w:
|
||||
case Mips::BI__builtin_msa_xori_b: i = 1; l = 0; u = 255; break;
|
||||
case Mips::BI__builtin_msa_bseli_b:
|
||||
case Mips::BI__builtin_msa_bmnzi_b:
|
||||
case Mips::BI__builtin_msa_bmzi_b: i = 2; l = 0; u = 255; break;
|
||||
// df/n format
|
||||
// These intrinsics take an unsigned 4 bit immediate.
|
||||
case Mips::BI__builtin_msa_copy_s_b:
|
||||
case Mips::BI__builtin_msa_copy_u_b:
|
||||
case Mips::BI__builtin_msa_insve_b:
|
||||
case Mips::BI__builtin_msa_splati_b: i = 1; l = 0; u = 15; break;
|
||||
case Mips::BI__builtin_msa_sld_b:
|
||||
case Mips::BI__builtin_msa_sldi_b: i = 2; l = 0; u = 15; break;
|
||||
// These intrinsics take an unsigned 3 bit immediate.
|
||||
case Mips::BI__builtin_msa_copy_s_h:
|
||||
case Mips::BI__builtin_msa_copy_u_h:
|
||||
case Mips::BI__builtin_msa_insve_h:
|
||||
case Mips::BI__builtin_msa_splati_h: i = 1; l = 0; u = 7; break;
|
||||
case Mips::BI__builtin_msa_sld_h:
|
||||
case Mips::BI__builtin_msa_sldi_h: i = 2; l = 0; u = 7; break;
|
||||
// These intrinsics take an unsigned 2 bit immediate.
|
||||
case Mips::BI__builtin_msa_copy_s_w:
|
||||
case Mips::BI__builtin_msa_copy_u_w:
|
||||
case Mips::BI__builtin_msa_insve_w:
|
||||
case Mips::BI__builtin_msa_splati_w: i = 1; l = 0; u = 3; break;
|
||||
case Mips::BI__builtin_msa_sld_w:
|
||||
case Mips::BI__builtin_msa_sldi_w: i = 2; l = 0; u = 3; break;
|
||||
// These intrinsics take an unsigned 1 bit immediate.
|
||||
case Mips::BI__builtin_msa_copy_s_d:
|
||||
case Mips::BI__builtin_msa_copy_u_d:
|
||||
case Mips::BI__builtin_msa_insve_d:
|
||||
case Mips::BI__builtin_msa_splati_d: i = 1; l = 0; u = 1; break;
|
||||
case Mips::BI__builtin_msa_sld_d:
|
||||
case Mips::BI__builtin_msa_sldi_d: i = 2; l = 0; u = 1; break;
|
||||
// Memory offsets and immediate loads.
|
||||
// These intrinsics take a signed 10 bit immediate.
|
||||
case Mips::BI__builtin_msa_ldi_b: i = 0; l = -128; u = 127; break;
|
||||
case Mips::BI__builtin_msa_ldi_h:
|
||||
case Mips::BI__builtin_msa_ldi_w:
|
||||
case Mips::BI__builtin_msa_ldi_d: i = 0; l = -512; u = 511; break;
|
||||
case Mips::BI__builtin_msa_ld_b: i = 1; l = -512; u = 511; m = 16; break;
|
||||
case Mips::BI__builtin_msa_ld_h: i = 1; l = -1024; u = 1022; m = 16; break;
|
||||
case Mips::BI__builtin_msa_ld_w: i = 1; l = -2048; u = 2044; m = 16; break;
|
||||
case Mips::BI__builtin_msa_ld_d: i = 1; l = -4096; u = 4088; m = 16; break;
|
||||
case Mips::BI__builtin_msa_st_b: i = 2; l = -512; u = 511; m = 16; break;
|
||||
case Mips::BI__builtin_msa_st_h: i = 2; l = -1024; u = 1022; m = 16; break;
|
||||
case Mips::BI__builtin_msa_st_w: i = 2; l = -2048; u = 2044; m = 16; break;
|
||||
case Mips::BI__builtin_msa_st_d: i = 2; l = -4096; u = 4088; m = 16; break;
|
||||
}
|
||||
|
||||
return SemaBuiltinConstantArgRange(TheCall, i, l, u);
|
||||
if (!m)
|
||||
return SemaBuiltinConstantArgRange(TheCall, i, l, u);
|
||||
|
||||
return SemaBuiltinConstantArgRange(TheCall, i, l, u) ||
|
||||
SemaBuiltinConstantArgMultiple(TheCall, i, m);
|
||||
}
|
||||
|
||||
bool Sema::CheckPPCBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) {
|
||||
@ -3614,6 +3782,28 @@ bool Sema::SemaBuiltinConstantArgRange(CallExpr *TheCall, int ArgNum,
|
||||
return false;
|
||||
}
|
||||
|
||||
/// SemaBuiltinConstantArgMultiple - Handle a check if argument ArgNum of CallExpr
|
||||
/// TheCall is a constant expression is a multiple of Num..
|
||||
bool Sema::SemaBuiltinConstantArgMultiple(CallExpr *TheCall, int ArgNum,
|
||||
unsigned Num) {
|
||||
llvm::APSInt Result;
|
||||
|
||||
// We can't check the value of a dependent argument.
|
||||
Expr *Arg = TheCall->getArg(ArgNum);
|
||||
if (Arg->isTypeDependent() || Arg->isValueDependent())
|
||||
return false;
|
||||
|
||||
// Check constant-ness first.
|
||||
if (SemaBuiltinConstantArg(TheCall, ArgNum, Result))
|
||||
return true;
|
||||
|
||||
if (Result.getSExtValue() % Num != 0)
|
||||
return Diag(TheCall->getLocStart(), diag::err_argument_not_multiple)
|
||||
<< Num << Arg->getSourceRange();
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/// SemaBuiltinARMSpecialReg - Handle a check if argument ArgNum of CallExpr
|
||||
/// TheCall is an ARM/AArch64 special register string literal.
|
||||
bool Sema::SemaBuiltinARMSpecialReg(unsigned BuiltinID, CallExpr *TheCall,
|
||||
|
||||
@ -4221,9 +4221,12 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT,
|
||||
// A template constructor is never a copy constructor.
|
||||
// FIXME: However, it may actually be selected at the actual overload
|
||||
// resolution point.
|
||||
if (isa<FunctionTemplateDecl>(ND))
|
||||
if (isa<FunctionTemplateDecl>(ND->getUnderlyingDecl()))
|
||||
continue;
|
||||
const CXXConstructorDecl *Constructor = cast<CXXConstructorDecl>(ND);
|
||||
// UsingDecl itself is not a constructor
|
||||
if (isa<UsingDecl>(ND))
|
||||
continue;
|
||||
auto *Constructor = cast<CXXConstructorDecl>(ND->getUnderlyingDecl());
|
||||
if (Constructor->isCopyConstructor(FoundTQs)) {
|
||||
FoundConstructor = true;
|
||||
const FunctionProtoType *CPT
|
||||
@ -4257,9 +4260,12 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT,
|
||||
bool FoundConstructor = false;
|
||||
for (const auto *ND : Self.LookupConstructors(RD)) {
|
||||
// FIXME: In C++0x, a constructor template can be a default constructor.
|
||||
if (isa<FunctionTemplateDecl>(ND))
|
||||
if (isa<FunctionTemplateDecl>(ND->getUnderlyingDecl()))
|
||||
continue;
|
||||
const CXXConstructorDecl *Constructor = cast<CXXConstructorDecl>(ND);
|
||||
// UsingDecl itself is not a constructor
|
||||
if (isa<UsingDecl>(ND))
|
||||
continue;
|
||||
auto *Constructor = cast<CXXConstructorDecl>(ND->getUnderlyingDecl());
|
||||
if (Constructor->isDefaultConstructor()) {
|
||||
FoundConstructor = true;
|
||||
const FunctionProtoType *CPT
|
||||
|
||||
@ -33,4 +33,4 @@ add_lld_library(lldCOFF
|
||||
LINK_LIBS ${PTHREAD_LIB}
|
||||
)
|
||||
|
||||
add_dependencies(lldCOFF COFFOptionsTableGen)
|
||||
add_dependencies(lldCOFF COFFOptionsTableGen intrinsics_gen)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user