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- In bge_ifmedia_upd_locked() take advantrage of LIST_FOREACH().
- If boot verbose, print asicrev, chiprev and bus type on attach. - For PCI Express devices: 1) Adjust max read request size to 4Kbytes 2) Turn on FIFO_LONG_BURST in RDMA during bge_blockinit() Though 1) does not seem to have much to do with the poor TX performance observed on PCI Express bge(4), 2) does fix the problem. [1] - Nuke the RX CPU self-diag, which prevents working cards from working (Linux tg3 does not have this diag neither does OpenBSD's bge(4)). The increasing of the firmware handshaking timeout to 20000 retries done as part of the original commit isn't merged as way already have a way higher BGE_TIMEOUT of 100000. PR: 119361 [1] Obtained from: tg3 via DragonflyBSD [1], DragonflyBSD
This commit is contained in:
Marius Strobl
parent
abc2df4ae4
commit
4f09c4c7e5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=190194
@ -384,6 +384,7 @@ static uint32_t bge_readreg_ind(struct bge_softc *, int);
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#endif
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static void bge_writemem_direct(struct bge_softc *, int, int);
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static void bge_writereg_ind(struct bge_softc *, int, int);
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static void bge_set_max_readrq(struct bge_softc *, int);
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static int bge_miibus_readreg(device_t, int, int);
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static int bge_miibus_writereg(device_t, int, int, int);
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@ -523,6 +524,34 @@ bge_writemem_ind(struct bge_softc *sc, int off, int val)
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pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, 0, 4);
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}
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/*
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* PCI Express only
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*/
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static void
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bge_set_max_readrq(struct bge_softc *sc, int expr_ptr)
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{
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device_t dev;
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uint16_t val;
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KASSERT((sc->bge_flags & BGE_FLAG_PCIE) && expr_ptr != 0,
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("%s: not applicable", __func__));
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dev = sc->bge_dev;
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val = pci_read_config(dev, expr_ptr + BGE_PCIE_DEVCTL, 2);
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if ((val & BGE_PCIE_DEVCTL_MAX_READRQ_MASK) !=
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BGE_PCIE_DEVCTL_MAX_READRQ_4096) {
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if (bootverbose)
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device_printf(dev, "adjust device control 0x%04x ",
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val);
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val &= ~BGE_PCIE_DEVCTL_MAX_READRQ_MASK;
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val |= BGE_PCIE_DEVCTL_MAX_READRQ_4096;
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pci_write_config(dev, expr_ptr + BGE_PCIE_DEVCTL, val, 2);
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if (bootverbose)
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printf("-> 0x%04x\n", val);
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}
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}
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#ifdef notdef
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static uint32_t
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bge_readreg_ind(struct bge_softc *sc, int off)
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@ -1278,18 +1307,6 @@ bge_chipinit(struct bge_softc *sc)
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/* Set endianness before we access any non-PCI registers. */
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pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
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/*
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* Check the 'ROM failed' bit on the RX CPU to see if
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* self-tests passed. Skip this check when there's no
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* chip containing the Ethernet address fitted, since
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* in that case it will always fail.
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*/
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if ((sc->bge_flags & BGE_FLAG_EADDR) &&
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CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
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device_printf(sc->bge_dev, "RX CPU self-diagnostics failed!\n");
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return (ENODEV);
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}
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/* Clear the MAC control register */
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CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
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@ -1742,14 +1759,18 @@ bge_blockinit(struct bge_softc *sc)
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/* Enable host coalescing bug fix. */
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if (sc->bge_asicrev == BGE_ASICREV_BCM5755 ||
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sc->bge_asicrev == BGE_ASICREV_BCM5787)
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val |= 1 << 29;
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val |= 1 << 29;
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/* Turn on write DMA state machine */
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CSR_WRITE_4(sc, BGE_WDMA_MODE, val);
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DELAY(40);
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/* Turn on read DMA state machine */
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CSR_WRITE_4(sc, BGE_RDMA_MODE,
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BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS);
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val = BGE_RDMAMODE_ENABLE | BGE_RDMAMODE_ALL_ATTNS;
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if (sc->bge_flags & BGE_FLAG_PCIE)
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val |= BGE_RDMAMODE_FIFO_LONG_BURST;
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CSR_WRITE_4(sc, BGE_RDMA_MODE, val);
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DELAY(40);
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/* Turn on RX data completion state machine */
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CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
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@ -2387,7 +2408,7 @@ bge_attach(device_t dev)
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goto fail;
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}
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/* Save ASIC rev. */
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/* Save various chip information. */
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sc->bge_chipid =
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pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
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BGE_PCIMISCCTL_ASICREV;
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@ -2470,14 +2491,17 @@ bge_attach(device_t dev)
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* Found a PCI Express capabilities register, this
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* must be a PCI Express device.
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*/
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if (reg != 0)
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if (reg != 0) {
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sc->bge_flags |= BGE_FLAG_PCIE;
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#else
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if (BGE_IS_5705_PLUS(sc)) {
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reg = pci_read_config(dev, BGE_PCIE_CAPID_REG, 4);
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if ((reg & 0xFF) == BGE_PCIE_CAPID)
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if ((reg & 0xFF) == BGE_PCIE_CAPID) {
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sc->bge_flags |= BGE_FLAG_PCIE;
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reg = BGE_PCIE_CAPID;
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#endif
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bge_set_max_readrq(sc, reg);
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}
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} else {
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/*
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* Check if the device is in PCI-X Mode.
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@ -2522,6 +2546,13 @@ bge_attach(device_t dev)
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goto fail;
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}
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if (bootverbose)
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device_printf(dev,
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"CHIP ID 0x%08x; ASIC REV 0x%02x; CHIP REV 0x%02x; %s\n",
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sc->bge_chipid, sc->bge_asicrev, sc->bge_chiprev,
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(sc->bge_flags & BGE_FLAG_PCIX) ? "PCI-X" :
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((sc->bge_flags & BGE_FLAG_PCIE) ? "PCI-E" : "PCI"));
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BGE_LOCK_INIT(sc, device_get_nameunit(dev));
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/* Try to reset the chip. */
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@ -3882,6 +3913,7 @@ bge_ifmedia_upd_locked(struct ifnet *ifp)
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{
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struct bge_softc *sc = ifp->if_softc;
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struct mii_data *mii;
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struct mii_softc *miisc;
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struct ifmedia *ifm;
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BGE_LOCK_ASSERT(sc);
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@ -3932,12 +3964,9 @@ bge_ifmedia_upd_locked(struct ifnet *ifp)
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sc->bge_link_evt++;
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mii = device_get_softc(sc->bge_miibus);
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if (mii->mii_instance) {
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struct mii_softc *miisc;
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for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
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miisc = LIST_NEXT(miisc, mii_list))
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if (mii->mii_instance)
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LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
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mii_phy_reset(miisc);
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}
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mii_mediachg(mii);
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/*
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@ -176,6 +176,22 @@
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#define BGE_PCI_MSI_ADDR_LO 0x60
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#define BGE_PCI_MSI_DATA 0x64
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/*
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* PCI Express definitions
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* According to
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* PCI Express base specification, REV. 1.0a
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*/
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/* PCI Express device control, 16bits */
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#define BGE_PCIE_DEVCTL 0x08
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#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000
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#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000
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/* PCI MSI. ??? */
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#define BGE_PCIE_CAPID_REG 0xD0
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#define BGE_PCIE_CAPID 0x10
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@ -1359,6 +1375,8 @@
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#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
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#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
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#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
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#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
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#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
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/* Read DMA status register */
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#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
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