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Fix r283120 which use class size larger than 8bits.

Browse Source 
The new mapping will restore binary compatibility with stable_10
but file generated since r283120 are broken.

Reviewed by:	jhb
Sponsored by:	Stormshield
This commit is contained in:
Fabien Thomas 2015-10-08 10:00:41 +00:00
parent 78e79434d2
commit 4f621ff9dc
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=289025
1 changed files with 21 additions and 21 deletions
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42
sys/sys/pmc.h
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@ -128,26 +128,26 @@ enum pmc_cputype {
*/
#define __PMC_CLASSES() \
__PMC_CLASS(TSC, 0x000, "CPU Timestamp counter") \
__PMC_CLASS(K7, 0x100, "AMD K7 performance counters") \
__PMC_CLASS(K8, 0x101, "AMD K8 performance counters") \
__PMC_CLASS(P5, 0x102, "Intel Pentium counters") \
__PMC_CLASS(P6, 0x103, "Intel Pentium Pro counters") \
__PMC_CLASS(P4, 0x104, "Intel Pentium-IV counters") \
__PMC_CLASS(IAF, 0x105, "Intel Core2/Atom, fixed function") \
__PMC_CLASS(IAP, 0x106, "Intel Core...Atom, programmable") \
__PMC_CLASS(UCF, 0x107, "Intel Uncore fixed function") \
__PMC_CLASS(UCP, 0x108, "Intel Uncore programmable") \
__PMC_CLASS(XSCALE, 0x200, "Intel XScale counters") \
__PMC_CLASS(ARMV7, 0x201, "ARMv7") \
__PMC_CLASS(ARMV8, 0x202, "ARMv8") \
__PMC_CLASS(MIPS24K, 0x300, "MIPS 24K") \
__PMC_CLASS(OCTEON, 0x301, "Cavium Octeon") \
__PMC_CLASS(MIPS74K, 0x302, "MIPS 74K") \
__PMC_CLASS(PPC7450, 0x400, "Motorola MPC7450 class") \
__PMC_CLASS(PPC970, 0x401, "IBM PowerPC 970 class") \
__PMC_CLASS(E500, 0x402, "Freescale e500 class") \
__PMC_CLASS(SOFT, 0x8000, "Software events")
__PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \
__PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \
__PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \
__PMC_CLASS(P5, 0x03, "Intel Pentium counters") \
__PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \
__PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \
__PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \
__PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \
__PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \
__PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \
__PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \
__PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \
__PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \
__PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \
__PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \
__PMC_CLASS(SOFT, 0x0F, "Software events") \
__PMC_CLASS(ARMV7, 0x10, "ARMv7") \
__PMC_CLASS(ARMV8, 0x11, "ARMv8") \
__PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \
__PMC_CLASS(E500, 0x13, "Freescale e500 class")
enum pmc_class {
#undef __PMC_CLASS
@ -156,7 +156,7 @@ enum pmc_class {
};
#define PMC_CLASS_FIRST PMC_CLASS_TSC
#define PMC_CLASS_LAST PMC_CLASS_SOFT
#define PMC_CLASS_LAST PMC_CLASS_E500
/*
* A PMC can be in the following states: