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There is nothing special that requires SSE to be only on 686 class cpus.
This enables 586-only SMP kernels to compile again. Problem reported by: Jacek Jedrzejczak <jacol@ids.gda.pl>
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=81879
@ -62,8 +62,8 @@ static void init_6x86(void);
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static void init_6x86MX(void);
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static void init_ppro(void);
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static void init_mendocino(void);
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void enable_sse(void);
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#endif
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void enable_sse(void);
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int hw_instruction_sse = 0;
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SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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@ -507,7 +507,9 @@ init_mendocino(void)
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write_eflags(eflags);
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#endif /* CPU_PPRO2CELERON */
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}
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#endif /* I686_CPU */
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/*
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* Initialize CR4 (Control register 4) to enable SSE instructions.
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*/
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@ -522,8 +524,6 @@ enable_sse(void)
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#endif
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}
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#endif /* I686_CPU */
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void
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initializecpu(void)
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{
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@ -571,9 +571,7 @@ initializecpu(void)
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default:
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break;
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}
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#ifdef I686_CPU
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enable_sse();
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#endif
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#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
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/*
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@ -62,8 +62,8 @@ static void init_6x86(void);
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static void init_6x86MX(void);
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static void init_ppro(void);
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static void init_mendocino(void);
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void enable_sse(void);
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#endif
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void enable_sse(void);
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int hw_instruction_sse = 0;
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SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD,
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@ -507,7 +507,9 @@ init_mendocino(void)
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write_eflags(eflags);
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#endif /* CPU_PPRO2CELERON */
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}
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#endif /* I686_CPU */
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/*
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* Initialize CR4 (Control register 4) to enable SSE instructions.
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*/
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@ -522,8 +524,6 @@ enable_sse(void)
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#endif
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}
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#endif /* I686_CPU */
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void
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initializecpu(void)
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{
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@ -571,9 +571,7 @@ initializecpu(void)
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default:
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break;
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}
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#ifdef I686_CPU
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enable_sse();
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#endif
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#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE)
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/*
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