1
0
mirror of https://git.FreeBSD.org/src.git synced 2024-12-16 10:20:30 +00:00

Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").

Reviewed by:	jhb, peter (early amd64 version)
This commit is contained in:
Jung-uk Kim 2008-11-26 19:25:13 +00:00
parent 54dd5ca200
commit 5113aa0af3
Notes: svn2git 2020-12-20 02:59:44 +00:00
svn path=/head/; revision=185341
26 changed files with 221 additions and 119 deletions

View File

@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
#include <sys/smp.h>
#include <sys/sysctl.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -677,8 +678,8 @@ amd64_mem_drvinit(void *unused)
return;
if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
return;
if ((strcmp(cpu_vendor, "GenuineIntel") != 0) &&
(strcmp(cpu_vendor, "AuthenticAMD") != 0))
if (cpu_vendor_id != CPU_VENDOR_INTEL &&
cpu_vendor_id != CPU_VENDOR_AMD)
return;
mem_range_softc.mr_op = &amd64_mrops;
}

View File

@ -69,6 +69,7 @@ void identify_cpu(void);
void earlysetcpuclass(void);
void panicifcpuunsupported(void);
static u_int find_cpu_vendor_id(void);
static void print_AMD_info(void);
static void print_AMD_assoc(int i);
@ -95,6 +96,14 @@ static struct {
{ "Sledgehammer", CPUCLASS_K8 }, /* CPU_SLEDGEHAMMER */
};
static struct {
char *vendor;
u_int vendor_id;
} cpu_vendors[] = {
{ INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
{ AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
};
int cpu_cores;
int cpu_logical;
@ -122,10 +131,10 @@ printcpuinfo(void)
}
}
if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
if (cpu_vendor_id == CPU_VENDOR_INTEL) {
/* Please make up your mind folks! */
strcat(cpu_model, "EM64T");
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
/*
* Values taken from AMD Processor Recognition
* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
@ -165,13 +174,13 @@ printcpuinfo(void)
printf("Unknown"); /* will panic below... */
}
printf("-class CPU)\n");
if(*cpu_vendor)
printf(" Origin = \"%s\"",cpu_vendor);
if(cpu_id)
if (*cpu_vendor)
printf(" Origin = \"%s\"", cpu_vendor);
if (cpu_id)
printf(" Id = 0x%x", cpu_id);
if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0) {
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD) {
printf(" Stepping = %u", cpu_id & 0xf);
if (cpu_high > 0) {
u_int cmp = 1, htt = 1;
@ -343,8 +352,8 @@ printcpuinfo(void)
);
}
if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
"AuthenticAMD") == 0)
if ((cpu_feature & CPUID_HTT) &&
cpu_vendor_id == CPU_VENDOR_AMD)
cpu_feature &= ~CPUID_HTT;
/*
@ -352,7 +361,7 @@ printcpuinfo(void)
* mention the capability.
*/
if (!tsc_is_invariant &&
(strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
(cpu_vendor_id == CPU_VENDOR_AMD &&
((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
AMD64_CPU_FAMILY(cpu_id) >= 0x10 ||
cpu_id == 0x60fb2))) {
@ -366,10 +375,10 @@ printcpuinfo(void)
*/
if (cpu_feature & CPUID_HTT)
htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(amd_feature2 & AMDID2_CMP))
cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
(cpu_high >= 4)) {
cpuid_count(4, 0, regs);
if ((regs[0] & 0x1f) != 0)
@ -391,7 +400,7 @@ printcpuinfo(void)
if (!bootverbose)
return;
if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
if (cpu_vendor_id == CPU_VENDOR_AMD)
print_AMD_info();
}
@ -450,6 +459,7 @@ identify_cpu(void)
((u_int *)&cpu_vendor)[1] = regs[3];
((u_int *)&cpu_vendor)[2] = regs[2];
cpu_vendor[12] = '\0';
cpu_vendor_id = find_cpu_vendor_id();
do_cpuid(1, regs);
cpu_id = regs[0];
@ -457,8 +467,8 @@ identify_cpu(void)
cpu_feature = regs[3];
cpu_feature2 = regs[2];
if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0) {
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD) {
do_cpuid(0x80000000, regs);
cpu_exthigh = regs[0];
}
@ -480,6 +490,17 @@ identify_cpu(void)
cpu = CPU_CLAWHAMMER;
}
static u_int
find_cpu_vendor_id(void)
{
int i;
for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
return (cpu_vendors[i].vendor_id);
return (0);
}
static void
print_AMD_assoc(int i)
{

View File

@ -60,6 +60,7 @@ u_int cpu_id; /* Stepping ID */
u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */
u_int cpu_procinfo2; /* Multicore info */
char cpu_vendor[20]; /* CPU Origin code */
u_int cpu_vendor_id; /* CPU vendor ID */
u_int cpu_fxsr; /* SSE enabled */
u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */

View File

@ -323,7 +323,7 @@ lapic_setup(int boot)
/* XXX: Error and thermal LVTs */
if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
if (cpu_vendor_id == CPU_VENDOR_AMD) {
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family. This feature renders

View File

@ -57,6 +57,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#include <machine/apicreg.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/mp_watchdog.h>
#include <machine/pcb.h>
@ -374,8 +375,7 @@ cpu_mp_start(void)
* First determine if this is an Intel processor which claims
* to have hyperthreading support.
*/
if ((cpu_feature & CPUID_HTT) &&
(strcmp(cpu_vendor, "GenuineIntel") == 0)) {
if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
/*
* If the "deterministic cache parameters" cpuid calls
* are available, use them.

View File

@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
#include <sys/sx.h>
#include <sys/systm.h>
#include <machine/apicreg.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/frame.h>
#include <machine/intr_machdep.h>
@ -211,8 +212,8 @@ msi_init(void)
{
/* Check if we have a supported CPU. */
if (!(strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0))
if (!(cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD))
return;
msi_enabled = 1;

View File

@ -33,15 +33,21 @@
/*
* Classes of processor.
*/
#define CPUCLASS_X86 0 /* X86 */
#define CPUCLASS_K8 1 /* K8 AMD64 class */
#define CPUCLASS_X86 0 /* X86 */
#define CPUCLASS_K8 1 /* K8 AMD64 class */
/*
* Kinds of processor.
*/
#define CPU_X86 0 /* Intel */
#define CPU_CLAWHAMMER 1 /* AMD Clawhammer */
#define CPU_SLEDGEHAMMER 2 /* AMD Sledgehammer */
#define CPU_X86 0 /* Intel */
#define CPU_CLAWHAMMER 1 /* AMD Clawhammer */
#define CPU_SLEDGEHAMMER 2 /* AMD Sledgehammer */
/*
* Vendors of processor.
*/
#define CPU_VENDOR_AMD 0x1022 /* AMD */
#define CPU_VENDOR_INTEL 0x8086 /* Intel */
#ifndef LOCORE
extern int cpu;

View File

@ -52,6 +52,7 @@ extern u_int cpu_mxcsr_mask;
extern u_int cpu_procinfo;
extern u_int cpu_procinfo2;
extern char cpu_vendor[];
extern u_int cpu_vendor_id;
extern char kstack[];
extern char sigcode[];
extern int szsigcode;

View File

@ -196,8 +196,8 @@
/*
* CPUID manufacturers identifiers
*/
#define INTEL_VENDOR_ID "GenuineIntel"
#define AMD_VENDOR_ID "AuthenticAMD"
#define AMD_VENDOR_ID "AuthenticAMD"
#define INTEL_VENDOR_ID "GenuineIntel"
/*
* Model-specific registers for the i386 family

View File

@ -45,6 +45,7 @@ __FBSDID("$FreeBSD$");
#include <machine/specialreg.h>
#include <machine/cpufunc.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
struct coretemp_softc {
@ -94,7 +95,7 @@ coretemp_identify(driver_t *driver, device_t parent)
return;
/* Check that CPUID 0x06 is supported and the vendor is Intel.*/
if (cpu_high < 6 || strcmp(cpu_vendor, "GenuineIntel"))
if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL)
return;
/*
* CPUID 0x06 returns 1 if the processor has on-die thermal

View File

@ -37,6 +37,7 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <machine/cpu.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -79,7 +80,7 @@ pmc_intel_initialize(void)
enum pmc_cputype cputype;
int error, model, nclasses, ncpus;
KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0,
KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
("[intel,%d] Initializing non-intel processor", __LINE__));
PMCDBG(MDP,INI,0, "intel-initialize cpuid=0x%x", cpu_id);

View File

@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -1610,7 +1611,7 @@ pmc_p4_initialize(struct pmc_mdep *md, int ncpus)
struct p4_event_descr *pe;
KASSERT(md != NULL, ("[p4,%d] md is NULL", __LINE__));
KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0,
KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
("[p4,%d] Initializing non-intel processor", __LINE__));
PMCDBG(MDP,INI,1, "%s", "p4-initialize");

View File

@ -41,6 +41,7 @@ __FBSDID("$FreeBSD$");
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/pmc_mdep.h>
#include <machine/specialreg.h>
@ -779,7 +780,7 @@ pmc_p6_initialize(struct pmc_mdep *md, int ncpus)
{
struct pmc_classdep *pcd;
KASSERT(strcmp(cpu_vendor, "GenuineIntel") == 0,
KASSERT(cpu_vendor_id == CPU_VENDOR_INTEL,
("[p6,%d] Initializing non-intel processor", __LINE__));
PMCDBG(MDP,INI,1, "%s", "p6-initialize");

View File

@ -38,6 +38,7 @@ __FBSDID("$FreeBSD$");
#include <sys/systm.h>
#include <machine/cpu.h>
#include <machine/cputypes.h>
#include <machine/apicreg.h>
#include <machine/pmc_mdep.h>
#include <machine/md_var.h>
@ -252,9 +253,9 @@ pmc_md_initialize()
/* determine the CPU kind */
md = NULL;
if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
if (cpu_vendor_id == CPU_VENDOR_AMD)
md = pmc_amd_initialize();
else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
else if (cpu_vendor_id == CPU_VENDOR_INTEL)
md = pmc_intel_initialize();
else
KASSERT(0, ("[x86,%d] Unknown vendor", __LINE__));
@ -270,9 +271,9 @@ pmc_md_initialize()
void
pmc_md_finalize(struct pmc_mdep *md)
{
if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
if (cpu_vendor_id == CPU_VENDOR_AMD)
pmc_amd_finalize(md);
else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
else if (cpu_vendor_id == CPU_VENDOR_INTEL)
pmc_intel_finalize(md);
else
KASSERT(0, ("[x86,%d] Unknown vendor", __LINE__));

View File

@ -39,6 +39,7 @@ __FBSDID("$FreeBSD$");
#include "cpufreq_if.h"
#include <machine/clock.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -54,6 +55,10 @@ __FBSDID("$FreeBSD$");
#define MSR_MISC_ENABLE 0x1a0
#define MSR_SS_ENABLE (1<<16)
#ifndef CPU_VENDOR_CENTAUR
#define CPU_VENDOR_CENTAUR 0x111d
#endif
/* Frequency and MSR control values. */
typedef struct {
uint16_t freq;
@ -64,7 +69,7 @@ typedef struct {
/* Identifying characteristics of a processor and supported frequencies. */
typedef struct {
const char *vendor;
const u_int vendor_id;
uint32_t id32;
freq_info *freqtab;
} cpu_info;
@ -88,12 +93,10 @@ struct est_softc {
#define FREQ_INFO(MHz, mV, bus_clk) \
FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
{ intel_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
{ CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
{ centaur_id, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
{ CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
const char intel_id[] = "GenuineIntel";
const char centaur_id[] = "CentaurHauls";
static int msr_info_enabled = 0;
TUNABLE_INT("hw.est.msr_info", &msr_info_enabled);
@ -891,7 +894,7 @@ static cpu_info ESTprocs[] = {
CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
{ NULL, 0, NULL },
{ 0, 0, NULL },
};
static void est_identify(driver_t *driver, device_t parent);
@ -958,8 +961,8 @@ est_identify(driver_t *driver, device_t parent)
return;
/* Check that CPUID is supported and the vendor is Intel.*/
if (cpu_high == 0 || (strcmp(cpu_vendor, intel_id) != 0 &&
strcmp(cpu_vendor, centaur_id) != 0))
if (cpu_high == 0 || (cpu_vendor_id != CPU_VENDOR_INTEL &&
cpu_vendor_id != CPU_VENDOR_CENTAUR))
return;
/*
@ -1159,7 +1162,7 @@ est_table_info(device_t dev, uint64_t msr, freq_info **freqs)
/* Find a table which matches (vendor, id32). */
id = msr >> 32;
for (p = ESTprocs; p->id32 != 0; p++) {
if (strcmp(p->vendor, cpu_vendor) == 0 && p->id32 == id)
if (p->vendor_id == cpu_vendor_id && p->id32 == id)
break;
}
if (p->id32 == 0)

View File

@ -35,6 +35,7 @@ __FBSDID("$FreeBSD$");
#include <sys/smp.h>
#include <sys/sysctl.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -677,8 +678,8 @@ i686_mem_drvinit(void *unused)
return;
if ((cpu_id & 0xf00) != 0x600 && (cpu_id & 0xf00) != 0xf00)
return;
if ((strcmp(cpu_vendor, "GenuineIntel") != 0) &&
(strcmp(cpu_vendor, "AuthenticAMD") != 0))
if (cpu_vendor_id != CPU_VENDOR_INTEL &&
cpu_vendor_id != CPU_VENDOR_AMD)
return;
mem_range_softc.mr_op = &i686_mrops;
}

View File

@ -77,6 +77,7 @@ void panicifcpuunsupported(void);
static void identifycyrix(void);
static void init_exthigh(void);
static u_int find_cpu_vendor_id(void);
static void print_AMD_info(void);
static void print_INTEL_info(void);
static void print_INTEL_TLB(u_int data);
@ -138,6 +139,26 @@ static struct {
{ "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
};
static struct {
char *vendor;
u_int vendor_id;
} cpu_vendors[] = {
{ INTEL_VENDOR_ID, CPU_VENDOR_INTEL }, /* GenuineIntel */
{ AMD_VENDOR_ID, CPU_VENDOR_AMD }, /* AuthenticAMD */
{ CENTAUR_VENDOR_ID, CPU_VENDOR_CENTAUR }, /* CentaurHauls */
{ NSC_VENDOR_ID, CPU_VENDOR_NSC }, /* Geode by NSC */
{ CYRIX_VENDOR_ID, CPU_VENDOR_CYRIX }, /* CyrixInstead */
{ TRANSMETA_VENDOR_ID, CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
{ SIS_VENDOR_ID, CPU_VENDOR_SIS }, /* SiS SiS SiS */
{ UMC_VENDOR_ID, CPU_VENDOR_UMC }, /* UMC UMC UMC */
{ NEXGEN_VENDOR_ID, CPU_VENDOR_NEXGEN }, /* NexGenDriven */
{ RISE_VENDOR_ID, CPU_VENDOR_RISE }, /* RiseRiseRise */
#if 0
/* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
{ "TransmetaCPU", CPU_VENDOR_TRANSMETA },
#endif
};
int cpu_cores;
int cpu_logical;
@ -153,12 +174,11 @@ init_exthigh(void)
if (done == 0) {
if (cpu_high > 0 &&
(strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
strcmp(cpu_vendor, "CentaurHauls") == 0 ||
strcmp(cpu_vendor, "Geode by NSC") == 0)) {
(cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
cpu_vendor_id == CPU_VENDOR_NSC)) {
do_cpuid(0x80000000, regs);
if (regs[0] >= 0x80000000)
cpu_exthigh = regs[0];
@ -189,7 +209,7 @@ printcpuinfo(void)
}
}
if (strcmp(cpu_vendor, "GenuineIntel") == 0) {
if (cpu_vendor_id == CPU_VENDOR_INTEL) {
if ((cpu_id & 0xf00) > 0x300) {
u_int brand_index;
u_int model;
@ -333,7 +353,7 @@ printcpuinfo(void)
cpu_brandtable[brand_index]);
}
}
} else if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_AMD) {
/*
* Values taken from AMD Processor Recognition
* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
@ -413,7 +433,7 @@ printcpuinfo(void)
enable_K6_wt_alloc();
}
#endif
} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
strcpy(cpu_model, "Cyrix ");
switch (cpu_id & 0xff0) {
case 0x440:
@ -549,7 +569,7 @@ printcpuinfo(void)
}
break;
}
} else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_RISE) {
strcpy(cpu_model, "Rise ");
switch (cpu_id & 0xff0) {
case 0x500:
@ -558,7 +578,7 @@ printcpuinfo(void)
default:
strcat(cpu_model, "Unknown");
}
} else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
switch (cpu_id & 0xff0) {
case 0x540:
strcpy(cpu_model, "IDT WinChip C6");
@ -589,9 +609,9 @@ printcpuinfo(void)
default:
strcpy(cpu_model, "VIA/IDT Unknown");
}
} else if (strcmp(cpu_vendor, "IBM") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_IBM) {
strcpy(cpu_model, "Blue Lightning CPU");
} else if (strcmp(cpu_vendor, "Geode by NSC") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_NSC) {
switch (cpu_id & 0xfff) {
case 0x540:
strcpy(cpu_model, "Geode SC1100");
@ -655,17 +675,16 @@ printcpuinfo(void)
if(cpu_id)
printf(" Id = 0x%x", cpu_id);
if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
strcmp(cpu_vendor, "TransmetaCPU") == 0 ||
strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
strcmp(cpu_vendor, "CentaurHauls") == 0 ||
strcmp(cpu_vendor, "Geode by NSC") == 0 ||
((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
cpu_vendor_id == CPU_VENDOR_RISE ||
cpu_vendor_id == CPU_VENDOR_CENTAUR ||
cpu_vendor_id == CPU_VENDOR_NSC ||
(cpu_vendor_id == CPU_VENDOR_CYRIX &&
((cpu_id & 0xf00) > 0x500))) {
printf(" Stepping = %u", cpu_id & 0xf);
if (strcmp(cpu_vendor, "CyrixInstead") == 0)
if (cpu_vendor_id == CPU_VENDOR_CYRIX)
printf(" DIR=0x%04x", cyrix_did);
if (cpu_high > 0) {
u_int cmp = 1, htt = 1;
@ -837,8 +856,8 @@ printcpuinfo(void)
);
}
if (cpu_feature & CPUID_HTT && strcmp(cpu_vendor,
"AuthenticAMD") == 0)
if ((cpu_feature & CPUID_HTT) &&
cpu_vendor_id == CPU_VENDOR_AMD)
cpu_feature &= ~CPUID_HTT;
/*
@ -846,8 +865,8 @@ printcpuinfo(void)
* mention the capability.
*/
if (!tsc_is_invariant &&
((strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
(strcmp(cpu_vendor, "GenuineIntel") == 0))&&
((cpu_vendor_id == CPU_VENDOR_AMD ||
cpu_vendor_id == CPU_VENDOR_INTEL) &&
((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
I386_CPU_FAMILY(cpu_id) >= 0x10 ||
cpu_id == 0x60fb2))) {
@ -861,10 +880,10 @@ printcpuinfo(void)
*/
if (cpu_feature & CPUID_HTT)
htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
if (cpu_vendor_id == CPU_VENDOR_AMD &&
(amd_feature2 & AMDID2_CMP))
cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
else if (strcmp(cpu_vendor, "GenuineIntel") == 0 &&
else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
(cpu_high >= 4)) {
cpuid_count(4, 0, regs);
if ((regs[0] & 0x1f) != 0)
@ -878,7 +897,7 @@ printcpuinfo(void)
printf("\n Logical CPUs per core: %d",
cpu_logical);
}
} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
printf(" DIR=0x%04x", cyrix_did);
printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
@ -887,7 +906,7 @@ printcpuinfo(void)
printf("\n CPU cache: write-through mode");
#endif
}
if (strcmp(cpu_vendor, "CentaurHauls") == 0)
if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
print_via_padlock_info();
/* Avoid ugly blank lines: only print newline when we have to. */
@ -897,12 +916,11 @@ printcpuinfo(void)
if (!bootverbose)
return;
if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
if (cpu_vendor_id == CPU_VENDOR_AMD)
print_AMD_info();
else if (strcmp(cpu_vendor, "GenuineIntel") == 0)
else if (cpu_vendor_id == CPU_VENDOR_INTEL)
print_INTEL_info();
else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
strcmp(cpu_vendor, "TransmetaCPU") == 0)
else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
print_transmeta_info();
}
@ -1097,9 +1115,11 @@ finishidentcpu(void)
u_char ccr3;
u_int regs[4];
cpu_vendor_id = find_cpu_vendor_id();
/* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0) {
if (cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD) {
init_exthigh();
if (cpu_exthigh >= 0x80000001) {
do_cpuid(0x80000001, regs);
@ -1114,7 +1134,7 @@ finishidentcpu(void)
do_cpuid(0x80000008, regs);
cpu_procinfo2 = regs[2];
}
} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
} else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
if (cpu == CPU_486) {
/*
* These conditions are equivalent to:
@ -1124,6 +1144,7 @@ finishidentcpu(void)
isblue = identblue();
if (isblue == IDENTBLUE_IBMCPU) {
strcpy(cpu_vendor, "IBM");
cpu_vendor_id = CPU_VENDOR_IBM;
cpu = CPU_BLUE;
return;
}
@ -1197,12 +1218,24 @@ finishidentcpu(void)
isblue = identblue();
if (isblue == IDENTBLUE_IBMCPU) {
strcpy(cpu_vendor, "IBM");
cpu_vendor_id = CPU_VENDOR_IBM;
cpu = CPU_BLUE;
return;
}
}
}
static u_int
find_cpu_vendor_id(void)
{
int i;
for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
return (cpu_vendors[i].vendor_id);
return (0);
}
static void
print_AMD_assoc(int i)
{

View File

@ -90,6 +90,7 @@ u_int cpu_id = 0; /* Stepping ID */
u_int cpu_procinfo = 0; /* HyperThreading Info / Brand Index / CLFUSH */
u_int cpu_procinfo2 = 0; /* Multicore info */
char cpu_vendor[20] = ""; /* CPU Origin code */
u_int cpu_vendor_id = 0; /* CPU vendor ID */
SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD,
&via_feature_rng, 0, "VIA C3/C7 RNG feature available in CPU");

View File

@ -33,6 +33,7 @@ __FBSDID("$FreeBSD$");
#include <sys/malloc.h>
#include <sys/memrange.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -175,7 +176,7 @@ static void
k6_mem_drvinit(void *unused)
{
if (strcmp(cpu_vendor, "AuthenticAMD") != 0)
if (cpu_vendor_id != CPU_VENDOR_AMD)
return;
if ((cpu_id & 0xf00) != 0x500)
return;

View File

@ -325,7 +325,7 @@ lapic_setup(int boot)
/* XXX: Error and thermal LVTs */
if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
if (cpu_vendor_id == CPU_VENDOR_AMD) {
/*
* Detect the presence of C1E capability mostly on latest
* dual-cores (or future) k8 family. This feature renders
@ -1073,7 +1073,7 @@ apic_init(void *dummy __unused)
* CPUs during early startup. We need to turn the local APIC back
* on on such CPUs now.
*/
if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 &&
if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL &&
(cpu_id & 0xff0) == 0x610) {
apic_base = rdmsr(MSR_APICBASE);
apic_base |= APICBASE_ENABLED;

View File

@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
#include <sys/sysctl.h>
#include <sys/types.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/specialreg.h>
@ -262,8 +263,8 @@ tmx86_longrun_profile_sysctl(SYSCTL_HANDLER_ARGS)
static void
setup_tmx86_longrun(void *dummy __unused)
{
if (strcmp(cpu_vendor, "GenuineTMx86") != 0 &&
strcmp(cpu_vendor, "TransmetaCPU") != 0)
if (cpu_vendor_id != CPU_VENDOR_TRANSMETA)
return;
crusoe_longrun = tmx86_get_longrun_mode();

View File

@ -72,6 +72,7 @@ __FBSDID("$FreeBSD$");
#include <vm/vm_extern.h>
#include <machine/apicreg.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/mp_watchdog.h>
#include <machine/pcb.h>
@ -422,8 +423,7 @@ cpu_mp_start(void)
* First determine if this is an Intel processor which claims
* to have hyperthreading support.
*/
if ((cpu_feature & CPUID_HTT) &&
(strcmp(cpu_vendor, "GenuineIntel") == 0)) {
if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
/*
* If the "deterministic cache parameters" cpuid calls
* are available, use them.

View File

@ -46,6 +46,7 @@ __FBSDID("$FreeBSD$");
#include <sys/sx.h>
#include <sys/systm.h>
#include <machine/apicreg.h>
#include <machine/cputypes.h>
#include <machine/md_var.h>
#include <machine/frame.h>
#include <machine/intr_machdep.h>
@ -211,8 +212,8 @@ msi_init(void)
{
/* Check if we have a supported CPU. */
if (!(strcmp(cpu_vendor, "GenuineIntel") == 0 ||
strcmp(cpu_vendor, "AuthenticAMD") == 0))
if (!(cpu_vendor_id == CPU_VENDOR_INTEL ||
cpu_vendor_id == CPU_VENDOR_AMD))
return;
msi_enabled = 1;

View File

@ -33,33 +33,49 @@
/*
* Classes of processor.
*/
#define CPUCLASS_286 0
#define CPUCLASS_386 1
#define CPUCLASS_486 2
#define CPUCLASS_586 3
#define CPUCLASS_686 4
#define CPUCLASS_286 0
#define CPUCLASS_386 1
#define CPUCLASS_486 2
#define CPUCLASS_586 3
#define CPUCLASS_686 4
/*
* Kinds of processor.
*/
#define CPU_286 0 /* Intel 80286 */
#define CPU_386SX 1 /* Intel 80386SX */
#define CPU_386 2 /* Intel 80386DX */
#define CPU_486SX 3 /* Intel 80486SX */
#define CPU_486 4 /* Intel 80486DX */
#define CPU_586 5 /* Intel P.....m (I hate lawyers; it's TM) */
#define CPU_486DLC 6 /* Cyrix 486DLC */
#define CPU_686 7 /* Pentium Pro */
#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */
#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */
#define CPU_BLUE 10 /* IBM BlueLighting CPU */
#define CPU_M2 11 /* Cyrix M2 (aka enhanced 6x86 with MMX */
#define CPU_NX586 12 /* NexGen (now AMD) 586 */
#define CPU_CY486DX 13 /* Cyrix 486S/DX/DX2/DX4 */
#define CPU_PII 14 /* Intel Pentium II */
#define CPU_PIII 15 /* Intel Pentium III */
#define CPU_P4 16 /* Intel Pentium 4 */
#define CPU_GEODE1100 17 /* NS Geode SC1100 */
#define CPU_286 0 /* Intel 80286 */
#define CPU_386SX 1 /* Intel 80386SX */
#define CPU_386 2 /* Intel 80386DX */
#define CPU_486SX 3 /* Intel 80486SX */
#define CPU_486 4 /* Intel 80486DX */
#define CPU_586 5 /* Intel Pentium */
#define CPU_486DLC 6 /* Cyrix 486DLC */
#define CPU_686 7 /* Pentium Pro */
#define CPU_M1SC 8 /* Cyrix M1sc (aka 5x86) */
#define CPU_M1 9 /* Cyrix M1 (aka 6x86) */
#define CPU_BLUE 10 /* IBM BlueLighting CPU */
#define CPU_M2 11 /* Cyrix M2 (enhanced 6x86 with MMX) */
#define CPU_NX586 12 /* NexGen (now AMD) 586 */
#define CPU_CY486DX 13 /* Cyrix 486S/DX/DX2/DX4 */
#define CPU_PII 14 /* Intel Pentium II */
#define CPU_PIII 15 /* Intel Pentium III */
#define CPU_P4 16 /* Intel Pentium 4 */
#define CPU_GEODE1100 17 /* NS Geode SC1100 */
/*
* Vendors of processor.
*/
#define CPU_VENDOR_NSC 0x100b /* NSC */
#define CPU_VENDOR_IBM 0x1014 /* IBM */
#define CPU_VENDOR_AMD 0x1022 /* AMD */
#define CPU_VENDOR_SIS 0x1039 /* SiS */
#define CPU_VENDOR_UMC 0x1060 /* UMC */
#define CPU_VENDOR_NEXGEN 0x1074 /* Nexgen */
#define CPU_VENDOR_CYRIX 0x1078 /* Cyrix */
#define CPU_VENDOR_IDT 0x111d /* Centaur/IDT/VIA */
#define CPU_VENDOR_TRANSMETA 0x1279 /* Transmeta */
#define CPU_VENDOR_INTEL 0x8086 /* Intel */
#define CPU_VENDOR_RISE 0xdead2bad /* Rise */
#define CPU_VENDOR_CENTAUR CPU_VENDOR_IDT
#ifndef LOCORE
extern int cpu;

View File

@ -59,6 +59,7 @@ extern u_int cpu_mxcsr_mask;
extern u_int cpu_procinfo;
extern u_int cpu_procinfo2;
extern char cpu_vendor[];
extern u_int cpu_vendor_id;
extern u_int cyrix_did;
extern char kstack[];
extern char sigcode[];

View File

@ -195,8 +195,16 @@
/*
* CPUID manufacturers identifiers
*/
#define INTEL_VENDOR_ID "GenuineIntel"
#define AMD_VENDOR_ID "AuthenticAMD"
#define AMD_VENDOR_ID "AuthenticAMD"
#define CENTAUR_VENDOR_ID "CentaurHauls"
#define CYRIX_VENDOR_ID "CyrixInstead"
#define INTEL_VENDOR_ID "GenuineIntel"
#define NEXGEN_VENDOR_ID "NexGenDriven"
#define NSC_VENDOR_ID "Geode by NSC"
#define RISE_VENDOR_ID "RiseRiseRise"
#define SIS_VENDOR_ID "SiS SiS SiS "
#define TRANSMETA_VENDOR_ID "GenuineTMx86"
#define UMC_VENDOR_ID "UMC UMC UMC "
/*
* Model-specific registers for the i386 family