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save changes for handling 5416/5418 parts
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parent
724c193aed
commit
517eabc6fa
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=166014
@ -533,24 +533,6 @@ ath_rate_tx_complete(struct ath_softc *sc, struct ath_node *an,
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short_tries, long_tries);
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return;
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}
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if (ts->ts_status) { /* this packet failed */
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DPRINTF(sc, ATH_DEBUG_RATE,
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"%s: %s size %d rate/try [%d/%d %d/%d %d/%d %d/%d] FAIL tries [%d/%d]\n",
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__func__,
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ether_sprintf(an->an_node.ni_macaddr),
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bin_to_size(size_to_bin(frame_size)),
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sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate0)].ieeerate,
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MS(ds0->ds_ctl2, AR_XmitDataTries0),
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sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate1)].ieeerate,
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MS(ds0->ds_ctl2, AR_XmitDataTries1),
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sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate2)].ieeerate,
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MS(ds0->ds_ctl2, AR_XmitDataTries2),
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sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate3)].ieeerate,
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MS(ds0->ds_ctl2, AR_XmitDataTries3),
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short_tries, long_tries);
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}
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mrr = sc->sc_mrretry && !(ic->ic_flags & IEEE80211_F_USEPROT);
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if (!mrr || !(ts->ts_rate & HAL_TXSTAT_ALTRATE)) {
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int ndx = rate_to_ndx(sn, final_rate);
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@ -571,32 +553,43 @@ ath_rate_tx_complete(struct ath_softc *sc, struct ath_node *an,
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0, 0,
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short_tries, long_tries, ts->ts_status);
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} else {
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int rate0, tries0, ndx0;
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int rate1, tries1, ndx1;
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int rate2, tries2, ndx2;
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int rate3, tries3, ndx3;
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int hwrate0, rate0, tries0, ndx0;
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int hwrate1, rate1, tries1, ndx1;
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int hwrate2, rate2, tries2, ndx2;
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int hwrate3, rate3, tries3, ndx3;
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int finalTSIdx = ts->ts_finaltsi;
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/*
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* Process intermediate rates that failed.
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*/
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rate0 = sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate0)].ieeerate;
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if (sc->sc_ah->ah_magic != 0x20065416) {
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hwrate0 = MS(ds0->ds_ctl3, AR_XmitRate0);
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hwrate1 = MS(ds0->ds_ctl3, AR_XmitRate1);
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hwrate2 = MS(ds0->ds_ctl3, AR_XmitRate2);
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hwrate3 = MS(ds0->ds_ctl3, AR_XmitRate3);
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} else {
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hwrate0 = MS(ds0->ds_ctl3, AR5416_XmitRate0);
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hwrate1 = MS(ds0->ds_ctl3, AR5416_XmitRate1);
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hwrate2 = MS(ds0->ds_ctl3, AR5416_XmitRate2);
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hwrate3 = MS(ds0->ds_ctl3, AR5416_XmitRate3);
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}
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rate0 = sc->sc_hwmap[hwrate0].ieeerate;
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tries0 = MS(ds0->ds_ctl2, AR_XmitDataTries0);
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ndx0 = rate_to_ndx(sn, rate0);
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rate1 = sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate1)].ieeerate;
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rate1 = sc->sc_hwmap[hwrate1].ieeerate;
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tries1 = MS(ds0->ds_ctl2, AR_XmitDataTries1);
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ndx1 = rate_to_ndx(sn, rate1);
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rate2 = sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate2)].ieeerate;
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rate2 = sc->sc_hwmap[hwrate2].ieeerate;
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tries2 = MS(ds0->ds_ctl2, AR_XmitDataTries2);
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ndx2 = rate_to_ndx(sn, rate2);
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rate3 = sc->sc_hwmap[MS(ds0->ds_ctl3, AR_XmitRate3)].ieeerate;
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rate3 = sc->sc_hwmap[hwrate3].ieeerate;
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tries3 = MS(ds0->ds_ctl2, AR_XmitDataTries3);
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ndx3 = rate_to_ndx(sn, rate3);
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#if 1
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DPRINTF(sc, ATH_DEBUG_RATE,
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"%s: %s size %d finaltsidx %d tries %d %s rate/try [%d/%d %d/%d %d/%d %d/%d]\n",
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__func__, ether_sprintf(an->an_node.ni_macaddr),
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@ -608,7 +601,6 @@ ath_rate_tx_complete(struct ath_softc *sc, struct ath_node *an,
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rate1, tries1,
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rate2, tries2,
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rate3, tries3);
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#endif
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/*
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* NB: series > 0 are not penalized for failure
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@ -136,6 +136,16 @@ struct sample_node {
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#define AR_XmitRate3 0x000f8000 /* series 3 tx rate */
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#define AR_XmitRate3_S 15
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/* TX ds_ctl3 for 5416 */
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#define AR5416_XmitRate0 0x000000ff /* series 0 tx rate */
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#define AR5416_XmitRate0_S 0
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#define AR5416_XmitRate1 0x0000ff00 /* series 1 tx rate */
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#define AR5416_XmitRate1_S 8
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#define AR5416_XmitRate2 0x00ff0000 /* series 2 tx rate */
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#define AR5416_XmitRate2_S 16
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#define AR5416_XmitRate3 0xff000000 /* series 3 tx rate */
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#define AR5416_XmitRate3_S 24
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#define MS(_v, _f) (((_v) & (_f)) >> _f##_S)
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/*
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