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- Place the gcc memory barrier hint in the right place in the 80386 version
of atomic_store_rel(). - Use the 80386 versions of atomic_load_acq() and atomic_store_rel() that do not use serializing instructions on all UP kernels since a UP machine does need to synchronize with other CPUs. This trims lots of cycles from spin locks on UP kernels among other things. Benchmarked by: rwatson
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=137591
@ -172,13 +172,14 @@ atomic_cmpset_int(volatile u_int *dst, u_int exp, u_int src)
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#if defined(__GNUC__) || defined(__INTEL_COMPILER)
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#if defined(I386_CPU)
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#if !defined(SMP)
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/*
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* We assume that a = b will do atomic loads and stores.
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*
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* XXX: This is _NOT_ safe on a P6 or higher because it does not guarantee
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* memory ordering. These should only be used on a 386.
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* We assume that a = b will do atomic loads and stores. However, on a
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* PentiumPro or higher, reads may pass writes, so for that case we have
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* to use a serializing instruction (i.e. with LOCK) to do the load in
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* SMP kernels. For UP kernels, however, the cache of the single processor
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* is always consistent, so we don't need any memory barriers.
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*/
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#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
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static __inline u_##TYPE \
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@ -190,12 +191,12 @@ atomic_load_acq_##TYPE(volatile u_##TYPE *p) \
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static __inline void \
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atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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{ \
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*p = v; \
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__asm __volatile("" : : : "memory"); \
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*p = v; \
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} \
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struct __hack
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#else /* !defined(I386_CPU) */
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#else /* defined(SMP) */
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#define ATOMIC_STORE_LOAD(TYPE, LOP, SOP) \
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static __inline u_##TYPE \
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@ -224,7 +225,7 @@ atomic_store_rel_##TYPE(volatile u_##TYPE *p, u_##TYPE v)\
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} \
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struct __hack
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#endif /* defined(I386_CPU) */
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#endif /* !defined(SMP) */
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#else /* !(defined(__GNUC__) || defined(__INTEL_COMPILER)) */
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