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Add patch file for r275280.
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/projects/clang350-import/; revision=275281
@ -0,0 +1,90 @@
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Pull in r215811 from upstream llvm trunk (by Nico Weber):
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arm asm: Let .fpu enable instructions, PR20447.
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I'm not very happy with duplicating the fpu->feature mapping in ARMAsmParser.cpp
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and in clang's driver. See the bug for a patch that doesn't do that, and the
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review thread [1] for why this duplication exists.
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1: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20140811/231052.html
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This makes the .fpu directive work properly, so we can successfully
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assemble several .S files using the directive, under lib/libc/arm.
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Introduced here: http://svnweb.freebsd.org/changeset/base/275280
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Index: lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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===================================================================
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--- lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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+++ lib/Target/ARM/AsmParser/ARMAsmParser.cpp
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@@ -8621,6 +8621,30 @@ bool ARMAsmParser::parseDirectiveCPU(SMLoc L) {
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return false;
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}
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+// FIXME: This is duplicated in getARMFPUFeatures() in
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+// tools/clang/lib/Driver/Tools.cpp
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+static const struct {
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+ const unsigned Fpu;
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+ const uint64_t Enabled;
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+ const uint64_t Disabled;
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+} Fpus[] = {
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+ {ARM::VFP, ARM::FeatureVFP2, ARM::FeatureNEON},
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+ {ARM::VFPV2, ARM::FeatureVFP2, ARM::FeatureNEON},
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+ {ARM::VFPV3, ARM::FeatureVFP3, ARM::FeatureNEON},
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+ {ARM::VFPV3_D16, ARM::FeatureVFP3 | ARM::FeatureD16, ARM::FeatureNEON},
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+ {ARM::VFPV4, ARM::FeatureVFP4, ARM::FeatureNEON},
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+ {ARM::VFPV4_D16, ARM::FeatureVFP4 | ARM::FeatureD16, ARM::FeatureNEON},
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+ {ARM::FP_ARMV8, ARM::FeatureFPARMv8,
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+ ARM::FeatureNEON | ARM::FeatureCrypto},
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+ {ARM::NEON, ARM::FeatureNEON, 0},
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+ {ARM::NEON_VFPV4, ARM::FeatureVFP4 | ARM::FeatureNEON, 0},
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+ {ARM::NEON_FP_ARMV8, ARM::FeatureFPARMv8 | ARM::FeatureNEON,
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+ ARM::FeatureCrypto},
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+ {ARM::CRYPTO_NEON_FP_ARMV8,
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+ ARM::FeatureFPARMv8 | ARM::FeatureNEON | ARM::FeatureCrypto, 0},
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+ {ARM::SOFTVFP, 0, 0},
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+};
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+
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/// parseDirectiveFPU
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/// ::= .fpu str
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bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
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@@ -8636,6 +8660,18 @@ bool ARMAsmParser::parseDirectiveFPU(SMLoc L) {
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return false;
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}
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+ for (const auto &Fpu : Fpus) {
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+ if (Fpu.Fpu != ID)
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+ continue;
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+
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+ // Need to toggle features that should be on but are off and that
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+ // should off but are on.
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+ unsigned Toggle = (Fpu.Enabled & ~STI.getFeatureBits()) |
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+ (Fpu.Disabled & STI.getFeatureBits());
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+ setAvailableFeatures(ComputeAvailableFeatures(STI.ToggleFeature(Toggle)));
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+ break;
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+ }
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+
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getTargetStreamer().emitFPU(ID);
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return false;
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}
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Index: test/MC/ARM/directive-fpu-instrs.s
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===================================================================
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--- test/MC/ARM/directive-fpu-instrs.s
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+++ test/MC/ARM/directive-fpu-instrs.s
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@@ -0,0 +1,16 @@
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+// RUN: llvm-mc -triple armv7-unknown-linux-gnueabi -mattr=+vfp3,+d16,-neon %s
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+
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+.fpu neon
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+VAND d3, d5, d5
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+vldr d21, [r7, #296]
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+
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+@ .thumb should not disable the prior .fpu neon
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+.thumb
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+
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+vmov q4, q11 @ v4si
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+str r6, [r7, #264]
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+mov r6, r5
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+vldr d21, [r7, #296]
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+add r9, r7, #216
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+
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+fstmfdd sp!, {d8, d9, d10, d11, d12, d13, d14, d15}
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