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Code Issues Releases Activity

Add some 11n bits from the if_ath_tx 11n branch:

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* Add the TID field in the TX status descriptor;
* Add in the 11n first/middle/last functions for fiddling
  with the descriptors. These are from the Linux and the
  reference driver, but I'm not (currently) using them.
* Add further AR_ISR_S5 register definitions.

Obtained from:	Linux ath9k, Atheros
This commit is contained in:
Adrian Chadd 2011-10-25 23:09:07 +00:00
parent 24f5f7ee4e
commit 5916ef68df
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=226759
5 changed files with 40 additions and 1 deletions
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1
sys/dev/ath/ath_hal/ah_desc.h
View File

@ -50,6 +50,7 @@ struct ath_tx_status {
/* #define ts_rssi ts_rssi_combined */
uint32_t ts_ba_low; /* blockack bitmap low */
uint32_t ts_ba_high; /* blockack bitmap high */
uint8_t ts_tid; /* TID */
uint32_t ts_evm0; /* evm bytes */
uint32_t ts_evm1;
uint32_t ts_evm2;

6
sys/dev/ath/ath_hal/ar5416/ar5416.h
View File

@ -339,8 +339,14 @@ extern u_int ar5416GetGlobalTxTimeout(struct ath_hal *ah);
extern void ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,
u_int durUpdateEn, u_int rtsctsRate, HAL_11N_RATE_SERIES series[],
u_int nseries, u_int flags);
extern void ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds,
u_int aggrLen, u_int numDelims);
extern void ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims);
extern void ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds);
extern void ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds);
extern void ar5416Set11nBurstDuration(struct ath_hal *ah, struct ath_desc *ds, u_int burstDuration);
extern const HAL_RATE_TABLE *ar5416GetRateTable(struct ath_hal *, u_int mode);

24
sys/dev/ath/ath_hal/ar5416/ar5416_xmit.c
View File

@ -504,6 +504,7 @@ ar5416ProcTxDesc(struct ath_hal *ah,
/* Update software copies of the HW status */
ts->ts_seqnum = MS(ds_txstatus[9], AR_SeqNum);
ts->ts_tstamp = AR_SendTimestamp(ds_txstatus);
ts->ts_tid = MS(ds_txstatus[9], AR_TxTid);
ts->ts_status = 0;
if (ds_txstatus[1] & AR_ExcessiveRetries)
@ -691,6 +692,19 @@ ar5416Set11nRateScenario(struct ath_hal *ah, struct ath_desc *ds,
| SM(rtsctsRate, AR_RTSCTSRate);
}
void
ar5416Set11nAggrFirst(struct ath_hal *ah, struct ath_desc *ds,
u_int aggrLen, u_int numDelims)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
ads->ds_ctl6 &= ~(AR_AggrLen | AR_PadDelim);
ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen) |
SM(numDelims, AR_PadDelim);
}
void
ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)
{
@ -710,6 +724,16 @@ ar5416Set11nAggrMiddle(struct ath_hal *ah, struct ath_desc *ds, u_int numDelims)
ds_txstatus[9] &= ~AR_TxDone;
}
void
ar5416Set11nAggrLast(struct ath_hal *ah, struct ath_desc *ds)
{
struct ar5416_desc *ads = AR5416DESC(ds);
ads->ds_ctl1 |= AR_IsAggr;
ads->ds_ctl1 &= ~AR_MoreAggr;
ads->ds_ctl6 &= ~AR_PadDelim;
}
void
ar5416Clr11nAggr(struct ath_hal *ah, struct ath_desc *ds)
{

2
sys/dev/ath/ath_hal/ar5416/ar5416desc.h
View File

@ -302,6 +302,8 @@ struct ar5416_desc {
#define AR_FinalTxIdx_S 21
#define AR_TxStatusRsvd82 0x01800000
#define AR_PowerMgmt 0x02000000
#define AR_TxTid 0xf0000000
#define AR_TxTid_S 28
#define AR_TxStatusRsvd83 0xfc000000
/***********

8
sys/dev/ath/ath_hal/ar5416/ar5416reg.h
View File

@ -260,7 +260,13 @@
#define AR_ISR_S5 0x0098
#define AR_ISR_S5_S 0x00d8
#define AR_ISR_S5_TIM_TIMER 0x00000010
#define AR_ISR_S5_GENTIMER7 0x00000080 // Mask for timer 7 trigger
#define AR_ISR_S5_TIM_TIMER 0x00000010 // TIM Timer ISR
#define AR_ISR_S5_DTIM_TIMER 0x00000020 // DTIM Timer ISR
#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 // ISR for generic timer trigger 7-15
#define AR_ISR_S5_GENTIMER_TRIG_S 0
#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 // ISR for generic timer threshold 7-15
#define AR_ISR_S5_GENTIMER_THRESH_S 16
#define AR_INTR_SPURIOUS 0xffffffff
#define AR_INTR_RTC_IRQ 0x00000001 /* rtc in shutdown state */