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Query and cache PCAM, MCAM registers on initialization in mlx5core.
On load_one, we now cache our capabilities registers internally, similar to QUERY_HCA_CAP. Capabilities can later be queried using macros introduced in this patch. Linux commit: 71862561f3a62015a11de16d1c306481e8415c08 Submitted by: slavash@ MFC after: 3 days Sponsored by: Mellanox Technologies
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Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=347272
@ -1050,6 +1050,12 @@ enum mlx5_mcam_feature_groups {
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MLX5_GET(qos_cap,\
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mdev->hca_caps_max[MLX5_CAP_QOS], cap)
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#define MLX5_CAP_PCAM_FEATURE(mdev, fld) \
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MLX5_GET(pcam_reg, (mdev)->caps.pcam, feature_cap_mask.enhanced_features.fld)
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#define MLX5_CAP_MCAM_FEATURE(mdev, fld) \
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MLX5_GET(mcam_reg, (mdev)->caps.mcam, mng_feature_cap_mask.enhanced_features.fld)
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#define MLX5_CAP_QCAM_REG(mdev, fld) \
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MLX5_GET(qcam_reg, (mdev)->caps.qcam, qos_access_reg_cap_mask.reg_cap.fld)
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@ -699,6 +699,8 @@ struct mlx5_core_dev {
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u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
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u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
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struct {
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u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
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u32 mcam[MLX5_ST_SZ_DW(mcam_reg)];
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u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
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u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
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} caps;
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@ -117,6 +117,20 @@ static int mlx5_get_qcam_reg(struct mlx5_core_dev *dev)
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MLX5_QCAM_REGS_FIRST_128);
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}
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static int mlx5_get_pcam_reg(struct mlx5_core_dev *dev)
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{
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return mlx5_query_pcam_reg(dev, dev->caps.pcam,
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MLX5_PCAM_FEATURE_ENHANCED_FEATURES,
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MLX5_PCAM_REGS_5000_TO_507F);
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}
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static int mlx5_get_mcam_reg(struct mlx5_core_dev *dev)
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{
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return mlx5_query_mcam_reg(dev, dev->caps.mcam,
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MLX5_MCAM_FEATURE_ENHANCED_FEATURES,
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MLX5_MCAM_REGS_FIRST_128);
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}
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int mlx5_query_hca_caps(struct mlx5_core_dev *dev)
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{
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int err;
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