mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-03 09:00:21 +00:00
Make 32-bit PowerPC kernels, like 64-bit PowerPC kernels, position-independent
executables. The goal here, not yet accomplished, is to let the e500 kernel run under QEMU by setting KERNBASE to something that fits in low memory and then having the kernel relocate itself at runtime.
This commit is contained in:
Nathan Whitehorn
parent
2c5c06a0d9
commit
5c845fde2e
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=279750
6
UPDATING
6
UPDATING
@ -31,6 +31,12 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 11.x IS SLOW:
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disable the most expensive debugging functionality run
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"ln -s 'abort:false,junk:false' /etc/malloc.conf".)
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20150307:
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The 32-bit PowerPC kernel has been changed to a position-independent
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executable. This can only be booted with a version of loader(8)
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newer than January 31, 2015, so make sure to update both world and
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kernel before rebooting.
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20150217:
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If you are running a -CURRENT kernel since r273872 (Oct 30th, 2014),
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but before r278950, the RNG was not seeded properly. Immediately
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@ -37,10 +37,9 @@ INCLUDES+= -I$S/contrib/libfdt
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CFLAGS+= -msoft-float -Wa,-many
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.if ${MACHINE_ARCH} == "powerpc64"
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# Build position-independent kernel
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CFLAGS+= -fPIC
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LDFLAGS+= -pie
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.endif
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.if !empty(DDB_ENABLED)
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CFLAGS+= -fno-omit-frame-pointer
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@ -411,7 +411,7 @@ link_elf_init(void* arg)
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ef = (elf_file_t) linker_kernel_file;
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ef->preloaded = 1;
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#ifdef __powerpc64__
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#ifdef __powerpc__
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ef->address = (caddr_t) (__startkernel - KERNBASE);
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#else
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ef->address = 0;
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@ -108,36 +108,47 @@ kernel_text:
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.text
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.globl __start
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__start:
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li 8,0
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li 9,0x100
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mtctr 9
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1:
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dcbf 0,8
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icbi 0,8
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addi 8,8,0x20
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bdnz 1b
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sync
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isync
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/* Figure out where we are */
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bl 1f
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.long _DYNAMIC-.
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.long _GLOBAL_OFFSET_TABLE_-.
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.long tmpstk-.
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1: mflr %r30
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/* Zero bss, in case we were started by something unhelpful */
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li 0,0
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lis 8,_edata@ha
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addi 8,8,_edata@l
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lis 9,_end@ha
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addi 9,9,_end@l
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2: stw 0,0(8)
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addi 8,8,4
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cmplw 8,9
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blt 2b
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/* Set up temporary stack pointer */
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lwz %r1,8(%r30)
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add %r1,%r1,%r30
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addi %r1,%r1,(8+TMPSTKSZ-32)
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/* Relocate self */
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stw %r3,16(%r1)
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stw %r4,20(%r1)
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stw %r5,24(%r1)
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stw %r6,28(%r1)
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lwz %r3,0(%r30) /* _DYNAMIC in %r3 */
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add %r3,%r3,%r30
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lwz %r4,4(%r30) /* GOT pointer */
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add %r4,%r4,%r30
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lwz %r4,4(%r4) /* got[0] is _DYNAMIC link addr */
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subf %r4,%r4,%r3 /* subtract to calculate relocbase */
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bl elf_reloc_self
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lis 1,(tmpstk+TMPSTKSZ-16)@ha
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addi 1,1,(tmpstk+TMPSTKSZ-16)@l
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lwz %r3,16(%r1)
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lwz %r4,20(%r1)
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lwz %r5,24(%r1)
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lwz %r6,28(%r1)
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/* MD setup */
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bl powerpc_init
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/* Set stack pointer to new value and branch to mi_startup */
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mr %r1, %r3
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li %r3, 0
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stw %r3, 0(%r1)
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bl mi_startup
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/* If mi_startup somehow returns, exit. This would be bad. */
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b OF_exit
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/*
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@ -235,10 +235,13 @@ extern void *testppc64, *testppc64size;
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extern void *restorebridge, *restorebridgesize;
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extern void *rfid_patch, *rfi_patch1, *rfi_patch2;
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extern void *trapcode64;
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extern Elf_Addr _GLOBAL_OFFSET_TABLE_[];
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#endif
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extern void *rstcode, *rstcodeend;
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extern void *trapcode, *trapcodeend, *trapcode2;
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extern void *trapcode, *trapcodeend;
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extern void *generictrap, *generictrap64;
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extern void *slbtrap, *slbtrapend;
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extern void *alitrap, *aliend;
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extern void *dsitrap, *dsiend;
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@ -254,7 +257,6 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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{
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struct pcpu *pc;
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vm_offset_t startkernel, endkernel;
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void *generictrap;
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size_t trap_offset, trapsize;
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vm_offset_t trap;
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void *kmdp;
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@ -467,20 +469,9 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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/* rfi_patch2 is at the end of dbleave */
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bcopy(&rfid_patch,&rfi_patch2,4);
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#endif
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/*
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* Set the common trap entry point to the one that
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* knows to restore 32-bit operation on execution.
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*/
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generictrap = &trapcode64;
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} else {
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generictrap = &trapcode;
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}
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#else /* powerpc64 */
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cpu_features |= PPC_FEATURE_64;
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generictrap = &trapcode;
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#endif
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trapsize = (size_t)&trapcodeend - (size_t)&trapcode;
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@ -490,7 +481,7 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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* different ones in a minute.
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*/
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for (trap = EXC_RST; trap < EXC_LAST; trap += 0x20)
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bcopy(generictrap, (void *)trap, trapsize);
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bcopy(&trapcode, (void *)trap, trapsize);
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#ifndef __powerpc64__
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if (cpu_features & PPC_FEATURE_64) {
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@ -530,12 +521,19 @@ powerpc_init(vm_offset_t fdt, vm_offset_t toc, vm_offset_t ofentry, void *mdp)
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#ifdef __powerpc64__
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/* Set TOC base so that the interrupt code can get at it */
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*((void **)TRAP_GENTRAP) = &trapcode2;
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*((void **)TRAP_GENTRAP) = &generictrap;
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*((register_t *)TRAP_TOCBASE) = toc;
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bcopy(&slbtrap, (void *)EXC_DSE,(size_t)&slbtrapend - (size_t)&slbtrap);
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bcopy(&slbtrap, (void *)EXC_ISE,(size_t)&slbtrapend - (size_t)&slbtrap);
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#else
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/* Set branch address for trap code */
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if (cpu_features & PPC_FEATURE_64)
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*((void **)TRAP_GENTRAP) = &generictrap64;
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else
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*((void **)TRAP_GENTRAP) = &generictrap;
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*((void **)TRAP_TOCBASE) = _GLOBAL_OFFSET_TABLE_;
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/* G2-specific TLB miss helper handlers */
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bcopy(&imisstrap, (void *)EXC_IMISS, (size_t)&imisssize);
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bcopy(&dlmisstrap, (void *)EXC_DLMISS, (size_t)&dlmisssize);
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@ -74,8 +74,9 @@
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* Kernel SRs are loaded directly from kernel_pmap_
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*/
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#define RESTORE_KERN_SRS(pmap,sr) \
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lis pmap,CNAME(kernel_pmap_store)@ha; \
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lwzu sr,CNAME(kernel_pmap_store)+PM_SR@l(pmap); \
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lwz pmap,TRAP_TOCBASE(0); \
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lwz pmap,CNAME(kernel_pmap_store)@got(pmap); \
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lwzu sr,PM_SR(pmap); \
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RESTORE_SRS(pmap,sr)
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/*
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@ -301,7 +302,12 @@ CNAME(restorebridgesize) = .-CNAME(restorebridge)
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*/
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.globl CNAME(rstcode), CNAME(rstcodeend)
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CNAME(rstcode):
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ba cpu_reset
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bl 1f
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.long cpu_reset
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1: mflr %r31
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lwz %r31,0(%r31)
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mtlr %r31
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blrl
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CNAME(rstcodeend):
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cpu_reset:
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@ -313,12 +319,12 @@ cpu_reset:
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mflr %r1
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addi %r1,%r1,(124-16)@l
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bla CNAME(cpudep_ap_early_bootstrap)
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bl CNAME(cpudep_ap_early_bootstrap)
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lis %r3,1@l
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bla CNAME(pmap_cpu_bootstrap)
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bla CNAME(cpudep_ap_bootstrap)
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bl CNAME(pmap_cpu_bootstrap)
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bl CNAME(cpudep_ap_bootstrap)
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mr %r1,%r3
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bla CNAME(cpudep_ap_setup)
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bl CNAME(cpudep_ap_setup)
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GET_CPUINFO(%r5)
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lwz %r3,(PC_RESTORE)(%r5)
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cmplwi %cr0,%r3,0
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@ -327,7 +333,7 @@ cpu_reset:
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b CNAME(longjmp)
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2:
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#ifdef SMP
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bla CNAME(machdep_ap_bootstrap)
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bl CNAME(machdep_ap_bootstrap)
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#endif
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/* Should not be reached */
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@ -344,21 +350,12 @@ CNAME(trapcode):
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mtsprg1 %r1 /* save SP */
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mflr %r1 /* Save the old LR in r1 */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1, 0x20 /* How to get the vector from LR */
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bla generictrap /* LR & SPRG3 is exception # */
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lwz %r1, TRAP_GENTRAP(0) /* Get branch address */
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mtlr %r1
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li %r1, 0xe0 /* How to get the vector from LR */
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blrl /* LR & (0xff00 | r1) is exception # */
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CNAME(trapcodeend):
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/*
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* 64-bit version of trapcode. Identical, except it calls generictrap64.
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*/
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.globl CNAME(trapcode64)
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CNAME(trapcode64):
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mtsprg1 %r1 /* save SP */
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mflr %r1 /* Save the old LR in r1 */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1, 0x20 /* How to get the vector from LR */
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bla generictrap64 /* LR & SPRG3 is exception # */
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/*
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* For ALI: has to save DSISR and DAR
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*/
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@ -385,7 +382,14 @@ CNAME(alitrap):
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/* Test whether we already had PR set */
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mfsrr1 %r31
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mtcr %r31
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bla s_trap
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/* Jump to s_trap */
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bl 1f
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.long s_trap
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1: mflr %r31
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lwz %r31,0(%r31)
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mtlr %r31
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blrl
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CNAME(aliend):
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/*
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@ -449,7 +453,7 @@ isi1:
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xoris %r0, %r0, 0x2 /* flip the msr<tgpr> bit */
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mtcrf 0x80, %r3 /* restore CR0 */
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mtmsr %r0 /* flip back to the native gprs */
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ba EXC_ISI /* go to instr. access interrupt */
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ba EXC_ISI /* go to instr. access interrupt */
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CNAME(imisssize) = .-CNAME(imisstrap)
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@ -613,13 +617,15 @@ CNAME(dsitrap):
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rlwinm %r31,%r31,7,25,28 /* get segment * 8 */
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/* get batu */
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addis %r31,%r31,CNAME(battable)@ha
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lwz %r30,CNAME(battable)@l(31)
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lwz %r30,TRAP_TOCBASE(0)
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lwz %r30,CNAME(battable)@got(%r30)
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add %r31,%r30,%r31
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lwz %r30,0(%r31)
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mtcr %r30
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bf 30,1f /* branch if supervisor valid is
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false */
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/* get batl */
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lwz %r31,CNAME(battable)+4@l(31)
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lwz %r31,4(%r31)
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/* We randomly use the highest two bat registers here */
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mftb %r28
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andi. %r28,%r28,1
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@ -644,7 +650,14 @@ CNAME(dsitrap):
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rfi /* return to trapped code */
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1:
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mflr %r28 /* save LR (SP already saved) */
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bla disitrap
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/* Jump to disitrap */
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bl 4f
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.long disitrap
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4: mflr %r1
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lwz %r1,0(%r1)
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mtlr %r1
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blrl
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CNAME(dsiend):
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/*
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@ -711,7 +724,7 @@ realtrap:
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GET_CPUINFO(%r1)
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lwz %r1,PC_CURPCB(%r1)
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RESTORE_KERN_SRS(%r30,%r31) /* enable kernel mapping */
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ba s_trap
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b s_trap
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/*
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* generictrap does some standard setup for trap handling to minimize
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@ -723,6 +736,7 @@ realtrap:
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* SPRG2 - Original LR
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*/
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.globl CNAME(generictrap64)
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generictrap64:
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mtsprg3 %r31
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mfmsr %r31
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@ -731,6 +745,7 @@ generictrap64:
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mfsprg3 %r31
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isync
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.globl CNAME(generictrap)
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generictrap:
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/* Save R1 for computing the exception vector */
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mtsprg3 %r1
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@ -848,8 +863,9 @@ dbtrap:
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andi. %r1,%r1,0xff00
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mtsprg3 %r1
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lis %r1,(tmpstk+TMPSTKSZ-16)@ha /* get new SP */
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addi %r1,%r1,(tmpstk+TMPSTKSZ-16)@l
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lwz %r1,TRAP_TOCBASE(0) /* get new SP */
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lwz %r1,tmpstk@got(%r1)
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addi %r1,%r1,TMPSTKSZ-16
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FRAME_SETUP(PC_DBSAVE)
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/* Call C trap code: */
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@ -896,9 +912,11 @@ CNAME(dblow):
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mfsprg2 %r29 /* ... and r29 */
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mflr %r1 /* save LR */
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mtsprg2 %r1 /* And then in SPRG2 */
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li %r1, 0 /* How to get the vector from LR */
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|
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bla generictrap /* and we look like a generic trap */
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lwz %r1, TRAP_GENTRAP(0) /* Get branch address */
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mtlr %r1
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li %r1, 0 /* How to get the vector from LR */
|
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blrl /* LR & (0xff00 | r1) is exception # */
|
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1:
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/* Privileged, so drop to KDB */
|
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GET_CPUINFO(%r1)
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@ -908,6 +926,13 @@ CNAME(dblow):
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stw %r30,(PC_DBSAVE+CPUSAVE_R30)(%r1) /* free r30 */
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stw %r31,(PC_DBSAVE+CPUSAVE_R31)(%r1) /* free r31 */
|
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mflr %r28 /* save LR */
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bla dbtrap
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/* Jump to dbtrap */
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bl 2f
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.long dbtrap
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2: mflr %r1
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lwz %r1,0(%r1)
|
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mtlr %r1
|
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blrl
|
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CNAME(dbend):
|
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#endif /* KDB */
|
||||
|
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@ -673,8 +673,7 @@ realtrap:
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* SPRG2 - Original LR
|
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*/
|
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|
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.globl CNAME(trapcode2)
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trapcode2:
|
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.globl CNAME(generictrap)
|
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generictrap:
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/* Save R1 for computing the exception vector */
|
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mtsprg3 %r1
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|
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@ -205,10 +205,28 @@ done_mapping:
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/*
|
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* Setup a temporary stack
|
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*/
|
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lis %r1, tmpstack@ha
|
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addi %r1, %r1, tmpstack@l
|
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bl 1f
|
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.long tmpstack-.
|
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1: mflr %r1
|
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lwz %r2,0(%r1)
|
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add %r1,%r1,%r2
|
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addi %r1, %r1, (TMPSTACKSZ - 16)
|
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|
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/*
|
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* Relocate kernel
|
||||
*/
|
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bl 1f
|
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.long _DYNAMIC-.
|
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.long _GLOBAL_OFFSET_TABLE_-.
|
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1: mflr %r5
|
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lwz %r3,0(%r5) /* _DYNAMIC in %r3 */
|
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add %r3,%r3,%r5
|
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lwz %r4,4(%r5) /* GOT pointer */
|
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add %r4,%r4,%r5
|
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lwz %r4,4(%r4) /* got[0] is _DYNAMIC link addr */
|
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subf %r4,%r4,%r3 /* subtract to calculate relocbase */
|
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bl elf_reloc_self
|
||||
|
||||
/*
|
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* Initialise exception vector offsets
|
||||
*/
|
||||
@ -338,10 +356,13 @@ bp_tlb1_end:
|
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blt 4b
|
||||
|
||||
/* Switch to the final mapping */
|
||||
lis %r5, __boot_page@ha
|
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ori %r5, %r5, __boot_page@l
|
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bl 5f
|
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5: mflr %r3
|
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.long __boot_page-.
|
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5: mflr %r5
|
||||
lwz %r3,0(%r3)
|
||||
add %r5,%r5,%r3 /* __boot_page in r5 */
|
||||
bl 6f
|
||||
6: mflr %r3
|
||||
rlwinm %r3, %r3, 0, 0xfff /* Offset from boot page start */
|
||||
add %r3, %r3, %r5 /* Make this virtual address */
|
||||
addi %r3, %r3, 32
|
||||
@ -365,8 +386,11 @@ bp_tlb1_end:
|
||||
/*
|
||||
* Setup a temporary stack
|
||||
*/
|
||||
lis %r1, tmpstack@ha
|
||||
addi %r1, %r1, tmpstack@l
|
||||
bl 1f
|
||||
.long tmpstack-.
|
||||
1: mflr %r1
|
||||
lwz %r2,0(%r1)
|
||||
add %r1,%r1,%r2
|
||||
addi %r1, %r1, (TMPSTACKSZ - 16)
|
||||
|
||||
/*
|
||||
@ -377,8 +401,11 @@ bp_tlb1_end:
|
||||
/*
|
||||
* Assign our pcpu instance
|
||||
*/
|
||||
lis %r3, ap_pcpu@h
|
||||
ori %r3, %r3, ap_pcpu@l
|
||||
bl 1f
|
||||
.long ap_pcpu-.
|
||||
1: mflr %r4
|
||||
lwz %r3, 0(%r4)
|
||||
add %r3, %r3, %r4
|
||||
lwz %r3, 0(%r3)
|
||||
mtsprg0 %r3
|
||||
|
||||
@ -543,24 +570,14 @@ __boot_page_padding:
|
||||
* dedicated for cases when invalidation(s) should NOT be propagated to other
|
||||
* CPUs.
|
||||
*
|
||||
* Global vars tlb0_ways, tlb0_entries_per_way are assumed to have been set up
|
||||
* correctly (by tlb0_get_tlbconf()).
|
||||
* void tid_flush(tlbtid_t tid, int tlb0_ways, int tlb0_entries_per_way);
|
||||
*
|
||||
* XXX: why isn't this in C?
|
||||
*/
|
||||
ENTRY(tid_flush)
|
||||
cmpwi %r3, TID_KERNEL
|
||||
beq tid_flush_end /* don't evict kernel translations */
|
||||
|
||||
/* Number of TLB0 ways */
|
||||
lis %r4, tlb0_ways@h
|
||||
ori %r4, %r4, tlb0_ways@l
|
||||
lwz %r4, 0(%r4)
|
||||
|
||||
/* Number of entries / way */
|
||||
lis %r5, tlb0_entries_per_way@h
|
||||
ori %r5, %r5, tlb0_entries_per_way@l
|
||||
lwz %r5, 0(%r5)
|
||||
|
||||
/* Disable interrupts */
|
||||
mfmsr %r10
|
||||
wrteei 0
|
||||
@ -718,6 +735,11 @@ setfault:
|
||||
/* Data section */
|
||||
/************************************************************************/
|
||||
.data
|
||||
.align 3
|
||||
GLOBAL(__startkernel)
|
||||
.long begin
|
||||
GLOBAL(__endkernel)
|
||||
.long end
|
||||
.align 4
|
||||
tmpstack:
|
||||
.space TMPSTACKSZ
|
||||
|
||||
@ -159,7 +159,7 @@ unsigned int kernel_ptbls; /* Number of KVA ptbls. */
|
||||
#define PMAP_REMOVE_DONE(pmap) \
|
||||
((pmap) != kernel_pmap && (pmap)->pm_stats.resident_count == 0)
|
||||
|
||||
extern void tid_flush(tlbtid_t);
|
||||
extern void tid_flush(tlbtid_t tid, int tlb0_ways, int tlb0_entries_per_way);
|
||||
extern int elf32_nxstack;
|
||||
|
||||
/**************************************************************************/
|
||||
@ -2818,7 +2818,7 @@ tid_alloc(pmap_t pmap)
|
||||
tidbusy[thiscpu][tid]->pm_tid[thiscpu] = TID_NONE;
|
||||
|
||||
/* Flush all entries from TLB0 matching this TID. */
|
||||
tid_flush(tid);
|
||||
tid_flush(tid, tlb0_ways, tlb0_entries_per_way);
|
||||
}
|
||||
|
||||
tidbusy[thiscpu][tid] = pmap;
|
||||
|
||||
@ -542,8 +542,11 @@ INTERRUPT(int_data_tlb_error)
|
||||
|
||||
search_kernel_pmap:
|
||||
/* Load r26 with kernel_pmap address */
|
||||
lis %r26, kernel_pmap_store@h
|
||||
ori %r26, %r26, kernel_pmap_store@l
|
||||
bl 1f
|
||||
.long kernel_pmap_store-.
|
||||
1: mflr %r21
|
||||
lwz %r26, 0(%r21)
|
||||
add %r26, %r21, %r26 /* kernel_pmap_store in r26 */
|
||||
|
||||
/* Force kernel tid, set TID to 0 in MAS1. */
|
||||
li %r21, 0
|
||||
@ -737,12 +740,17 @@ INTERRUPT(int_debug)
|
||||
FRAME_SETUP(SPR_SPRG2, PC_BOOKE_CRITSAVE, EXC_DEBUG)
|
||||
GET_CPUINFO(%r3)
|
||||
lwz %r3, (PC_BOOKE_CRITSAVE+CPUSAVE_SRR0)(%r3)
|
||||
lis %r4, interrupt_vector_base@ha
|
||||
addi %r4, %r4, interrupt_vector_base@l
|
||||
bl 0f
|
||||
.long interrupt_vector_base-.
|
||||
.long interrupt_vector_top-.
|
||||
0: mflr %r5
|
||||
lwz %r4,0(%r5) /* interrupt_vector_base in r4 */
|
||||
add %r4,%r4,%r5
|
||||
cmplw cr0, %r3, %r4
|
||||
blt 1f
|
||||
lis %r4, interrupt_vector_top@ha
|
||||
addi %r4, %r4, interrupt_vector_top@l
|
||||
lwz %r4,4(%r5) /* interrupt_vector_top in r4 */
|
||||
add %r4,%r4,%r5
|
||||
addi %r4,%r4,4
|
||||
cmplw cr0, %r3, %r4
|
||||
bge 1f
|
||||
/* Disable single-stepping for the interrupt handlers. */
|
||||
|
||||
@ -66,17 +66,21 @@ ASENTRY(ofwcall)
|
||||
/* Record the old MSR */
|
||||
mfmsr %r6
|
||||
|
||||
/* GOT pointer in r7 */
|
||||
bl _GLOBAL_OFFSET_TABLE_@local-4
|
||||
mflr %r7
|
||||
|
||||
/* read client interface handler */
|
||||
lis %r4,openfirmware_entry@ha
|
||||
lwz %r4,openfirmware_entry@l(%r4)
|
||||
lwz %r4,openfirmware_entry@got(%r7)
|
||||
lwz %r4,0(%r4)
|
||||
|
||||
/*
|
||||
* Set the MSR to the OF value. This has the side effect of disabling
|
||||
* exceptions, which prevents preemption later.
|
||||
*/
|
||||
|
||||
lis %r5,ofmsr@ha
|
||||
lwz %r5,ofmsr@l(%r5)
|
||||
lwz %r5,ofmsr@got(%r7)
|
||||
lwz %r5,0(%r5)
|
||||
mtmsr %r5
|
||||
isync
|
||||
|
||||
@ -87,8 +91,8 @@ ASENTRY(ofwcall)
|
||||
* later.
|
||||
*/
|
||||
mr %r5,%r1
|
||||
lis %r1,(ofwstk+OFWSTKSZ-32)@ha
|
||||
addi %r1,%r1,(ofwstk+OFWSTKSZ-32)@l
|
||||
lwz %r1,ofwstk@got(%r7)
|
||||
addi %r1,%r1,(OFWSTKSZ-32)
|
||||
stw %r5,20(%r1) /* Save real stack pointer */
|
||||
stw %r2,24(%r1) /* Save curthread */
|
||||
stw %r6,28(%r1) /* Save old MSR */
|
||||
@ -124,18 +128,22 @@ ASENTRY(rtascall)
|
||||
mflr %r0
|
||||
stw %r0,4(%r1)
|
||||
|
||||
/* GOT pointer in r7 */
|
||||
bl _GLOBAL_OFFSET_TABLE_@local-4
|
||||
mflr %r7
|
||||
|
||||
/* Record the old MSR to real-mode-accessible area */
|
||||
mfmsr %r0
|
||||
lis %r5,rtas_regsave@ha
|
||||
stw %r0,rtas_regsave@l(%r5)
|
||||
lwz %r5,rtas_regsave@got(%r7)
|
||||
stw %r0,0(%r5)
|
||||
|
||||
/* read client interface handler */
|
||||
lis %r5,rtas_entry@ha
|
||||
lwz %r5,rtas_entry@l(%r5)
|
||||
lwz %r5,rtas_entry@got(%r7)
|
||||
lwz %r5,0(%r5)
|
||||
|
||||
/* Set the MSR to the RTAS value */
|
||||
lis %r6,rtasmsr@ha
|
||||
lwz %r6,rtasmsr@l(%r6)
|
||||
lwz %r6,rtasmsr@got(%r7)
|
||||
lwz %r6,0(%r6)
|
||||
mtmsr %r6
|
||||
isync
|
||||
|
||||
@ -143,9 +151,13 @@ ASENTRY(rtascall)
|
||||
mtctr %r5
|
||||
bctrl
|
||||
|
||||
/* GOT pointer in r7 */
|
||||
bl _GLOBAL_OFFSET_TABLE_@local-4
|
||||
mflr %r7
|
||||
|
||||
/* Now set the MSR back */
|
||||
lis %r6,rtas_regsave@ha
|
||||
lwz %r6,rtas_regsave@l(%r6)
|
||||
lwz %r6,rtas_regsave@got(%r7)
|
||||
lwz %r6,0(%r6)
|
||||
mtmsr %r6
|
||||
isync
|
||||
|
||||
|
||||
@ -147,6 +147,8 @@ SYSINIT(oelf32, SI_SUB_EXEC, SI_ORDER_ANY,
|
||||
(sysinit_cfunc_t) elf32_insert_brand_entry,
|
||||
&freebsd_brand_oinfo);
|
||||
|
||||
void elf_reloc_self(Elf_Dyn *dynp, Elf_Addr relocbase);
|
||||
|
||||
void
|
||||
elf32_dump_thread(struct thread *td, void *dst, size_t *off)
|
||||
{
|
||||
@ -252,6 +254,39 @@ elf_reloc_internal(linker_file_t lf, Elf_Addr relocbase, const void *data,
|
||||
return(0);
|
||||
}
|
||||
|
||||
void
|
||||
elf_reloc_self(Elf_Dyn *dynp, Elf_Addr relocbase)
|
||||
{
|
||||
Elf_Rela *rela = 0, *relalim;
|
||||
Elf_Addr relasz = 0;
|
||||
Elf_Addr *where;
|
||||
|
||||
/*
|
||||
* Extract the rela/relasz values from the dynamic section
|
||||
*/
|
||||
for (; dynp->d_tag != DT_NULL; dynp++) {
|
||||
switch (dynp->d_tag) {
|
||||
case DT_RELA:
|
||||
rela = (Elf_Rela *)(relocbase+dynp->d_un.d_ptr);
|
||||
break;
|
||||
case DT_RELASZ:
|
||||
relasz = dynp->d_un.d_val;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Relocate these values
|
||||
*/
|
||||
relalim = (Elf_Rela *)((caddr_t)rela + relasz);
|
||||
for (; rela < relalim; rela++) {
|
||||
if (ELF_R_TYPE(rela->r_info) != R_PPC_RELATIVE)
|
||||
continue;
|
||||
where = (Elf_Addr *)(relocbase + rela->r_offset);
|
||||
*where = (Elf_Addr)(relocbase + rela->r_addend);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
elf_reloc(linker_file_t lf, Elf_Addr relocbase, const void *data, int type,
|
||||
elf_lookup_fn lookup)
|
||||
|
||||
@ -121,8 +121,9 @@ ENTRY(cpu_switch)
|
||||
cpu_switchin:
|
||||
#if defined(SMP) && defined(SCHED_ULE)
|
||||
/* Wait for the new thread to become unblocked */
|
||||
lis %r6,blocked_lock@ha
|
||||
addi %r6,%r6,blocked_lock@l
|
||||
bl _GLOBAL_OFFSET_TABLE_@local-4
|
||||
mflr %r6
|
||||
lwz %r6,blocked_lock@got(%r6)
|
||||
blocked_loop:
|
||||
lwz %r7,TD_LOCK(%r2)
|
||||
cmpw %r6,%r7
|
||||
|
||||
Loading…
Reference in New Issue
Block a user