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Remove the parts of cpu_functions from armv6 that are unused on that
architecture. Sponsored by: ABT Systems Ltd
This commit is contained in:
parent
d15a8db5ad
commit
610d93d80a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=306641
@ -242,28 +242,11 @@ struct cpu_functions sheeva_cpufuncs = {
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#ifdef CPU_MV_PJ4B
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struct cpu_functions pj4bv7_cpufuncs = {
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/* CPU functions */
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.cf_cpwait = armv7_drain_writebuf,
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/* MMU functions */
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.cf_control = cpufunc_control,
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.cf_setttb = armv7_setttb,
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/* TLB functions */
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.cf_tlb_flushID = armv7_tlb_flushID,
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.cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
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.cf_tlb_flushD = armv7_tlb_flushID,
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.cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
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/* Cache operations */
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.cf_icache_sync_range = armv7_icache_sync_range,
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.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
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.cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
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.cf_dcache_inv_range = armv7_dcache_inv_range,
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.cf_dcache_wb_range = armv7_dcache_wb_range,
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.cf_idcache_inv_all = armv7_idcache_inv_all,
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.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
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.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
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.cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
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.cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
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.cf_l2cache_inv_range = (void *)cpufunc_nullop,
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@ -275,7 +258,6 @@ struct cpu_functions pj4bv7_cpufuncs = {
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.cf_sleep = (void *)cpufunc_nullop,
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/* Soft functions */
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.cf_context_switch = armv7_context_switch,
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.cf_setup = pj4bv7_setup
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};
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#endif /* CPU_MV_PJ4B */
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@ -436,28 +418,11 @@ struct cpu_functions fa526_cpufuncs = {
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#if defined(CPU_ARM1176)
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struct cpu_functions arm1176_cpufuncs = {
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/* CPU functions */
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.cf_cpwait = cpufunc_nullop,
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/* MMU functions */
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.cf_control = cpufunc_control,
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.cf_setttb = arm11x6_setttb,
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/* TLB functions */
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.cf_tlb_flushID = arm11_tlb_flushID,
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.cf_tlb_flushID_SE = arm11_tlb_flushID_SE,
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.cf_tlb_flushD = arm11_tlb_flushD,
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.cf_tlb_flushD_SE = arm11_tlb_flushD_SE,
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/* Cache operations */
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.cf_icache_sync_range = arm11x6_icache_sync_range,
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.cf_dcache_wbinv_all = arm11x6_dcache_wbinv_all,
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.cf_dcache_wbinv_range = armv6_dcache_wbinv_range,
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.cf_dcache_inv_range = armv6_dcache_inv_range,
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.cf_dcache_wb_range = armv6_dcache_wb_range,
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.cf_idcache_inv_all = armv6_idcache_inv_all,
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.cf_idcache_wbinv_all = arm11x6_idcache_wbinv_all,
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.cf_idcache_wbinv_range = arm11x6_idcache_wbinv_range,
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.cf_l2cache_wbinv_all = (void *)cpufunc_nullop,
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.cf_l2cache_wbinv_range = (void *)cpufunc_nullop,
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.cf_l2cache_inv_range = (void *)cpufunc_nullop,
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@ -469,40 +434,17 @@ struct cpu_functions arm1176_cpufuncs = {
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.cf_sleep = arm11x6_sleep,
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/* Soft functions */
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.cf_context_switch = arm11_context_switch,
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.cf_setup = arm11x6_setup
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};
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#endif /*CPU_ARM1176 */
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#if defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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struct cpu_functions cortexa_cpufuncs = {
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/* CPU functions */
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.cf_cpwait = cpufunc_nullop,
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/* MMU functions */
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.cf_control = cpufunc_control,
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.cf_setttb = armv7_setttb,
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/*
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* TLB functions. ARMv7 does all TLB ops based on a unified TLB model
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* whether the hardware implements separate I+D or not, so we use the
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* same 'ID' functions for all 3 variations.
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*/
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.cf_tlb_flushID = armv7_tlb_flushID,
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.cf_tlb_flushID_SE = armv7_tlb_flushID_SE,
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.cf_tlb_flushD = armv7_tlb_flushID,
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.cf_tlb_flushD_SE = armv7_tlb_flushID_SE,
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/* Cache operations */
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.cf_icache_sync_range = armv7_icache_sync_range,
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.cf_dcache_wbinv_all = armv7_dcache_wbinv_all,
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.cf_dcache_wbinv_range = armv7_dcache_wbinv_range,
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.cf_dcache_inv_range = armv7_dcache_inv_range,
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.cf_dcache_wb_range = armv7_dcache_wb_range,
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.cf_idcache_inv_all = armv7_idcache_inv_all,
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.cf_idcache_wbinv_all = armv7_idcache_wbinv_all,
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.cf_idcache_wbinv_range = armv7_idcache_wbinv_range,
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/*
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* Note: For CPUs using the PL310 the L2 ops are filled in when the
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@ -519,7 +461,6 @@ struct cpu_functions cortexa_cpufuncs = {
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.cf_sleep = armv7_cpu_sleep,
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/* Soft functions */
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.cf_context_switch = armv7_context_switch,
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.cf_setup = cortexa_setup
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};
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#endif /* CPU_CORTEXA */
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@ -59,14 +59,16 @@ breakpoint(void)
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struct cpu_functions {
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/* CPU functions */
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#if __ARM_ARCH < 6
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void (*cf_cpwait) (void);
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#endif
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/* MMU functions */
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u_int (*cf_control) (u_int bic, u_int eor);
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void (*cf_setttb) (u_int ttb);
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#if __ARM_ARCH < 6
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/* TLB functions */
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void (*cf_tlb_flushID) (void);
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@ -139,6 +141,7 @@ struct cpu_functions {
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void (*cf_idcache_inv_all) (void);
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void (*cf_idcache_wbinv_all) (void);
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void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
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#endif
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void (*cf_l2cache_wbinv_all) (void);
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void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
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@ -151,9 +154,11 @@ struct cpu_functions {
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void (*cf_sleep) (int mode);
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#if __ARM_ARCH < 6
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/* Soft functions */
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void (*cf_context_switch) (void);
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#endif
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void (*cf_setup) (void);
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};
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