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https://git.FreeBSD.org/src.git
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Implement a rudimentary interrupt handling system which should be good
enough for clock interrupts in SKI.
This commit is contained in:
Doug Rabson
parent
d84feb93c4
commit
61e1efff8a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=67032
@ -94,7 +94,7 @@ configure(void *dummy)
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* Now we're ready to handle (pending) interrupts.
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* XXX this is slightly misplaced.
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*/
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spl0();
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enable_intr();
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cold = 0;
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}
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@ -180,7 +180,7 @@ cpu_initclocks()
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*/
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cycles_per_sec = 700000000;
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ia64_set_itm(ia64_get_itc() + (cycles_per_sec + hz/2) / hz);
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ia64_set_itv(240); /* highest priority class */
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freq = cycles_per_sec;
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last_time = ia64_get_itc();
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@ -52,7 +52,8 @@
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add r17=2f-1b,r17;; \
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mov b0=r17; \
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br.sptk.few exception_save; \
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2: alloc r14=ar.pfs,0,0,2,0; \
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2: (p3) ssm psr.i; \
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alloc r14=ar.pfs,0,0,2,0; \
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movl r15=exception_restore; \
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mov out0=_n_; \
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mov out1=sp;; \
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@ -511,7 +512,37 @@ ia64_vector_table:
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/* 0x3000: External Interrupt vector */
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TRAP(12)
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mov r16=b0 // save user's b0
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1: mov r17=ip;; // construct return address
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add r17=2f-1b,r17;; // for exception_save
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mov b0=r17
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br.sptk.few exception_save // 'call' exception_save
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2: alloc r14=ar.pfs,0,0,2,0 // make a frame for calling with
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mov out1=sp;;
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add sp=-16,sp;;
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3: mov out0=cr.ivr // find interrupt vector
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;;
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cmp.eq p6,p0=15,out0 // check for spurious vector number
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(p6) br.dpnt.few exception_restore // if spurious, we are done
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;;
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ssm psr.i // re-enable interrupts
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;; // now that we are in-progress
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srlz.d
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;;
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br.call.sptk.many rp=interrupt // call high-level handler
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rsm psr.i // disable interrupts
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;;
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srlz.d
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;;
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mov cr.eoi=r0 // and ack the interrupt
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;;
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srlz.d
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br.sptk.few 3b // loop for more
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.align 1024
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/* 0x3400: Reserved */
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@ -993,6 +1024,9 @@ ENTRY(exception_restore, 0)
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*
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* Return:
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* sp kernel stack pointer
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* p1 true if user mode
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* p2 true if kernel mode
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* p3 true if interrupts were enabled
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*/
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ENTRY(exception_save, 0)
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rsm psr.dt // turn off data translations
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@ -1005,6 +1039,7 @@ ENTRY(exception_save, 0)
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mov rIFA=cr.ifa
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mov rPR=pr
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;;
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tbit.nz p3,p0=rIPSR,14 // check for interrupt enable state
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extr.u r17=rIPSR,32,2 // extract ipsr.cpl
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;;
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cmp.eq p1,p2=r0,r17 // test for kernel mode
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@ -52,7 +52,8 @@
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add r17=2f-1b,r17;; \
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mov b0=r17; \
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br.sptk.few exception_save; \
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2: alloc r14=ar.pfs,0,0,2,0; \
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2: (p3) ssm psr.i; \
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alloc r14=ar.pfs,0,0,2,0; \
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movl r15=exception_restore; \
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mov out0=_n_; \
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mov out1=sp;; \
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@ -511,7 +512,37 @@ ia64_vector_table:
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/* 0x3000: External Interrupt vector */
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TRAP(12)
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mov r16=b0 // save user's b0
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1: mov r17=ip;; // construct return address
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add r17=2f-1b,r17;; // for exception_save
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mov b0=r17
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br.sptk.few exception_save // 'call' exception_save
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2: alloc r14=ar.pfs,0,0,2,0 // make a frame for calling with
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mov out1=sp;;
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add sp=-16,sp;;
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3: mov out0=cr.ivr // find interrupt vector
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;;
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cmp.eq p6,p0=15,out0 // check for spurious vector number
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(p6) br.dpnt.few exception_restore // if spurious, we are done
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;;
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ssm psr.i // re-enable interrupts
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;; // now that we are in-progress
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srlz.d
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;;
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br.call.sptk.many rp=interrupt // call high-level handler
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rsm psr.i // disable interrupts
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;;
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srlz.d
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;;
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mov cr.eoi=r0 // and ack the interrupt
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;;
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srlz.d
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br.sptk.few 3b // loop for more
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.align 1024
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/* 0x3400: Reserved */
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@ -993,6 +1024,9 @@ ENTRY(exception_restore, 0)
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*
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* Return:
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* sp kernel stack pointer
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* p1 true if user mode
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* p2 true if kernel mode
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* p3 true if interrupts were enabled
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*/
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ENTRY(exception_save, 0)
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rsm psr.dt // turn off data translations
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@ -1005,6 +1039,7 @@ ENTRY(exception_save, 0)
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mov rIFA=cr.ifa
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mov rPR=pr
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;;
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tbit.nz p3,p0=rIPSR,14 // check for interrupt enable state
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extr.u r17=rIPSR,32,2 // extract ipsr.cpl
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;;
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cmp.eq p1,p2=r0,r17 // test for kernel mode
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@ -76,41 +76,13 @@ void (*perf_irq)(unsigned long, struct trapframe *) = dummy_perf;
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static u_int schedclk2;
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void
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interrupt(a0, a1, a2, framep)
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unsigned long a0, a1, a2;
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struct trapframe *framep;
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interrupt(u_int64_t vector, struct trapframe *framep)
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{
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#if 0
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/*
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* Find our per-cpu globals.
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*/
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globalp = (struct globaldata *) alpha_pal_rdval();
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atomic_add_int(&PCPU_GET(intr_nesting_level), 1);
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{
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struct proc* p = curproc;
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if (!p) p = &proc0;
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if ((caddr_t) framep < (caddr_t) p->p_addr + 1024) {
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mtx_enter(&Giant, MTX_DEF);
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panic("possible stack overflow\n");
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}
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}
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framep->tf_regs[FRAME_TRAPARG_A0] = a0;
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framep->tf_regs[FRAME_TRAPARG_A1] = a1;
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framep->tf_regs[FRAME_TRAPARG_A2] = a2;
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switch (a0) {
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case ALPHA_INTR_XPROC: /* interprocessor interrupt */
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CTR0(KTR_INTR|KTR_SMP, "interprocessor interrupt");
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smp_handle_ipi(framep); /* note: lock not taken */
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break;
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case ALPHA_INTR_CLOCK: /* clock interrupt */
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switch (vector) {
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case 240: /* clock interrupt */
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CTR0(KTR_INTR, "clock interrupt");
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if (PCPU_GET(cpuno) != hwrpb->rpb_primary_cpu_id) {
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CTR0(KTR_INTR, "ignoring clock on secondary");
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return;
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}
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mtx_enter(&Giant, MTX_DEF);
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cnt.v_intr++;
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@ -119,53 +91,20 @@ interrupt(a0, a1, a2, framep)
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#else
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intrcnt[INTRCNT_CLOCK]++;
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#endif
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if (platform.clockintr){
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(*platform.clockintr)(framep);
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/* divide hz (1024) by 8 to get stathz (128) */
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if((++schedclk2 & 0x7) == 0)
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statclock((struct clockframe *)framep);
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}
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hardclock((struct clockframe *)framep);
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setdelayed();
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/* divide hz (1024) by 8 to get stathz (128) */
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if((++schedclk2 & 0x7) == 0)
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statclock((struct clockframe *)framep);
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mtx_exit(&Giant, MTX_DEF);
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break;
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case ALPHA_INTR_ERROR: /* Machine Check or Correctable Error */
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mtx_enter(&Giant, MTX_DEF);
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a0 = alpha_pal_rdmces();
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if (platform.mcheck_handler)
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(*platform.mcheck_handler)(a0, framep, a1, a2);
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else
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machine_check(a0, framep, a1, a2);
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mtx_exit(&Giant, MTX_DEF);
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break;
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case ALPHA_INTR_DEVICE: /* I/O device interrupt */
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mtx_enter(&Giant, MTX_DEF);
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cnt.v_intr++;
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if (platform.iointr)
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(*platform.iointr)(framep, a1);
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mtx_exit(&Giant, MTX_DEF);
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break;
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case ALPHA_INTR_PERF: /* interprocessor interrupt */
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mtx_enter(&Giant, MTX_DEF);
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perf_irq(a1, framep);
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mtx_exit(&Giant, MTX_DEF);
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break;
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case ALPHA_INTR_PASSIVE:
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#if 0
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printf("passive release interrupt vec 0x%lx (ignoring)\n", a1);
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#endif
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break;
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default:
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mtx_enter(&Giant, MTX_DEF);
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panic("unexpected interrupt: type 0x%lx vec 0x%lx a2 0x%lx\n",
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a0, a1, a2);
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panic("unexpected interrupt: vec %ld\n", vector);
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/* NOTREACHED */
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}
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atomic_subtract_int(&PCPU_GET(intr_nesting_level), 1);
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#endif
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}
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@ -1033,7 +1033,7 @@ setregs(struct proc *p, u_long entry, u_long stack, u_long ps_strings)
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bzero(frame->tf_f, sizeof(frame->tf_f));
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frame->tf_cr_iip = entry;
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frame->tf_cr_ipsr = (IA64_PSR_IC
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/* | IA64_PSR_I XXX not yet */
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| IA64_PSR_I
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| IA64_PSR_IT
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| IA64_PSR_DT
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| IA64_PSR_RT
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@ -151,8 +151,7 @@ void ia64_fpstate_save __P((struct proc *p, int write));
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void ia64_fpstate_drop __P((struct proc *p));
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void ia64_fpstate_switch __P((struct proc *p));
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void init_prom_interface __P((struct rpb*));
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void interrupt
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__P((unsigned long, unsigned long, unsigned long, struct trapframe *));
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void interrupt __P((u_int64_t, struct trapframe *));
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void machine_check
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__P((unsigned long, struct trapframe *, unsigned long, unsigned long));
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u_int64_t hwrpb_checksum __P((void));
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@ -409,6 +409,15 @@ ia64_set_itm(u_int64_t v)
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__asm __volatile("mov cr.itm=%0" :: "r" (v));
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}
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/*
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* Write the value of ar.itv.
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*/
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static __inline void
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ia64_set_itv(u_int64_t v)
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{
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__asm __volatile("mov cr.itv=%0" :: "r" (v));
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}
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/*
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* Write a region register.
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*/
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