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x86 specialreg: add bit masks definitions for EFER features

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listed in AMD64 APM vol.2 rev. 3.42.

Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
This commit is contained in:
Konstantin Belousov 2024-10-24 02:21:11 +03:00
parent 5999b74e96
commit 6308db659f
1 changed files with 3 additions and 0 deletions
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3
sys/x86/include/specialreg.h
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@ -105,6 +105,9 @@
#define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */
#define EFER_TCE 0x000008000 /* Translation Cache Extension */
#define EFER_MCOMMIT 0x000020000 /* Enable MCOMMIT (AMD) */
#define EFER_INTWB 0x000040000 /* Interruptible WBINVD */
#define EFER_UAIE 0x000100000 /* Upper Address Ignore */
#define EFER_AIBRSE 0x000200000 /* Automatic IBRS */
/*
* Intel Extended Features registers