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A slightly-closer-to-working version that includes code appropriate
to regular Pentiums. Unfortunately, it doesn't work on mine, but I'm not sure if this is the fault of the driver.
This commit is contained in:
Garrett Wollman
parent
b3f735dcfd
commit
650e27cd25
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=14860
@ -26,7 +26,7 @@
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id$
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* $Id: perfmon.c,v 1.1 1996/03/26 19:57:53 wollman Exp $
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*/
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#include <sys/param.h>
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@ -43,6 +43,11 @@ static int perfmon_inuse;
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static int perfmon_cpuok;
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static int msr_ctl[NPMC];
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static int msr_pmc[NPMC];
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static unsigned int ctl_shadow[NPMC];
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static quad_t pmc_shadow[NPMC]; /* used when ctr is stopped on P5 */
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static int (*writectl)(int);
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static int writectl5(int);
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static int writectl6(int);
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/*
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* Must be called after cpu_class is set up.
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@ -51,13 +56,21 @@ void
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perfmon_init(void)
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{
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switch(cpu_class) {
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case CPUCLASS_586: /* assume it's the same for now */
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case CPUCLASS_586:
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perfmon_cpuok = 1;
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msr_ctl[0] = 0x11;
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msr_ctl[1] = 0x11;
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msr_pmc[0] = 0x12;
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msr_pmc[1] = 0x13;
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writectl = writectl5;
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break;
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case CPUCLASS_686:
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perfmon_cpuok = 1;
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msr_ctl[0] = 0x186;
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msr_ctl[1] = 0x187;
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msr_pmc[0] = 0xc1;
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msr_pmc[1] = 0xc2;
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writectl = writectl6;
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break;
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default:
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@ -80,8 +93,11 @@ perfmon_setup(int pmc, unsigned int control)
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perfmon_inuse |= (1 << pmc);
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control &= ~(PMCF_SYS_FLAGS << 16);
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wrmsr(msr_ctl[pmc], control);
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wrmsr(msr_pmc[pmc], 0);
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disable_intr();
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ctl_shadow[pmc] = control;
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writectl(pmc);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
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enable_intr();
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return 0;
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}
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@ -92,7 +108,7 @@ perfmon_get(int pmc, unsigned int *control)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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*control = rdmsr(msr_ctl[pmc]);
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*control = ctl_shadow[pmc];
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return 0;
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}
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return EBUSY; /* XXX reversed sense */
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@ -106,6 +122,7 @@ perfmon_fini(int pmc)
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if (perfmon_inuse & (1 << pmc)) {
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perfmon_stop(pmc);
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ctl_shadow[pmc] = 0;
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perfmon_inuse &= ~(1 << pmc);
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return 0;
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}
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@ -115,48 +132,34 @@ perfmon_fini(int pmc)
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int
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perfmon_start(int pmc)
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{
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/*
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* XXX - Current Intel design does not allow counters to be enabled
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* independently.
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*/
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if (pmc != PMC_ALL)
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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#if 0
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if (perfmon_inuse & (1 << pmc)) {
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wrmsr(msr_ctl[pmc], rdmsr(msr_ctl[pmc]) | (PMCF_EN << 16));
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return 0;
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}
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#else
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if (perfmon_inuse) {
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wrmsr(msr_ctl[0], rdmsr(msr_ctl[0]) | (PMCF_EN << 16));
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disable_intr();
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ctl_shadow[pmc] |= (PMCF_EN << 16);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc]);
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writectl(pmc);
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enable_intr();
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return 0;
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}
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#endif
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return EBUSY;
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}
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int
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perfmon_stop(int pmc)
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{
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/*
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* XXX - Current Intel design does not allow counters to be enabled
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* independently.
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*/
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if (pmc != PMC_ALL)
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if (pmc < 0 || pmc >= NPMC)
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return EINVAL;
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#if 0
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if (perfmon_inuse & (1 << pmc)) {
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wrmsr(msr_ctl[pmc], rdmsr(msr_ctl[pmc]) & ~(PMCF_EN << 16));
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disable_intr();
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pmc_shadow[pmc] = rdmsr(msr_pmc[pmc]);
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ctl_shadow[pmc] &= ~(PMCF_EN << 16);
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writectl(pmc);
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enable_intr();
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return 0;
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}
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#else
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if (perfmon_inuse) {
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wrmsr(msr_ctl[0], rdmsr(msr_ctl[0]) & ~(PMCF_EN << 16));
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return 0;
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}
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#endif
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return EBUSY;
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}
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@ -167,7 +170,10 @@ perfmon_read(int pmc, quad_t *val)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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*val = rdmsr(msr_pmc[pmc]);
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if (ctl_shadow[pmc] & (PMCF_EN << 16))
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*val = rdmsr(msr_pmc[pmc]);
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else
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*val = pmc_shadow[pmc];
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return 0;
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}
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@ -181,12 +187,64 @@ perfmon_reset(int pmc)
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return EINVAL;
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if (perfmon_inuse & (1 << pmc)) {
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wrmsr(msr_pmc[pmc], 0);
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wrmsr(msr_pmc[pmc], pmc_shadow[pmc] = 0);
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return 0;
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}
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return EBUSY;
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}
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/*
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* Unfortunately, the performance-monitoring registers are laid out
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* differently in the P5 and P6. We keep everything in P6 format
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* internally (except for the event code), and convert to P5
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* format as needed on those CPUs. The writectl function pointer
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* is set up to point to one of these functions by perfmon_init().
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*/
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int
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writectl6(int pmc)
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{
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if (pmc > 0 && !(ctl_shadow[pmc] & (PMCF_EN << 16))) {
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wrmsr(msr_ctl[pmc], 0);
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} else {
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wrmsr(msr_ctl[pmc], ctl_shadow[pmc]);
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}
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return 0;
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}
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#define P5FLAG_P 0x200
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#define P5FLAG_E 0x100
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#define P5FLAG_USR 0x80
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#define P5FLAG_OS 0x40
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int
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writectl5(int pmc)
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{
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quad_t newval = 0;
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if (ctl_shadow[1] & (PMCF_EN << 16)) {
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if (ctl_shadow[1] & (PMCF_USR << 16))
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newval |= P5FLAG_USR << 16;
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if (ctl_shadow[1] & (PMCF_OS << 16))
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newval |= P5FLAG_OS << 16;
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if (ctl_shadow[1] & (PMCF_E << 16))
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newval |= P5FLAG_E << 16;
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newval |= (ctl_shadow[1] & 0x3f) << 16;
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}
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if (ctl_shadow[0] & (PMCF_EN << 16)) {
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if (ctl_shadow[1] & (PMCF_USR << 16))
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newval |= P5FLAG_USR;
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if (ctl_shadow[1] & (PMCF_OS << 16))
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newval |= P5FLAG_OS;
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if (ctl_shadow[1] & (PMCF_E << 16))
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newval |= P5FLAG_E;
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newval |= ctl_shadow[1] & 0x3f;
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}
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printf("about to wrmsr(%x, %x)\n", msr_ctl[0], (unsigned)newval);
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printf("old value is %x\n", (unsigned)rdmsr(msr_ctl[0]));
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wrmsr(msr_ctl[0], newval);
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return 0; /* XXX should check for errors */
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}
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/*
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* Now the user-mode interface, called from a subdevice of mem.c.
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*/
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