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Turn on the 0WS option for 16bit cards. Newer machines insert enough
delay that without this the performance is unacceptable. The 83C690, 83C790, and 83C795 chips which this affects are all designed to work with 0 waitstates in 16bit mode. Also cleaned up the toggling of 16bit access mode that occurs during normal operation; the previous code may not have done the right thing in all cases.
This commit is contained in:
David Greenman
parent
28b2e8ef73
commit
6514ad5540
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=29221
@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_ed.c,v 1.117 1997/07/20 14:09:57 bde Exp $
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* $Id: if_ed.c,v 1.118 1997/09/02 01:18:07 bde Exp $
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*/
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/*
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@ -717,25 +717,35 @@ ed_probe_WD80x3(isa_dev)
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sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
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/*
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* Set upper address bits and 8/16 bit access to shared memory
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* Set upper address bits, 8/16 bit access to shared memory, and
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* zero waitstate operation for 16 bit cards.
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*/
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if (isa16bit) {
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if (sc->is790) {
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sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
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outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
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/*
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* Enable zero waitstate operation
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*/
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outb(sc->asic_addr + ED_WD790_GCR, inb(sc->asic_addr +
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ED_WD790_GCR) | ED_WD790_GCR_ZWSEN);
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} else {
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
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ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
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((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
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sc->wd_laar_proto = ED_WD_LAAR_L16EN | ED_WD_LAAR_0WS16 |
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((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
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}
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/*
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* Enable 16bit access
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*/
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
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ED_WD_LAAR_M16EN);
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} else {
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if (((sc->type & ED_WD_SOFTCONFIG) ||
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#ifdef TOSH_ETHER
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(sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
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#endif
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(sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
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((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
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sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
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ED_WD_LAAR_ADDRHI;
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
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}
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}
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@ -788,8 +798,8 @@ ed_probe_WD80x3(isa_dev)
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
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~ED_WD_LAAR_M16EN);
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}
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return (0);
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}
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@ -807,8 +817,8 @@ ed_probe_WD80x3(isa_dev)
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
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~ED_WD_LAAR_M16EN);
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}
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return (ED_WD_IO_PORTS);
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}
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@ -2144,7 +2154,7 @@ ed_start(ifp)
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*/
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case ED_VENDOR_WD_SMC:{
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto | ED_WD_LAAR_M16EN));
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sc->wd_laar_proto | ED_WD_LAAR_M16EN);
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
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}
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@ -2171,7 +2181,8 @@ ed_start(ifp)
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
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outb(sc->asic_addr + ED_WD_LAAR,
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sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
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break;
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}
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}
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@ -2534,8 +2545,7 @@ edintr_sc(sc)
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(sc->vendor == ED_VENDOR_WD_SMC)) {
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto |=
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ED_WD_LAAR_M16EN));
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sc->wd_laar_proto | ED_WD_LAAR_M16EN);
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR,
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ED_WD_MSR_MENB);
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@ -2551,8 +2561,7 @@ edintr_sc(sc)
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
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}
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}
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}
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@ -24,7 +24,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: if_ed.c,v 1.117 1997/07/20 14:09:57 bde Exp $
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* $Id: if_ed.c,v 1.118 1997/09/02 01:18:07 bde Exp $
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*/
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/*
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@ -717,25 +717,35 @@ ed_probe_WD80x3(isa_dev)
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sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
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/*
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* Set upper address bits and 8/16 bit access to shared memory
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* Set upper address bits, 8/16 bit access to shared memory, and
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* zero waitstate operation for 16 bit cards.
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*/
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if (isa16bit) {
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if (sc->is790) {
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sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
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outb(sc->asic_addr + ED_WD_LAAR, ED_WD_LAAR_M16EN);
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/*
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* Enable zero waitstate operation
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*/
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outb(sc->asic_addr + ED_WD790_GCR, inb(sc->asic_addr +
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ED_WD790_GCR) | ED_WD790_GCR_ZWSEN);
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} else {
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
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ED_WD_LAAR_L16EN | ED_WD_LAAR_M16EN |
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((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
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sc->wd_laar_proto = ED_WD_LAAR_L16EN | ED_WD_LAAR_0WS16 |
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((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
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}
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/*
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* Enable 16bit access
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*/
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
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ED_WD_LAAR_M16EN);
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} else {
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if (((sc->type & ED_WD_SOFTCONFIG) ||
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#ifdef TOSH_ETHER
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(sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
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#endif
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(sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto =
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((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI)));
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sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
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ED_WD_LAAR_ADDRHI;
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
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}
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}
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@ -788,8 +798,8 @@ ed_probe_WD80x3(isa_dev)
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
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~ED_WD_LAAR_M16EN);
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}
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return (0);
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}
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@ -807,8 +817,8 @@ ed_probe_WD80x3(isa_dev)
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR, (sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
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~ED_WD_LAAR_M16EN);
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}
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return (ED_WD_IO_PORTS);
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}
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@ -2144,7 +2154,7 @@ ed_start(ifp)
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*/
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case ED_VENDOR_WD_SMC:{
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto | ED_WD_LAAR_M16EN));
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sc->wd_laar_proto | ED_WD_LAAR_M16EN);
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
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}
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@ -2171,7 +2181,8 @@ ed_start(ifp)
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
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outb(sc->asic_addr + ED_WD_LAAR,
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sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
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break;
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}
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}
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@ -2534,8 +2545,7 @@ edintr_sc(sc)
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(sc->vendor == ED_VENDOR_WD_SMC)) {
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto |=
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ED_WD_LAAR_M16EN));
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sc->wd_laar_proto | ED_WD_LAAR_M16EN);
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if (sc->is790) {
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outb(sc->asic_addr + ED_WD_MSR,
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ED_WD_MSR_MENB);
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@ -2551,8 +2561,7 @@ edintr_sc(sc)
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outb(sc->asic_addr + ED_WD_MSR, 0x00);
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}
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outb(sc->asic_addr + ED_WD_LAAR,
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(sc->wd_laar_proto &=
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~ED_WD_LAAR_M16EN));
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sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
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}
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}
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}
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