mirror of
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synced 2024-12-15 10:17:20 +00:00
Added two Cyrix 6x86/6x86MX options.
- CPU_CYRIX_NO_LOCK enables weak locking. If this option is not set and FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared. - CPU_WT_ALLOC enables write-through allocation.
This commit is contained in:
KATO Takenori
parent
6b2e066b6e
commit
6593be6011
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=30162
@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: initcpu.c,v 1.6 1997/06/27 13:46:19 kato Exp $
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* $Id: initcpu.c,v 1.7 1997/07/24 14:19:25 kato Exp $
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*/
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#include "opt_cpu.h"
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@ -304,6 +304,15 @@ init_6x86(void)
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/* Initialize CCR0. */
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
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/* Initialize CCR1. */
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#ifdef CPU_CYRIX_NO_LOCK
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
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#else
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#ifdef FAILSAFE
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
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#endif
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#endif
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/* Initialize CCR2. */
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#ifdef CPU_SUSP_HLT
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
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@ -324,6 +333,11 @@ init_6x86(void)
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write_cyrix_reg(CCR4, ccr4 | 7);
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#endif
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/* Initialize CCR5. */
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#ifdef CPU_WT_ALLOC
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write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
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#endif
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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@ -373,6 +387,15 @@ init_6x86MX(void)
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/* Initialize CCR0. */
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
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/* Initialize CCR1. */
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#ifdef CPU_CYRIX_NO_LOCK
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
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#else
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#ifdef FAILSAFE
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
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#endif
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#endif
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/* Initialize CCR2. */
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#ifdef CPU_SUSP_HLT
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
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@ -392,6 +415,11 @@ init_6x86MX(void)
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write_cyrix_reg(CCR4, ccr4 | 7);
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#endif
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/* Initialize CCR5. */
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#ifdef CPU_WT_ALLOC
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write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
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#endif
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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@ -506,10 +534,10 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
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ccr1 = read_cyrix_reg(CCR1);
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ccr2 = read_cyrix_reg(CCR2);
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ccr3 = read_cyrix_reg(CCR3);
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
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write_cyrix_reg(CCR3, CCR3_MAPEN0);
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ccr4 = read_cyrix_reg(CCR4);
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if (cpu == CPU_M1)
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if ((cpu == CPU_M1) || (cpu == CPU_M2))
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ccr5 = read_cyrix_reg(CCR5);
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else
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pcr0 = read_cyrix_reg(PCR0);
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@ -522,12 +550,12 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
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printf("CCR1=%x, CCR2=%x, CCR3=%x",
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(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
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printf(", CCR4=%x, ", (u_int)ccr4);
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if (cpu == CPU_M1)
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printf("CCR5=%x\n", ccr5);
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else
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if (cpu == CPU_M1SC)
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printf("PCR0=%x\n", pcr0);
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else
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printf("CCR5=%x\n", ccr5);
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}
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}
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printf("CR0=%x\n", cr0);
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $
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# $Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -132,6 +132,10 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
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# of Cyrix 6x86 and 6x86MX CPUs. If this option is not set and
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# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared. (NOTE 3)
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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@ -154,6 +158,8 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
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# enters suspend mode following execution of HALT instruction.
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#
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# CPU_WT_ALLOC enables write-through allocation.
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#
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# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
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# flush at hold state.
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#
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@ -169,6 +175,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# in write-through mode when revision < 2.7. If revision of Cyrix
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# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
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#
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# NOTE 3: This option may cause failures for software that requires
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# locked cycles in order to operate correctly.
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#
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options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
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options "CPU_BLUELIGHTNING_3X"
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options "CPU_BTB_EN"
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $
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# $Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -132,6 +132,10 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
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# of Cyrix 6x86 and 6x86MX CPUs. If this option is not set and
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# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared. (NOTE 3)
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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@ -154,6 +158,8 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
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# enters suspend mode following execution of HALT instruction.
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#
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# CPU_WT_ALLOC enables write-through allocation.
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#
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# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
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# flush at hold state.
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#
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@ -169,6 +175,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# in write-through mode when revision < 2.7. If revision of Cyrix
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# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
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#
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# NOTE 3: This option may cause failures for software that requires
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# locked cycles in order to operate correctly.
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#
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options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
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options "CPU_BLUELIGHTNING_3X"
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options "CPU_BTB_EN"
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@ -2,7 +2,7 @@
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# LINT -- config file for checking all the sources, tries to pull in
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# as much of the source tree as it can.
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#
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# $Id: LINT,v 1.369 1997/09/23 08:42:42 jkh Exp $
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# $Id: LINT,v 1.370 1997/09/23 16:28:00 jkh Exp $
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#
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# NB: You probably don't want to try running a kernel built from this
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# file. Instead, you should start from GENERIC, and add options from
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@ -132,6 +132,10 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# CPU_DIRECT_MAPPED_CACHE sets L1 cache of Cyrix 486DLC CPU in direct
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# mapped mode. Default is 2-way set associative mode.
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#
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# CPU_CYRIX_NO_LOCK enables weak locking for the entire address space
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# of Cyrix 6x86 and 6x86MX CPUs. If this option is not set and
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# FAILESAFE is defined, NO_LOCK bit of CCR1 is cleared. (NOTE 3)
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#
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# CPU_DISABLE_5X86_LSSER disables load store serialize (i.e. enables
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# reorder). This option should not be used if you use memory mapped
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# I/O device(s).
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@ -154,6 +158,8 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# CPU_SUSP_HLT enables suspend on HALT. If this option is set, CPU
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# enters suspend mode following execution of HALT instruction.
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#
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# CPU_WT_ALLOC enables write-through allocation.
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#
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# CYRIX_CACHE_WORKS enables CPU cache on Cyrix 486 CPUs with cache
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# flush at hold state.
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#
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@ -169,6 +175,9 @@ cpu "I686_CPU" # aka Pentium Pro(tm)
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# in write-through mode when revision < 2.7. If revision of Cyrix
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# 6x86 >= 2.7, CPU cache is always enabled in write-back mode.
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#
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# NOTE 3: This option may cause failures for software that requires
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# locked cycles in order to operate correctly.
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#
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options "CPU_BLUELIGHTNING_FPU_OP_CACHE"
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options "CPU_BLUELIGHTNING_3X"
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options "CPU_BTB_EN"
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@ -26,7 +26,7 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: initcpu.c,v 1.6 1997/06/27 13:46:19 kato Exp $
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* $Id: initcpu.c,v 1.7 1997/07/24 14:19:25 kato Exp $
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*/
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#include "opt_cpu.h"
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@ -304,6 +304,15 @@ init_6x86(void)
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/* Initialize CCR0. */
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
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/* Initialize CCR1. */
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#ifdef CPU_CYRIX_NO_LOCK
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
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#else
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#ifdef FAILSAFE
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
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#endif
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#endif
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/* Initialize CCR2. */
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#ifdef CPU_SUSP_HLT
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
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@ -324,6 +333,11 @@ init_6x86(void)
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write_cyrix_reg(CCR4, ccr4 | 7);
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#endif
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/* Initialize CCR5. */
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#ifdef CPU_WT_ALLOC
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write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
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#endif
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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@ -373,6 +387,15 @@ init_6x86MX(void)
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/* Initialize CCR0. */
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1);
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/* Initialize CCR1. */
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#ifdef CPU_CYRIX_NO_LOCK
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR1_NO_LOCK);
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#else
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#ifdef FAILSAFE
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write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) & ~CCR1_NO_LOCK);
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#endif
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#endif
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/* Initialize CCR2. */
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#ifdef CPU_SUSP_HLT
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write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT);
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@ -392,6 +415,11 @@ init_6x86MX(void)
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write_cyrix_reg(CCR4, ccr4 | 7);
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#endif
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/* Initialize CCR5. */
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#ifdef CPU_WT_ALLOC
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write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC);
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#endif
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/* Restore CCR3. */
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write_cyrix_reg(CCR3, ccr3);
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@ -506,10 +534,10 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
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ccr1 = read_cyrix_reg(CCR1);
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ccr2 = read_cyrix_reg(CCR2);
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ccr3 = read_cyrix_reg(CCR3);
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
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write_cyrix_reg(CCR3, CCR3_MAPEN0);
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ccr4 = read_cyrix_reg(CCR4);
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if (cpu == CPU_M1)
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if ((cpu == CPU_M1) || (cpu == CPU_M2))
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ccr5 = read_cyrix_reg(CCR5);
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else
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pcr0 = read_cyrix_reg(PCR0);
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@ -522,12 +550,12 @@ DB_SHOW_COMMAND(cyrixreg, cyrixreg)
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printf("CCR1=%x, CCR2=%x, CCR3=%x",
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(u_int)ccr1, (u_int)ccr2, (u_int)ccr3);
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1)) {
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if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) {
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printf(", CCR4=%x, ", (u_int)ccr4);
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if (cpu == CPU_M1)
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printf("CCR5=%x\n", ccr5);
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else
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if (cpu == CPU_M1SC)
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printf("PCR0=%x\n", pcr0);
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else
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printf("CCR5=%x\n", ccr5);
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}
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}
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printf("CR0=%x\n", cr0);
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