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la57: do not set global bit for PML5 entry

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The bit is reserved for PLM5, causing #PF on KVA access on real
hardware, unlike QEMU.

Sponsored by:	Advanced Micro Devices (AMD)
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
This commit is contained in:
Konstantin Belousov 2024-09-14 20:15:51 +03:00
parent 280e50461a
commit 678bc2281c
1 changed files with 1 additions and 1 deletions
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2
sys/amd64/amd64/pmap.c
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@ -2226,7 +2226,7 @@ pmap_bootstrap_la57(void *arg __unused)
* entering all existing kernel mappings into level 5 table.
*/
v_pml5[pmap_pml5e_index(UPT_MAX_ADDRESS)] = KPML4phys | X86_PG_V |
X86_PG_RW | X86_PG_A | X86_PG_M | pg_g;
X86_PG_RW | X86_PG_A | X86_PG_M;
/*
* Add pml5 entry for 1:1 trampoline mapping after LA57 is turned on.