mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-20 11:11:24 +00:00
Import ARM_INTRNG, the "next generation" interrupt architecture for arm
and armv6 architecures. The primary enhancement over the old design is support for hierarchical interrupt controllers (such as a gpio driver which can receive interrupts from a root PIC and act as a PIC itself for clients interested in handling a change of gpio pin state as an interrupt). The new code also provides an infrastructure for mapping interrupts described in metadata in the form of a "controller reference plus interrupt number" tuple into the simple "0-n" flat numeric space understood by rman and the bus resource mechanisms. Use of the new code is enabled by setting the ARM_INTRNG option, and by making a few simple changes to the platform's support code. In addition each existing PIC driver needs changes to be ready for INTRNG; this commit contains the changes for the arm/gic driver, which most armv6 SoCs use, but it does not enable the new code yet on any platform. This project has been many years in the making, starting as a GSoC project by Jakub Klama (jceel@) in 2012. That didn't get committed right away and the source base evolved out from under it to some degree. In 2014 I rebased the diffs to then -current and did some enhancements in the area of mapping interrupt numbers and storing associated fdt data, then the project went cold again for a while. Eventually Svata Kraus took that work in progress and did another big round of work on it, removing most of the remaining rough edges. Finally I took that and made one more pass through it, mostly disabling the "INTR_SOLO" feature for now, pending further design discussions on how to most efficiently dispatch a pending interrupt through more than one layer of PIC. The current code with the INTR_SOLO feature disabled uses approximate 100 extra cpu cycles for each cascaded PIC the interrupt has to be passed to, so what's left to do is about efficiency, not correct operation. Differential Revision: https://reviews.freebsd.org/D2047
This commit is contained in:
Ian Lepore
parent
d82754bbbc
commit
686450c898
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=289529
@ -34,18 +34,25 @@
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/ktr.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/pcpu.h>
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#include <sys/proc.h>
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#include <sys/cpuset.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#ifdef ARM_INTRNG
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#include <sys/sched.h>
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#endif
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/smp.h>
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@ -55,6 +62,10 @@ __FBSDID("$FreeBSD$");
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#ifdef ARM_INTRNG
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#include "pic_if.h"
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#endif
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/* We are using GICv2 register naming */
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/* Distributor Registers */
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@ -83,8 +94,8 @@ __FBSDID("$FreeBSD$");
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#define GICC_ABPR 0x001C /* v1 ICCABPR */
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#define GICC_IIDR 0x00FC /* v1 ICCIIDR*/
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#define GIC_FIRST_IPI 0 /* Irqs 0-15 are SGIs/IPIs. */
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#define GIC_LAST_IPI 15
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#define GIC_FIRST_SGI 0 /* Irqs 0-15 are SGIs/IPIs. */
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#define GIC_LAST_SGI 15
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#define GIC_FIRST_PPI 16 /* Irqs 16-31 are private (per */
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#define GIC_LAST_PPI 31 /* core) peripheral interrupts. */
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#define GIC_FIRST_SPI 32 /* Irqs 32+ are shared peripherals. */
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@ -102,8 +113,18 @@ __FBSDID("$FreeBSD$");
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#define GIC_DEFAULT_ICFGR_INIT 0x00000000
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#endif
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#ifdef ARM_INTRNG
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static u_int gic_irq_cpu;
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static int arm_gic_intr(void *);
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static int arm_gic_bind(device_t dev, struct arm_irqsrc *isrc);
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#endif
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struct arm_gic_softc {
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device_t gic_dev;
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#ifdef ARM_INTRNG
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void * gic_intrhand;
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struct arm_irqsrc ** gic_irqs;
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#endif
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struct resource * gic_res[3];
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bus_space_tag_t gic_c_bst;
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bus_space_tag_t gic_d_bst;
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@ -117,10 +138,13 @@ struct arm_gic_softc {
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static struct resource_spec arm_gic_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Distributor registers */
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{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* CPU Interrupt Intf. registers */
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#ifdef ARM_INTRNG
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_OPTIONAL }, /* Parent interrupt */
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#endif
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{ -1, 0 }
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};
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static struct arm_gic_softc *arm_gic_sc = NULL;
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static struct arm_gic_softc *gic_sc = NULL;
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#define gic_c_read_4(_sc, _reg) \
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bus_space_read_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg))
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@ -128,12 +152,16 @@ static struct arm_gic_softc *arm_gic_sc = NULL;
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bus_space_write_4((_sc)->gic_c_bst, (_sc)->gic_c_bsh, (_reg), (_val))
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#define gic_d_read_4(_sc, _reg) \
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bus_space_read_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg))
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#define gic_d_write_1(_sc, _reg, _val) \
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bus_space_write_1((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
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#define gic_d_write_4(_sc, _reg, _val) \
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bus_space_write_4((_sc)->gic_d_bst, (_sc)->gic_d_bsh, (_reg), (_val))
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#ifndef ARM_INTRNG
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static int gic_config_irq(int irq, enum intr_trigger trig,
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enum intr_polarity pol);
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static void gic_post_filter(void *);
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#endif
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static struct ofw_compat_data compat_data[] = {
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{"arm,gic", true}, /* Non-standard, used in FreeBSD dts. */
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@ -159,6 +187,72 @@ arm_gic_probe(device_t dev)
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return (BUS_PROBE_DEFAULT);
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}
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#ifdef ARM_INTRNG
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static inline void
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gic_irq_unmask(struct arm_gic_softc *sc, u_int irq)
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{
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gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F)));
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}
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static inline void
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gic_irq_mask(struct arm_gic_softc *sc, u_int irq)
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{
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gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F)));
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}
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#endif
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#ifdef SMP
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#ifdef ARM_INTRNG
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static void
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arm_gic_init_secondary(device_t dev)
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{
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struct arm_gic_softc *sc = device_get_softc(dev);
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struct arm_irqsrc *isrc;
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u_int irq;
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for (irq = 0; irq < sc->nirqs; irq += 4)
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gic_d_write_4(sc, GICD_IPRIORITYR(irq >> 2), 0);
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/* Set all the interrupts to be in Group 0 (secure) */
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for (irq = 0; irq < sc->nirqs; irq += 32) {
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gic_d_write_4(sc, GICD_IGROUPR(irq >> 5), 0);
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}
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/* Enable CPU interface */
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gic_c_write_4(sc, GICC_CTLR, 1);
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/* Set priority mask register. */
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gic_c_write_4(sc, GICC_PMR, 0xff);
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/* Enable interrupt distribution */
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gic_d_write_4(sc, GICD_CTLR, 0x01);
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/* Unmask attached SGI interrupts. */
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for (irq = GIC_FIRST_SGI; irq <= GIC_LAST_SGI; irq++) {
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isrc = sc->gic_irqs[irq];
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if (isrc != NULL && isrc->isrc_handlers != 0) {
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CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
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gic_irq_unmask(sc, irq);
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}
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}
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/* Unmask attached PPI interrupts. */
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for (irq = GIC_FIRST_PPI; irq <= GIC_LAST_PPI; irq++) {
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isrc = sc->gic_irqs[irq];
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if (isrc == NULL || isrc->isrc_handlers == 0)
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continue;
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if (isrc->isrc_flags & ARM_ISRCF_BOUND) {
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if (CPU_ISSET(PCPU_GET(cpuid), &isrc->isrc_cpu))
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gic_irq_unmask(sc, irq);
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} else {
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CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
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gic_irq_unmask(sc, irq);
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}
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}
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}
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#else
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static void
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arm_gic_init_secondary(device_t dev)
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{
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@ -189,7 +283,10 @@ arm_gic_init_secondary(device_t dev)
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gic_d_write_4(sc, GICD_ISENABLER(29 >> 5), (1UL << (29 & 0x1F)));
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gic_d_write_4(sc, GICD_ISENABLER(30 >> 5), (1UL << (30 & 0x1F)));
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}
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#endif /* ARM_INTRNG */
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#endif /* SMP */
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#ifndef ARM_INTRNG
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int
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gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
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int *trig, int *pol)
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@ -234,6 +331,19 @@ gic_decode_fdt(uint32_t iparent, uint32_t *intr, int *interrupt,
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}
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return (0);
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}
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#endif
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#ifdef ARM_INTRNG
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static inline intptr_t
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gic_xref(device_t dev)
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{
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#ifdef FDT
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return (OF_xref_from_node(ofw_bus_get_node(dev)));
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#else
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return (0);
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#endif
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}
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#endif
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static int
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arm_gic_attach(device_t dev)
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@ -241,8 +351,11 @@ arm_gic_attach(device_t dev)
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struct arm_gic_softc *sc;
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int i;
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uint32_t icciidr;
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#ifdef ARM_INTRNG
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intptr_t xref = gic_xref(dev);
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#endif
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if (arm_gic_sc)
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if (gic_sc)
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return (ENXIO);
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sc = device_get_softc(dev);
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@ -253,7 +366,7 @@ arm_gic_attach(device_t dev)
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}
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sc->gic_dev = dev;
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arm_gic_sc = sc;
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gic_sc = sc;
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/* Initialize mutex */
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mtx_init(&sc->mutex, "GIC lock", "", MTX_SPIN);
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@ -273,9 +386,14 @@ arm_gic_attach(device_t dev)
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sc->nirqs = gic_d_read_4(sc, GICD_TYPER);
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sc->nirqs = 32 * ((sc->nirqs & 0x1f) + 1);
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#ifdef ARM_INTRNG
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sc->gic_irqs = malloc(sc->nirqs * sizeof (*sc->gic_irqs), M_DEVBUF,
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M_WAITOK | M_ZERO);
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#else
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/* Set up function pointers */
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arm_post_filter = gic_post_filter;
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arm_config_irq = gic_config_irq;
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#endif
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icciidr = gic_c_read_4(sc, GICC_IIDR);
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device_printf(dev,"pn 0x%x, arch 0x%x, rev 0x%x, implementer 0x%x irqs %u\n",
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@ -311,10 +429,455 @@ arm_gic_attach(device_t dev)
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/* Enable interrupt distribution */
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gic_d_write_4(sc, GICD_CTLR, 0x01);
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#ifndef ARM_INTRNG
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return (0);
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#else
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/*
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* Now, when everything is initialized, it's right time to
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* register interrupt controller to interrupt framefork.
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*/
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if (arm_pic_register(dev, xref) != 0) {
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device_printf(dev, "could not register PIC\n");
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goto cleanup;
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}
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if (sc->gic_res[2] == NULL) {
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if (arm_pic_claim_root(dev, xref, arm_gic_intr, sc,
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GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) {
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device_printf(dev, "could not set PIC as a root\n");
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arm_pic_unregister(dev, xref);
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goto cleanup;
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}
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} else {
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if (bus_setup_intr(dev, sc->gic_res[2], INTR_TYPE_CLK,
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arm_gic_intr, NULL, sc, &sc->gic_intrhand)) {
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device_printf(dev, "could not setup irq handler\n");
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arm_pic_unregister(dev, xref);
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goto cleanup;
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}
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}
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return (0);
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cleanup:
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/*
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* XXX - not implemented arm_gic_detach() should be called !
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*/
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if (sc->gic_irqs != NULL)
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free(sc->gic_irqs, M_DEVBUF);
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bus_release_resources(dev, arm_gic_spec, sc->gic_res);
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return(ENXIO);
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#endif
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}
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#ifdef ARM_INTRNG
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static int
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arm_gic_intr(void *arg)
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{
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struct arm_gic_softc *sc = arg;
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struct arm_irqsrc *isrc;
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uint32_t irq_active_reg, irq;
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struct trapframe *tf;
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irq_active_reg = gic_c_read_4(sc, GICC_IAR);
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irq = irq_active_reg & 0x3FF;
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/*
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* 1. We do EOI here because recent read value from active interrupt
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* register must be used for it. Another approach is to save this
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* value into associated interrupt source.
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* 2. EOI must be done on same CPU where interrupt has fired. Thus
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* we must ensure that interrupted thread does not migrate to
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* another CPU.
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* 3. EOI cannot be delayed by any preemption which could happen on
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* critical_exit() used in MI intr code, when interrupt thread is
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* scheduled. See next point.
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* 4. IPI_RENDEZVOUS assumes that no preemption is permitted during
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* an action and any use of critical_exit() could break this
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* assumption. See comments within smp_rendezvous_action().
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* 5. We always return FILTER_HANDLED as this is an interrupt
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* controller dispatch function. Otherwise, in cascaded interrupt
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* case, the whole interrupt subtree would be masked.
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*/
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if (irq >= sc->nirqs) {
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device_printf(sc->gic_dev, "Spurious interrupt detected\n");
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gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
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return (FILTER_HANDLED);
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}
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tf = curthread->td_intr_frame;
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dispatch_irq:
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isrc = sc->gic_irqs[irq];
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if (isrc == NULL) {
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device_printf(sc->gic_dev, "Stray interrupt %u detected\n", irq);
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gic_irq_mask(sc, irq);
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gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
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goto next_irq;
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}
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/*
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* Note that GIC_FIRST_SGI is zero and is not used in 'if' statement
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* as compiler complains that comparing u_int >= 0 is always true.
|
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*/
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if (irq <= GIC_LAST_SGI) {
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#ifdef SMP
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/* Call EOI for all IPI before dispatch. */
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gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
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arm_ipi_dispatch(isrc, tf);
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goto next_irq;
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#else
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printf("SGI %u on UP system detected\n", irq - GIC_FIRST_SGI);
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gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
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goto next_irq;
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#endif
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}
|
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|
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if (isrc->isrc_trig == INTR_TRIGGER_EDGE)
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gic_c_write_4(sc, GICC_EOIR, irq_active_reg);
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|
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arm_irq_dispatch(isrc, tf);
|
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|
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next_irq:
|
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// arm_irq_memory_barrier(irq); /* XXX */
|
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// irq_active_reg = gic_c_read_4(sc, GICC_IAR);
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// irq = irq_active_reg & 0x3FF;
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if (0 && irq < sc->nirqs)
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goto dispatch_irq;
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|
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return (FILTER_HANDLED);
|
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}
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|
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static int
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gic_attach_isrc(struct arm_gic_softc *sc, struct arm_irqsrc *isrc, u_int irq)
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{
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const char *name;
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/*
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* 1. The link between ISRC and controller must be set atomically.
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* 2. Just do things only once in rare case when consumers
|
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* of shared interrupt came here at the same moment.
|
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*/
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mtx_lock_spin(&sc->mutex);
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if (sc->gic_irqs[irq] != NULL) {
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mtx_unlock_spin(&sc->mutex);
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return (sc->gic_irqs[irq] == isrc ? 0 : EEXIST);
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}
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sc->gic_irqs[irq] = isrc;
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isrc->isrc_data = irq;
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mtx_unlock_spin(&sc->mutex);
|
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|
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name = device_get_nameunit(sc->gic_dev);
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if (irq <= GIC_LAST_SGI)
|
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arm_irq_set_name(isrc, "%s,i%u", name, irq - GIC_FIRST_SGI);
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else if (irq <= GIC_LAST_PPI)
|
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arm_irq_set_name(isrc, "%s,p%u", name, irq - GIC_FIRST_PPI);
|
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else
|
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arm_irq_set_name(isrc, "%s,s%u", name, irq - GIC_FIRST_SPI);
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return (0);
|
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}
|
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|
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static int
|
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gic_detach_isrc(struct arm_gic_softc *sc, struct arm_irqsrc *isrc, u_int irq)
|
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{
|
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|
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mtx_lock_spin(&sc->mutex);
|
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if (sc->gic_irqs[irq] != isrc) {
|
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mtx_unlock_spin(&sc->mutex);
|
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return (sc->gic_irqs[irq] == NULL ? 0 : EINVAL);
|
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}
|
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sc->gic_irqs[irq] = NULL;
|
||||
isrc->isrc_data = 0;
|
||||
mtx_unlock_spin(&sc->mutex);
|
||||
|
||||
arm_irq_set_name(isrc, "");
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
gic_config(struct arm_gic_softc *sc, u_int irq, enum intr_trigger trig,
|
||||
enum intr_polarity pol)
|
||||
{
|
||||
uint32_t reg;
|
||||
uint32_t mask;
|
||||
|
||||
if (irq < GIC_FIRST_SPI)
|
||||
return;
|
||||
|
||||
mtx_lock_spin(&sc->mutex);
|
||||
|
||||
reg = gic_d_read_4(sc, GICD_ICFGR(irq >> 4));
|
||||
mask = (reg >> 2*(irq % 16)) & 0x3;
|
||||
|
||||
if (pol == INTR_POLARITY_LOW) {
|
||||
mask &= ~GICD_ICFGR_POL_MASK;
|
||||
mask |= GICD_ICFGR_POL_LOW;
|
||||
} else if (pol == INTR_POLARITY_HIGH) {
|
||||
mask &= ~GICD_ICFGR_POL_MASK;
|
||||
mask |= GICD_ICFGR_POL_HIGH;
|
||||
}
|
||||
|
||||
if (trig == INTR_TRIGGER_LEVEL) {
|
||||
mask &= ~GICD_ICFGR_TRIG_MASK;
|
||||
mask |= GICD_ICFGR_TRIG_LVL;
|
||||
} else if (trig == INTR_TRIGGER_EDGE) {
|
||||
mask &= ~GICD_ICFGR_TRIG_MASK;
|
||||
mask |= GICD_ICFGR_TRIG_EDGE;
|
||||
}
|
||||
|
||||
/* Set mask */
|
||||
reg = reg & ~(0x3 << 2*(irq % 16));
|
||||
reg = reg | (mask << 2*(irq % 16));
|
||||
gic_d_write_4(sc, GICD_ICFGR(irq >> 4), reg);
|
||||
|
||||
mtx_unlock_spin(&sc->mutex);
|
||||
}
|
||||
|
||||
static int
|
||||
gic_bind(struct arm_gic_softc *sc, u_int irq, cpuset_t *cpus)
|
||||
{
|
||||
uint32_t cpu, end, mask;
|
||||
|
||||
end = min(mp_ncpus, 8);
|
||||
for (cpu = end; cpu < MAXCPU; cpu++)
|
||||
if (CPU_ISSET(cpu, cpus))
|
||||
return (EINVAL);
|
||||
|
||||
for (mask = 0, cpu = 0; cpu < end; cpu++)
|
||||
if (CPU_ISSET(cpu, cpus))
|
||||
mask |= 1 << cpu;
|
||||
|
||||
gic_d_write_1(sc, GICD_ITARGETSR(0) + irq, mask);
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
gic_irq_from_nspc(struct arm_gic_softc *sc, u_int type, u_int num, u_int *irqp)
|
||||
{
|
||||
|
||||
switch (type) {
|
||||
case ARM_IRQ_NSPC_PLAIN:
|
||||
*irqp = num;
|
||||
return (*irqp < sc->nirqs ? 0 : EINVAL);
|
||||
|
||||
case ARM_IRQ_NSPC_IRQ:
|
||||
*irqp = num + GIC_FIRST_PPI;
|
||||
return (*irqp < sc->nirqs ? 0 : EINVAL);
|
||||
|
||||
case ARM_IRQ_NSPC_IPI:
|
||||
*irqp = num + GIC_FIRST_SGI;
|
||||
return (*irqp < GIC_LAST_SGI ? 0 : EINVAL);
|
||||
|
||||
default:
|
||||
return (EINVAL);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
gic_map_nspc(struct arm_gic_softc *sc, struct arm_irqsrc *isrc, u_int *irqp)
|
||||
{
|
||||
int error;
|
||||
|
||||
error = gic_irq_from_nspc(sc, isrc->isrc_nspc_type, isrc->isrc_nspc_num,
|
||||
irqp);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
return (gic_attach_isrc(sc, isrc, *irqp));
|
||||
}
|
||||
|
||||
#ifdef FDT
|
||||
static int
|
||||
gic_map_fdt(struct arm_gic_softc *sc, struct arm_irqsrc *isrc, u_int *irqp)
|
||||
{
|
||||
u_int irq, tripol;
|
||||
enum intr_trigger trig;
|
||||
enum intr_polarity pol;
|
||||
int error;
|
||||
|
||||
if (isrc->isrc_ncells == 1) {
|
||||
irq = isrc->isrc_cells[0];
|
||||
pol = INTR_POLARITY_CONFORM;
|
||||
trig = INTR_TRIGGER_CONFORM;
|
||||
} else if (isrc->isrc_ncells == 3) {
|
||||
if (isrc->isrc_cells[0] == 0)
|
||||
irq = isrc->isrc_cells[1] + GIC_FIRST_SPI;
|
||||
else
|
||||
irq = isrc->isrc_cells[1] + GIC_FIRST_PPI;
|
||||
|
||||
/*
|
||||
* In intr[2], bits[3:0] are trigger type and level flags.
|
||||
* 1 = low-to-high edge triggered
|
||||
* 2 = high-to-low edge triggered
|
||||
* 4 = active high level-sensitive
|
||||
* 8 = active low level-sensitive
|
||||
* The hardware only supports active-high-level or rising-edge.
|
||||
*/
|
||||
tripol = isrc->isrc_cells[2];
|
||||
if (tripol & 0x0a) {
|
||||
printf("unsupported trigger/polarity configuration "
|
||||
"0x%2x\n", tripol & 0x0f);
|
||||
return (ENOTSUP);
|
||||
}
|
||||
pol = INTR_POLARITY_CONFORM;
|
||||
if (tripol & 0x01)
|
||||
trig = INTR_TRIGGER_EDGE;
|
||||
else
|
||||
trig = INTR_TRIGGER_LEVEL;
|
||||
} else
|
||||
return (EINVAL);
|
||||
|
||||
if (irq >= sc->nirqs)
|
||||
return (EINVAL);
|
||||
|
||||
error = gic_attach_isrc(sc, isrc, irq);
|
||||
if (error != 0)
|
||||
return (error);
|
||||
|
||||
isrc->isrc_nspc_type = ARM_IRQ_NSPC_PLAIN;
|
||||
isrc->isrc_nspc_num = irq;
|
||||
isrc->isrc_trig = trig;
|
||||
isrc->isrc_pol = pol;
|
||||
|
||||
*irqp = irq;
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static int
|
||||
arm_gic_register(device_t dev, struct arm_irqsrc *isrc, boolean_t *is_percpu)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
u_int irq;
|
||||
int error;
|
||||
|
||||
if (isrc->isrc_type == ARM_ISRCT_NAMESPACE)
|
||||
error = gic_map_nspc(sc, isrc, &irq);
|
||||
#ifdef FDT
|
||||
else if (isrc->isrc_type == ARM_ISRCT_FDT)
|
||||
error = gic_map_fdt(sc, isrc, &irq);
|
||||
#endif
|
||||
else
|
||||
return (EINVAL);
|
||||
|
||||
if (error == 0)
|
||||
*is_percpu = irq < GIC_FIRST_SPI ? TRUE : FALSE;
|
||||
return (error);
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_enable_intr(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
u_int irq = isrc->isrc_data;
|
||||
|
||||
if (isrc->isrc_trig == INTR_TRIGGER_CONFORM)
|
||||
isrc->isrc_trig = INTR_TRIGGER_LEVEL;
|
||||
|
||||
/*
|
||||
* XXX - In case that per CPU interrupt is going to be enabled in time
|
||||
* when SMP is already started, we need some IPI call which
|
||||
* enables it on others CPUs. Further, it's more complicated as
|
||||
* pic_enable_source() and pic_disable_source() should act on
|
||||
* per CPU basis only. Thus, it should be solved here somehow.
|
||||
*/
|
||||
if (isrc->isrc_flags & ARM_ISRCF_PERCPU)
|
||||
CPU_SET(PCPU_GET(cpuid), &isrc->isrc_cpu);
|
||||
|
||||
gic_config(sc, irq, isrc->isrc_trig, isrc->isrc_pol);
|
||||
arm_gic_bind(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_enable_source(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
u_int irq = isrc->isrc_data;
|
||||
|
||||
arm_irq_memory_barrier(irq);
|
||||
gic_irq_unmask(sc, irq);
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_disable_source(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
u_int irq = isrc->isrc_data;
|
||||
|
||||
gic_irq_mask(sc, irq);
|
||||
}
|
||||
|
||||
static int
|
||||
arm_gic_unregister(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
u_int irq = isrc->isrc_data;
|
||||
|
||||
return (gic_detach_isrc(sc, isrc, irq));
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_pre_ithread(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
|
||||
arm_gic_disable_source(dev, isrc);
|
||||
gic_c_write_4(sc, GICC_EOIR, isrc->isrc_data);
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_post_ithread(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
|
||||
arm_irq_memory_barrier(0);
|
||||
arm_gic_enable_source(dev, isrc);
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_post_filter(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
|
||||
/* EOI for edge-triggered done earlier. */
|
||||
if (isrc->isrc_trig == INTR_TRIGGER_EDGE)
|
||||
return;
|
||||
|
||||
arm_irq_memory_barrier(0);
|
||||
gic_c_write_4(sc, GICC_EOIR, isrc->isrc_data);
|
||||
}
|
||||
|
||||
#ifdef SMP
|
||||
static int
|
||||
arm_gic_bind(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
uint32_t irq = isrc->isrc_data;
|
||||
|
||||
if (irq < GIC_FIRST_SPI)
|
||||
return (EINVAL);
|
||||
|
||||
if (CPU_EMPTY(&isrc->isrc_cpu)) {
|
||||
gic_irq_cpu = arm_irq_next_cpu(gic_irq_cpu, &all_cpus);
|
||||
CPU_SETOF(gic_irq_cpu, &isrc->isrc_cpu);
|
||||
}
|
||||
return (gic_bind(sc, irq, &isrc->isrc_cpu));
|
||||
}
|
||||
|
||||
static void
|
||||
arm_gic_ipi_send(device_t dev, struct arm_irqsrc *isrc, cpuset_t cpus)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
uint32_t irq, val = 0, i;
|
||||
|
||||
irq = isrc->isrc_data;
|
||||
|
||||
for (i = 0; i < MAXCPU; i++)
|
||||
if (CPU_ISSET(i, &cpus))
|
||||
val |= 1 << (16 + i);
|
||||
|
||||
gic_d_write_4(sc, GICD_SGIR(0), val | irq);
|
||||
}
|
||||
#endif
|
||||
#else
|
||||
static int
|
||||
arm_gic_next_irq(struct arm_gic_softc *sc, int last_irq)
|
||||
{
|
||||
@ -327,7 +890,7 @@ arm_gic_next_irq(struct arm_gic_softc *sc, int last_irq)
|
||||
* bits (ie CPU number), not just the IRQ number, and we do not
|
||||
* have this information later.
|
||||
*/
|
||||
if ((active_irq & 0x3ff) <= GIC_LAST_IPI)
|
||||
if ((active_irq & 0x3ff) <= GIC_LAST_SGI)
|
||||
gic_c_write_4(sc, GICC_EOIR, active_irq);
|
||||
active_irq &= 0x3FF;
|
||||
|
||||
@ -400,7 +963,7 @@ arm_gic_mask(device_t dev, int irq)
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
|
||||
gic_d_write_4(sc, GICD_ICENABLER(irq >> 5), (1UL << (irq & 0x1F)));
|
||||
gic_c_write_4(sc, GICC_EOIR, irq);
|
||||
gic_c_write_4(sc, GICC_EOIR, irq); /* XXX - not allowed */
|
||||
}
|
||||
|
||||
static void
|
||||
@ -408,7 +971,7 @@ arm_gic_unmask(device_t dev, int irq)
|
||||
{
|
||||
struct arm_gic_softc *sc = device_get_softc(dev);
|
||||
|
||||
if (irq > GIC_LAST_IPI)
|
||||
if (irq > GIC_LAST_SGI)
|
||||
arm_irq_memory_barrier(irq);
|
||||
|
||||
gic_d_write_4(sc, GICD_ISENABLER(irq >> 5), (1UL << (irq & 0x1F)));
|
||||
@ -455,10 +1018,10 @@ arm_gic_ipi_clear(device_t dev, int ipi)
|
||||
static void
|
||||
gic_post_filter(void *arg)
|
||||
{
|
||||
struct arm_gic_softc *sc = arm_gic_sc;
|
||||
struct arm_gic_softc *sc = gic_sc;
|
||||
uintptr_t irq = (uintptr_t) arg;
|
||||
|
||||
if (irq > GIC_LAST_IPI)
|
||||
if (irq > GIC_LAST_SGI)
|
||||
arm_irq_memory_barrier(irq);
|
||||
gic_c_write_4(sc, GICC_EOIR, irq);
|
||||
}
|
||||
@ -467,64 +1030,81 @@ static int
|
||||
gic_config_irq(int irq, enum intr_trigger trig, enum intr_polarity pol)
|
||||
{
|
||||
|
||||
return (arm_gic_config(arm_gic_sc->gic_dev, irq, trig, pol));
|
||||
return (arm_gic_config(gic_sc->gic_dev, irq, trig, pol));
|
||||
}
|
||||
|
||||
void
|
||||
arm_mask_irq(uintptr_t nb)
|
||||
{
|
||||
|
||||
arm_gic_mask(arm_gic_sc->gic_dev, nb);
|
||||
arm_gic_mask(gic_sc->gic_dev, nb);
|
||||
}
|
||||
|
||||
void
|
||||
arm_unmask_irq(uintptr_t nb)
|
||||
{
|
||||
|
||||
arm_gic_unmask(arm_gic_sc->gic_dev, nb);
|
||||
arm_gic_unmask(gic_sc->gic_dev, nb);
|
||||
}
|
||||
|
||||
int
|
||||
arm_get_next_irq(int last_irq)
|
||||
{
|
||||
|
||||
return (arm_gic_next_irq(arm_gic_sc, last_irq));
|
||||
}
|
||||
|
||||
void
|
||||
arm_pic_init_secondary(void)
|
||||
{
|
||||
|
||||
arm_gic_init_secondary(arm_gic_sc->gic_dev);
|
||||
return (arm_gic_next_irq(gic_sc, last_irq));
|
||||
}
|
||||
|
||||
#ifdef SMP
|
||||
void
|
||||
arm_pic_init_secondary(void)
|
||||
{
|
||||
|
||||
arm_gic_init_secondary(gic_sc->gic_dev);
|
||||
}
|
||||
|
||||
void
|
||||
pic_ipi_send(cpuset_t cpus, u_int ipi)
|
||||
{
|
||||
|
||||
arm_gic_ipi_send(arm_gic_sc->gic_dev, cpus, ipi);
|
||||
arm_gic_ipi_send(gic_sc->gic_dev, cpus, ipi);
|
||||
}
|
||||
|
||||
int
|
||||
pic_ipi_read(int i)
|
||||
{
|
||||
|
||||
return (arm_gic_ipi_read(arm_gic_sc->gic_dev, i));
|
||||
return (arm_gic_ipi_read(gic_sc->gic_dev, i));
|
||||
}
|
||||
|
||||
void
|
||||
pic_ipi_clear(int ipi)
|
||||
{
|
||||
|
||||
arm_gic_ipi_clear(arm_gic_sc->gic_dev, ipi);
|
||||
arm_gic_ipi_clear(gic_sc->gic_dev, ipi);
|
||||
}
|
||||
#endif
|
||||
#endif /* ARM_INTRNG */
|
||||
|
||||
static device_method_t arm_gic_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, arm_gic_probe),
|
||||
DEVMETHOD(device_attach, arm_gic_attach),
|
||||
#ifdef ARM_INTRNG
|
||||
/* Interrupt controller interface */
|
||||
DEVMETHOD(pic_disable_source, arm_gic_disable_source),
|
||||
DEVMETHOD(pic_enable_intr, arm_gic_enable_intr),
|
||||
DEVMETHOD(pic_enable_source, arm_gic_enable_source),
|
||||
DEVMETHOD(pic_post_filter, arm_gic_post_filter),
|
||||
DEVMETHOD(pic_post_ithread, arm_gic_post_ithread),
|
||||
DEVMETHOD(pic_pre_ithread, arm_gic_pre_ithread),
|
||||
DEVMETHOD(pic_register, arm_gic_register),
|
||||
DEVMETHOD(pic_unregister, arm_gic_unregister),
|
||||
#ifdef SMP
|
||||
DEVMETHOD(pic_bind, arm_gic_bind),
|
||||
DEVMETHOD(pic_init_secondary, arm_gic_init_secondary),
|
||||
DEVMETHOD(pic_ipi_send, arm_gic_ipi_send),
|
||||
#endif
|
||||
#endif
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
|
||||
1458
sys/arm/arm/intrng.c
Normal file
1458
sys/arm/arm/intrng.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -74,7 +74,9 @@ volatile int mp_naps;
|
||||
/* Set to 1 once we're ready to let the APs out of the pen. */
|
||||
volatile int aps_ready = 0;
|
||||
|
||||
#ifndef ARM_INTRNG
|
||||
static int ipi_handler(void *arg);
|
||||
#endif
|
||||
void set_stackptrs(int cpu);
|
||||
|
||||
/* Temporary variables for init_secondary() */
|
||||
@ -134,7 +136,6 @@ cpu_mp_start(void)
|
||||
else
|
||||
for (i = 1; i < mp_ncpus; i++)
|
||||
CPU_SET(i, &all_cpus);
|
||||
|
||||
}
|
||||
|
||||
/* Introduce rest of cores to the world */
|
||||
@ -150,7 +151,9 @@ init_secondary(int cpu)
|
||||
{
|
||||
struct pcpu *pc;
|
||||
uint32_t loop_counter;
|
||||
#ifndef ARM_INTRNG
|
||||
int start = 0, end = 0;
|
||||
#endif
|
||||
|
||||
#ifdef ARM_NEW_PMAP
|
||||
pmap_set_tex();
|
||||
@ -211,11 +214,12 @@ init_secondary(int cpu)
|
||||
|
||||
mtx_unlock_spin(&ap_boot_mtx);
|
||||
|
||||
#ifndef ARM_INTRNG
|
||||
/* Enable ipi */
|
||||
#ifdef IPI_IRQ_START
|
||||
start = IPI_IRQ_START;
|
||||
#ifdef IPI_IRQ_END
|
||||
end = IPI_IRQ_END;
|
||||
end = IPI_IRQ_END;
|
||||
#else
|
||||
end = IPI_IRQ_START;
|
||||
#endif
|
||||
@ -223,6 +227,7 @@ init_secondary(int cpu)
|
||||
|
||||
for (int i = start; i <= end; i++)
|
||||
arm_unmask_irq(i);
|
||||
#endif /* INTRNG */
|
||||
enable_interrupts(PSR_I);
|
||||
|
||||
loop_counter = 0;
|
||||
@ -245,6 +250,108 @@ init_secondary(int cpu)
|
||||
/* NOTREACHED */
|
||||
}
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
static void
|
||||
ipi_rendezvous(void *dummy __unused)
|
||||
{
|
||||
|
||||
CTR0(KTR_SMP, "IPI_RENDEZVOUS");
|
||||
smp_rendezvous_action();
|
||||
}
|
||||
|
||||
static void
|
||||
ipi_ast(void *dummy __unused)
|
||||
{
|
||||
|
||||
CTR0(KTR_SMP, "IPI_AST");
|
||||
}
|
||||
|
||||
static void
|
||||
ipi_stop(void *dummy __unused)
|
||||
{
|
||||
u_int cpu;
|
||||
|
||||
/*
|
||||
* IPI_STOP_HARD is mapped to IPI_STOP.
|
||||
*/
|
||||
CTR0(KTR_SMP, "IPI_STOP or IPI_STOP_HARD");
|
||||
|
||||
cpu = PCPU_GET(cpuid);
|
||||
savectx(&stoppcbs[cpu]);
|
||||
|
||||
/*
|
||||
* CPUs are stopped when entering the debugger and at
|
||||
* system shutdown, both events which can precede a
|
||||
* panic dump. For the dump to be correct, all caches
|
||||
* must be flushed and invalidated, but on ARM there's
|
||||
* no way to broadcast a wbinv_all to other cores.
|
||||
* Instead, we have each core do the local wbinv_all as
|
||||
* part of stopping the core. The core requesting the
|
||||
* stop will do the l2 cache flush after all other cores
|
||||
* have done their l1 flushes and stopped.
|
||||
*/
|
||||
cpu_idcache_wbinv_all();
|
||||
|
||||
/* Indicate we are stopped */
|
||||
CPU_SET_ATOMIC(cpu, &stopped_cpus);
|
||||
|
||||
/* Wait for restart */
|
||||
while (!CPU_ISSET(cpu, &started_cpus))
|
||||
cpu_spinwait();
|
||||
|
||||
CPU_CLR_ATOMIC(cpu, &started_cpus);
|
||||
CPU_CLR_ATOMIC(cpu, &stopped_cpus);
|
||||
CTR0(KTR_SMP, "IPI_STOP (restart)");
|
||||
}
|
||||
|
||||
static void
|
||||
ipi_preempt(void *arg)
|
||||
{
|
||||
struct trapframe *oldframe;
|
||||
struct thread *td;
|
||||
|
||||
critical_enter();
|
||||
td = curthread;
|
||||
td->td_intr_nesting_level++;
|
||||
oldframe = td->td_intr_frame;
|
||||
td->td_intr_frame = (struct trapframe *)arg;
|
||||
|
||||
CTR1(KTR_SMP, "%s: IPI_PREEMPT", __func__);
|
||||
sched_preempt(td);
|
||||
|
||||
td->td_intr_frame = oldframe;
|
||||
td->td_intr_nesting_level--;
|
||||
critical_exit();
|
||||
}
|
||||
|
||||
static void
|
||||
ipi_hardclock(void *arg)
|
||||
{
|
||||
struct trapframe *oldframe;
|
||||
struct thread *td;
|
||||
|
||||
critical_enter();
|
||||
td = curthread;
|
||||
td->td_intr_nesting_level++;
|
||||
oldframe = td->td_intr_frame;
|
||||
td->td_intr_frame = (struct trapframe *)arg;
|
||||
|
||||
CTR1(KTR_SMP, "%s: IPI_HARDCLOCK", __func__);
|
||||
hardclockintr();
|
||||
|
||||
td->td_intr_frame = oldframe;
|
||||
td->td_intr_nesting_level--;
|
||||
critical_exit();
|
||||
}
|
||||
|
||||
static void
|
||||
ipi_tlb(void *dummy __unused)
|
||||
{
|
||||
|
||||
CTR1(KTR_SMP, "%s: IPI_TLB", __func__);
|
||||
cpufuncs.cf_tlb_flushID();
|
||||
}
|
||||
#else
|
||||
static int
|
||||
ipi_handler(void *arg)
|
||||
{
|
||||
@ -320,15 +427,28 @@ ipi_handler(void *arg)
|
||||
|
||||
return (FILTER_HANDLED);
|
||||
}
|
||||
#endif
|
||||
|
||||
static void
|
||||
release_aps(void *dummy __unused)
|
||||
{
|
||||
uint32_t loop_counter;
|
||||
#ifndef ARM_INTRNG
|
||||
int start = 0, end = 0;
|
||||
#endif
|
||||
|
||||
if (mp_ncpus == 1)
|
||||
return;
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
arm_ipi_set_handler(IPI_RENDEZVOUS, "rendezvous", ipi_rendezvous, NULL, 0);
|
||||
arm_ipi_set_handler(IPI_AST, "ast", ipi_ast, NULL, 0);
|
||||
arm_ipi_set_handler(IPI_STOP, "stop", ipi_stop, NULL, 0);
|
||||
arm_ipi_set_handler(IPI_PREEMPT, "preempt", ipi_preempt, NULL, 0);
|
||||
arm_ipi_set_handler(IPI_HARDCLOCK, "hardclock", ipi_hardclock, NULL, 0);
|
||||
arm_ipi_set_handler(IPI_TLB, "tlb", ipi_tlb, NULL, 0);
|
||||
|
||||
#else
|
||||
#ifdef IPI_IRQ_START
|
||||
start = IPI_IRQ_START;
|
||||
#ifdef IPI_IRQ_END
|
||||
@ -353,6 +473,7 @@ release_aps(void *dummy __unused)
|
||||
/* Enable ipi */
|
||||
arm_unmask_irq(i);
|
||||
}
|
||||
#endif
|
||||
atomic_store_rel_int(&aps_ready, 1);
|
||||
/* Wake the other threads up */
|
||||
#if __ARM_ARCH >= 7
|
||||
|
||||
@ -85,8 +85,17 @@ static struct resource *nexus_alloc_resource(device_t, device_t, int, int *,
|
||||
u_long, u_long, u_long, u_int);
|
||||
static int nexus_activate_resource(device_t, device_t, int, int,
|
||||
struct resource *);
|
||||
#ifdef ARM_INTRNG
|
||||
#ifdef SMP
|
||||
static int nexus_bind_intr(device_t, device_t, struct resource *, int);
|
||||
#endif
|
||||
#endif
|
||||
static int nexus_config_intr(device_t dev, int irq, enum intr_trigger trig,
|
||||
enum intr_polarity pol);
|
||||
#ifdef ARM_INTRNG
|
||||
static int nexus_describe_intr(device_t dev, device_t child,
|
||||
struct resource *irq, void *cookie, const char *descr);
|
||||
#endif
|
||||
static int nexus_deactivate_resource(device_t, device_t, int, int,
|
||||
struct resource *);
|
||||
static int nexus_release_resource(device_t, device_t, int, int,
|
||||
@ -115,6 +124,12 @@ static device_method_t nexus_methods[] = {
|
||||
DEVMETHOD(bus_release_resource, nexus_release_resource),
|
||||
DEVMETHOD(bus_setup_intr, nexus_setup_intr),
|
||||
DEVMETHOD(bus_teardown_intr, nexus_teardown_intr),
|
||||
#ifdef ARM_INTRNG
|
||||
DEVMETHOD(bus_describe_intr, nexus_describe_intr),
|
||||
#ifdef SMP
|
||||
DEVMETHOD(bus_bind_intr, nexus_bind_intr),
|
||||
#endif
|
||||
#endif
|
||||
#ifdef FDT
|
||||
DEVMETHOD(ofw_bus_map_intr, nexus_ofw_map_intr),
|
||||
#endif
|
||||
@ -251,9 +266,12 @@ nexus_config_intr(device_t dev, int irq, enum intr_trigger trig,
|
||||
{
|
||||
int ret = ENODEV;
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
ret = arm_irq_config(irq, trig, pol);
|
||||
#else
|
||||
if (arm_config_irq)
|
||||
ret = (*arm_config_irq)(irq, trig, pol);
|
||||
|
||||
#endif
|
||||
return (ret);
|
||||
}
|
||||
|
||||
@ -267,9 +285,14 @@ nexus_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
|
||||
flags |= INTR_EXCL;
|
||||
|
||||
for (irq = rman_get_start(res); irq <= rman_get_end(res); irq++) {
|
||||
#ifdef ARM_INTRNG
|
||||
arm_irq_add_handler(child, filt, intr, arg, irq, flags,
|
||||
cookiep);
|
||||
#else
|
||||
arm_setup_irqhandler(device_get_nameunit(child),
|
||||
filt, intr, arg, irq, flags, cookiep);
|
||||
arm_unmask_irq(irq);
|
||||
#endif
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
@ -278,9 +301,31 @@ static int
|
||||
nexus_teardown_intr(device_t dev, device_t child, struct resource *r, void *ih)
|
||||
{
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
return (arm_irq_remove_handler(child, rman_get_start(r), ih));
|
||||
#else
|
||||
return (arm_remove_irqhandler(rman_get_start(r), ih));
|
||||
#endif
|
||||
}
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
static int
|
||||
nexus_describe_intr(device_t dev, device_t child, struct resource *irq,
|
||||
void *cookie, const char *descr)
|
||||
{
|
||||
|
||||
return (arm_irq_describe(rman_get_start(irq), cookie, descr));
|
||||
}
|
||||
|
||||
#ifdef SMP
|
||||
static int
|
||||
nexus_bind_intr(device_t dev, device_t child, struct resource *irq, int cpu)
|
||||
{
|
||||
|
||||
return (arm_irq_bind(rman_get_start(irq), cpu));
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
static int
|
||||
nexus_activate_resource(device_t bus, device_t child, int type, int rid,
|
||||
|
||||
124
sys/arm/arm/pic_if.m
Normal file
124
sys/arm/arm/pic_if.m
Normal file
@ -0,0 +1,124 @@
|
||||
#-
|
||||
# Copyright (c) 2012 Jakub Wojciech Klama <jceel@FreeBSD.org>
|
||||
# Copyright (c) 2015 Svatopluk Kraus
|
||||
# Copyright (c) 2015 Michal Meloun
|
||||
# All rights reserved.
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in the
|
||||
# documentation and/or other materials provided with the distribution.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
# SUCH DAMAGE.
|
||||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
#include <sys/bus.h>
|
||||
#include <sys/cpuset.h>
|
||||
#include <machine/frame.h>
|
||||
#include <machine/intr.h>
|
||||
|
||||
INTERFACE pic;
|
||||
|
||||
CODE {
|
||||
static int null_pic_bind(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
return (EOPNOTSUPP);
|
||||
}
|
||||
|
||||
static void null_pic_disable_intr(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void null_pic_enable_intr(device_t dev, struct arm_irqsrc *isrc)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void null_pic_init_secondary(device_t dev)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
static void null_pic_ipi_send(device_t dev, cpuset_t cpus, u_int ipi)
|
||||
{
|
||||
return;
|
||||
}
|
||||
};
|
||||
|
||||
METHOD int register {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
boolean_t *is_percpu;
|
||||
};
|
||||
|
||||
METHOD int unregister {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
};
|
||||
|
||||
METHOD void disable_intr {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
} DEFAULT null_pic_disable_intr;
|
||||
|
||||
METHOD void disable_source {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
};
|
||||
|
||||
METHOD void enable_source {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
};
|
||||
|
||||
METHOD void enable_intr {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
} DEFAULT null_pic_enable_intr;
|
||||
|
||||
METHOD void pre_ithread {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
};
|
||||
|
||||
METHOD void post_ithread {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
};
|
||||
|
||||
METHOD void post_filter {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
};
|
||||
|
||||
METHOD int bind {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
} DEFAULT null_pic_bind;
|
||||
|
||||
METHOD void init_secondary {
|
||||
device_t dev;
|
||||
} DEFAULT null_pic_init_secondary;
|
||||
|
||||
METHOD void ipi_send {
|
||||
device_t dev;
|
||||
struct arm_irqsrc *isrc;
|
||||
cpuset_t cpus;
|
||||
} DEFAULT null_pic_ipi_send;
|
||||
@ -34,12 +34,16 @@
|
||||
|
||||
#include <machine/bus.h>
|
||||
|
||||
#ifndef INTRNG
|
||||
|
||||
/* Max interrupt number */
|
||||
#define FDT_INTR_MAX NIRQ
|
||||
|
||||
/* Map phandle/intpin pair to global IRQ number */
|
||||
#define FDT_MAP_IRQ(node, pin) (pin)
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Bus space tag. XXX endianess info needs to be derived from the blob.
|
||||
*/
|
||||
|
||||
@ -43,6 +43,102 @@
|
||||
#include <dev/ofw/openfirm.h>
|
||||
#endif
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
|
||||
#ifndef NIRQ
|
||||
#define NIRQ 1024 /* XXX - It should be an option. */
|
||||
#endif
|
||||
|
||||
#ifdef notyet
|
||||
#define INTR_SOLO INTR_MD1
|
||||
typedef int arm_irq_filter_t(void *arg, struct trapframe *tf);
|
||||
#else
|
||||
typedef int arm_irq_filter_t(void *arg);
|
||||
#endif
|
||||
|
||||
#define ARM_ISRC_NAMELEN (MAXCOMLEN + 1)
|
||||
|
||||
typedef void arm_ipi_filter_t(void *arg);
|
||||
|
||||
enum arm_isrc_type {
|
||||
ARM_ISRCT_NAMESPACE,
|
||||
ARM_ISRCT_FDT
|
||||
};
|
||||
|
||||
#define ARM_ISRCF_REGISTERED 0x01 /* registered in a controller */
|
||||
#define ARM_ISRCF_PERCPU 0x02 /* per CPU interrupt */
|
||||
#define ARM_ISRCF_BOUND 0x04 /* bound to a CPU */
|
||||
|
||||
/* Interrupt source definition. */
|
||||
struct arm_irqsrc {
|
||||
device_t isrc_dev; /* where isrc is mapped */
|
||||
intptr_t isrc_xref; /* device reference key */
|
||||
uintptr_t isrc_data; /* device data for isrc */
|
||||
u_int isrc_irq; /* unique identificator */
|
||||
enum arm_isrc_type isrc_type; /* how is isrc decribed */
|
||||
u_int isrc_flags;
|
||||
char isrc_name[ARM_ISRC_NAMELEN];
|
||||
uint16_t isrc_nspc_type;
|
||||
uint16_t isrc_nspc_num;
|
||||
enum intr_trigger isrc_trig;
|
||||
enum intr_polarity isrc_pol;
|
||||
cpuset_t isrc_cpu; /* on which CPUs is enabled */
|
||||
u_int isrc_index;
|
||||
u_long * isrc_count;
|
||||
u_int isrc_handlers;
|
||||
struct intr_event * isrc_event;
|
||||
arm_irq_filter_t * isrc_filter;
|
||||
arm_ipi_filter_t * isrc_ipifilter;
|
||||
void * isrc_arg;
|
||||
#ifdef FDT
|
||||
u_int isrc_ncells;
|
||||
pcell_t isrc_cells[]; /* leave it last */
|
||||
#endif
|
||||
};
|
||||
|
||||
void arm_irq_set_name(struct arm_irqsrc *isrc, const char *fmt, ...)
|
||||
__printflike(2, 3);
|
||||
|
||||
void arm_irq_dispatch(struct arm_irqsrc *isrc, struct trapframe *tf);
|
||||
|
||||
#define ARM_IRQ_NSPC_NONE 0
|
||||
#define ARM_IRQ_NSPC_PLAIN 1
|
||||
#define ARM_IRQ_NSPC_IRQ 2
|
||||
#define ARM_IRQ_NSPC_IPI 3
|
||||
|
||||
u_int arm_namespace_map_irq(device_t dev, uint16_t type, uint16_t num);
|
||||
#ifdef FDT
|
||||
u_int arm_fdt_map_irq(phandle_t, pcell_t *, u_int);
|
||||
#endif
|
||||
|
||||
int arm_pic_register(device_t dev, intptr_t xref);
|
||||
int arm_pic_unregister(device_t dev, intptr_t xref);
|
||||
int arm_pic_claim_root(device_t dev, intptr_t xref, arm_irq_filter_t *filter,
|
||||
void *arg, u_int ipicount);
|
||||
|
||||
int arm_irq_add_handler(device_t dev, driver_filter_t, driver_intr_t, void *,
|
||||
u_int, int, void **);
|
||||
int arm_irq_remove_handler(device_t dev, u_int, void *);
|
||||
int arm_irq_config(u_int, enum intr_trigger, enum intr_polarity);
|
||||
int arm_irq_describe(u_int, void *, const char *);
|
||||
|
||||
u_int arm_irq_next_cpu(u_int current_cpu, cpuset_t *cpumask);
|
||||
|
||||
#ifdef SMP
|
||||
int arm_irq_bind(u_int, int);
|
||||
|
||||
void arm_ipi_dispatch(struct arm_irqsrc *isrc, struct trapframe *tf);
|
||||
|
||||
#define AISHF_NOALLOC 0x0001
|
||||
|
||||
int arm_ipi_set_handler(u_int ipi, const char *name, arm_ipi_filter_t *filter,
|
||||
void *arg, u_int flags);
|
||||
|
||||
void arm_pic_init_secondary(void);
|
||||
#endif
|
||||
|
||||
#else /* ARM_INTRNG */
|
||||
|
||||
/* XXX move to std.* files? */
|
||||
#ifdef CPU_XSCALE_81342
|
||||
#define NIRQ 128
|
||||
@ -71,7 +167,6 @@
|
||||
#define NIRQ 32
|
||||
#endif
|
||||
|
||||
|
||||
int arm_get_next_irq(int);
|
||||
void arm_mask_irq(uintptr_t);
|
||||
void arm_unmask_irq(uintptr_t);
|
||||
@ -83,8 +178,6 @@ extern void (*arm_post_filter)(void *);
|
||||
extern int (*arm_config_irq)(int irq, enum intr_trigger trig,
|
||||
enum intr_polarity pol);
|
||||
|
||||
void arm_irq_memory_barrier(uintptr_t);
|
||||
|
||||
void arm_pic_init_secondary(void);
|
||||
int gic_decode_fdt(uint32_t iparentnode, uint32_t *intrcells, int *interrupt,
|
||||
int *trig, int *pol);
|
||||
@ -93,4 +186,8 @@ int gic_decode_fdt(uint32_t iparentnode, uint32_t *intrcells, int *interrupt,
|
||||
int arm_fdt_map_irq(phandle_t, pcell_t *, int);
|
||||
#endif
|
||||
|
||||
#endif /* ARM_INTRNG */
|
||||
|
||||
void arm_irq_memory_barrier(uintptr_t);
|
||||
|
||||
#endif /* _MACHINE_INTR_H */
|
||||
|
||||
@ -6,6 +6,19 @@
|
||||
#include <sys/_cpuset.h>
|
||||
#include <machine/pcb.h>
|
||||
|
||||
#ifdef ARM_INTRNG
|
||||
enum {
|
||||
IPI_AST,
|
||||
IPI_PREEMPT,
|
||||
IPI_RENDEZVOUS,
|
||||
IPI_STOP,
|
||||
IPI_STOP_HARD = IPI_STOP, /* These are synonyms on arm. */
|
||||
IPI_HARDCLOCK,
|
||||
IPI_TLB,
|
||||
IPI_CACHE,
|
||||
ARM_IPI_COUNT
|
||||
};
|
||||
#else
|
||||
#define IPI_AST 0
|
||||
#define IPI_PREEMPT 2
|
||||
#define IPI_RENDEZVOUS 3
|
||||
@ -14,6 +27,7 @@
|
||||
#define IPI_HARDCLOCK 6
|
||||
#define IPI_TLB 7
|
||||
#define IPI_CACHE 8
|
||||
#endif /* INTRNG */
|
||||
|
||||
void init_secondary(int cpu);
|
||||
void mpentry(void);
|
||||
@ -24,8 +38,10 @@ void ipi_selected(cpuset_t cpus, u_int ipi);
|
||||
|
||||
/* PIC interface */
|
||||
void pic_ipi_send(cpuset_t cpus, u_int ipi);
|
||||
#ifndef ARM_INTRNG
|
||||
void pic_ipi_clear(int ipi);
|
||||
int pic_ipi_read(int arg);
|
||||
#endif
|
||||
|
||||
/* Platform interface */
|
||||
void platform_mp_setmaxid(void);
|
||||
|
||||
@ -41,7 +41,8 @@ arm/arm/gic.c optional gic
|
||||
arm/arm/identcpu.c standard
|
||||
arm/arm/in_cksum.c optional inet | inet6
|
||||
arm/arm/in_cksum_arm.S optional inet | inet6
|
||||
arm/arm/intr.c standard
|
||||
arm/arm/intr.c optional !arm_intrng
|
||||
arm/arm/intrng.c optional arm_intrng
|
||||
arm/arm/locore.S standard no-obj
|
||||
arm/arm/machdep.c standard
|
||||
arm/arm/mem.c optional mem
|
||||
@ -49,6 +50,7 @@ arm/arm/minidump_machdep.c optional mem
|
||||
arm/arm/mp_machdep.c optional smp
|
||||
arm/arm/nexus.c standard
|
||||
arm/arm/physmem.c standard
|
||||
arm/arm/pic_if.m optional arm_intrng
|
||||
arm/arm/pl190.c optional pl190
|
||||
arm/arm/pl310.c optional pl310
|
||||
arm/arm/platform.c optional platform
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#$FreeBSD$
|
||||
ARMV6 opt_global.h
|
||||
ARM_CACHE_LOCK_ENABLE opt_global.h
|
||||
ARM_INTRNG opt_global.h
|
||||
ARM_KERN_DIRECTMAP opt_vm.h
|
||||
ARM_L2_PIPT opt_global.h
|
||||
ARM_MANY_BOARD opt_global.h
|
||||
|
||||
Loading…
Reference in New Issue
Block a user