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Remove the arm FIQ support

Browse Source 
It isn't used, and only masks/unmasks FIQs on the local CPU so will be
broken on SMP.

Reviewed by:	mmel
Differential Revision:	https://reviews.freebsd.org/D33804
This commit is contained in:
Andrew Turner 2024-06-10 15:58:47 +01:00
parent 86bafddd61
commit 6abad5b606
12 changed files with 9 additions and 374 deletions
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2
sys/arm/arm/autoconf.c
View File

@ -90,7 +90,7 @@ static void
configure_final(void *dummy)
{
enable_interrupts(PSR_I | PSR_F);
enable_interrupts(PSR_I);
cninit_finish();
cold = 0;
}

37
sys/arm/arm/exception.S
View File

@ -165,12 +165,12 @@ _C_LABEL(dtrace_invop_jump_addr):
#define DO_AST \
ldr r0, [sp]; /* Get the SPSR from stack */ \
mrs r4, cpsr; /* save CPSR */ \
orr r1, r4, #(PSR_I|PSR_F); \
orr r1, r4, #(PSR_I); \
msr cpsr_c, r1; /* Disable interrupts */ \
and r0, r0, #(PSR_MODE); /* Returning to USR mode? */ \
teq r0, #(PSR_USR32_MODE); \
bne 2f; /* Nope, get out now */ \
bic r4, r4, #(PSR_I|PSR_F); \
bic r4, r4, #(PSR_I); \
1: GET_CURTHREAD_PTR(r5); \
ldr r1, [r5, #(TD_AST)]; \
teq r1, #0; \
@ -178,7 +178,7 @@ _C_LABEL(dtrace_invop_jump_addr):
msr cpsr_c, r4; /* Restore interrupts */ \
mov r0, sp; \
bl _C_LABEL(ast); /* ast(frame) */ \
orr r0, r4, #(PSR_I|PSR_F); \
orr r0, r4, #(PSR_I); \
msr cpsr_c, r0; \
b 1b; \
2:
@ -315,21 +315,6 @@ ASENTRY_NP(irq_entry)
b _C_LABEL(intr_irq_handler)/* trapframe to the handler. */
END(irq_entry)
/*
* Entry point for an FIQ interrupt.
*
* We don't currently support FIQ handlers very much. Something can
* install itself in the FIQ vector using code (that may or may not work
* these days) in fiq.c. If nobody does that and an FIQ happens, this
* default handler just disables FIQs and otherwise ignores it.
*/
ASENTRY_NP(fiq_entry)
mrs r8, cpsr /* FIQ handling isn't supported, */
bic r8, #(PSR_F) /* just disable FIQ and return. */
msr cpsr_c, r8 /* The r8 we trash here is the */
subs pc, lr, #4 /* banked FIQ-mode r8. */
END(fiq_entry)
/*
* Entry point for an Address Exception exception.
* This is an arm26 exception that should never happen.
@ -378,8 +363,6 @@ _C_LABEL(page0):
ldr pc, .Ldata_abort_entry
ldr pc, .Laddr_exception_entry
ldr pc, .Lirq_entry
.fiqv: ldr pc, .Lfiq_entry
.space 256 /* room for some fiq handler code */
_C_LABEL(page0_data):
.Lreset_entry: .word reset_entry
@ -389,18 +372,4 @@ _C_LABEL(page0_data):
.Ldata_abort_entry: .word data_abort_entry
.Laddr_exception_entry: .word addr_exception_entry
.Lirq_entry: .word irq_entry
.Lfiq_entry: .word fiq_entry
/*
* These items are used by the code in fiq.c to install what it calls the
* "null" handler. It's actually our default vector entry that just jumps
* to the default handler which just disables FIQs and returns.
*/
.global _C_LABEL(fiq_nullhandler_code), _C_LABEL(fiq_nullhandler_size)
_C_LABEL(fiq_nullhandler_code):
.word .fiqv
_C_LABEL(fiq_nullhandler_size):
.word 4

163
sys/arm/arm/fiq.c
View File

@ -1,163 +0,0 @@
/* $NetBSD: fiq.c,v 1.5 2002/04/03 23:33:27 thorpej Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2001, 2002 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <machine/armreg.h>
#include <machine/cpufunc.h>
#include <machine/fiq.h>
#include <vm/vm.h>
#include <machine/pcb.h>
#include <vm/pmap.h>
#include <machine/cpu.h>
TAILQ_HEAD(, fiqhandler) fiqhandler_stack =
TAILQ_HEAD_INITIALIZER(fiqhandler_stack);
extern char *fiq_nullhandler_code;
extern uint32_t fiq_nullhandler_size;
/*
* fiq_installhandler:
*
* Actually install the FIQ handler down at the FIQ vector.
*
* The FIQ vector is fixed by the hardware definition as the
* seventh 32-bit word in the vector page.
*
* Note: If the FIQ is invoked via an extra layer of
* indirection, the actual FIQ code store lives in the
* data segment, so there is no need to manipulate
* the vector page's protection.
*/
static void
fiq_installhandler(void *func, size_t size)
{
const uint32_t fiqvector = 7 * sizeof(uint32_t);
memcpy((void *)(vector_page + fiqvector), func, size);
icache_sync((vm_offset_t) fiqvector, size);
}
/*
* fiq_claim:
*
* Claim the FIQ vector.
*/
int
fiq_claim(struct fiqhandler *fh)
{
struct fiqhandler *ofh;
u_int oldirqstate;
int error = 0;
if (fh->fh_size > 0x100)
return (EFBIG);
oldirqstate = disable_interrupts(PSR_F);
if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) {
if ((ofh->fh_flags & FH_CANPUSH) == 0) {
error = EBUSY;
goto out;
}
/* Save the previous FIQ handler's registers. */
if (ofh->fh_regs != NULL)
fiq_getregs(ofh->fh_regs);
}
/* Set FIQ mode registers to ours. */
if (fh->fh_regs != NULL)
fiq_setregs(fh->fh_regs);
TAILQ_INSERT_HEAD(&fiqhandler_stack, fh, fh_list);
/* Now copy the actual handler into place. */
fiq_installhandler(fh->fh_func, fh->fh_size);
/* Make sure FIQs are enabled when we return. */
oldirqstate &= ~PSR_F;
out:
restore_interrupts(oldirqstate);
return (error);
}
/*
* fiq_release:
*
* Release the FIQ vector.
*/
void
fiq_release(struct fiqhandler *fh)
{
u_int oldirqstate;
struct fiqhandler *ofh;
oldirqstate = disable_interrupts(PSR_F);
/*
* If we are the currently active FIQ handler, then we
* need to save our registers and pop the next one back
* into the vector.
*/
if (fh == TAILQ_FIRST(&fiqhandler_stack)) {
if (fh->fh_regs != NULL)
fiq_getregs(fh->fh_regs);
TAILQ_REMOVE(&fiqhandler_stack, fh, fh_list);
if ((ofh = TAILQ_FIRST(&fiqhandler_stack)) != NULL) {
if (ofh->fh_regs != NULL)
fiq_setregs(ofh->fh_regs);
fiq_installhandler(ofh->fh_func, ofh->fh_size);
}
} else
TAILQ_REMOVE(&fiqhandler_stack, fh, fh_list);
if (TAILQ_FIRST(&fiqhandler_stack) == NULL) {
/* Copy the NULL handler back down into the vector. */
fiq_installhandler(fiq_nullhandler_code, fiq_nullhandler_size);
/* Make sure FIQs are disabled when we return. */
oldirqstate |= PSR_F;
}
restore_interrupts(oldirqstate);
}

92
sys/arm/arm/fiq_subr.S
View File

@ -1,92 +0,0 @@
/* $NetBSD: fiq_subr.S,v 1.3 2002/04/12 18:50:31 thorpej Exp $ */
/*-
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#include <machine/asm.h>
#include <machine/armreg.h>
/*
* MODE_CHANGE_NOP should be inserted between a mode change and a
* banked register (R8--R15) access.
*/
#if defined(CPU_ARM2) || defined(CPU_ARM250)
#define MODE_CHANGE_NOP mov r0, r0
#else
#define MODE_CHANGE_NOP /* Data sheet says ARM3 doesn't need it */
#endif
#define SWITCH_TO_FIQ_MODE \
mrs r2, cpsr ; \
mov r3, r2 ; \
bic r2, r2, #(PSR_MODE) ; \
orr r2, r2, #(PSR_FIQ32_MODE) ; \
msr cpsr_fsxc, r2
#define BACK_TO_SVC_MODE \
msr cpsr_fsxc, r3
/*
* fiq_getregs:
*
* Fetch the FIQ mode banked registers into the fiqhandler
* structure.
*/
ENTRY(fiq_getregs)
SWITCH_TO_FIQ_MODE
stmia r0, {r8-r13}
BACK_TO_SVC_MODE
RET
END(fiq_getregs)
/*
* fiq_setregs:
*
* Load the FIQ mode banked registers from the fiqhandler
* structure.
*/
ENTRY(fiq_setregs)
SWITCH_TO_FIQ_MODE
ldmia r0, {r8-r13}
BACK_TO_SVC_MODE
RET
END(fiq_setregs)

2
sys/arm/arm/machdep.c
View File

@ -314,7 +314,7 @@ spinlock_enter(void)
td = curthread;
if (td->td_md.md_spinlock_count == 0) {
cspr = disable_interrupts(PSR_I | PSR_F);
cspr = disable_interrupts(PSR_I);
td->td_md.md_spinlock_count = 1;
td->td_md.md_saved_cspr = cspr;
critical_enter();

4
sys/arm/arm/pmap-v6.c
View File

@ -3364,7 +3364,7 @@ pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
* will be affected by the broken mapping, disable interrupts
* until the mapping change is completed.
*/
cspr = disable_interrupts(PSR_I | PSR_F);
cspr = disable_interrupts(PSR_I);
pte1_clear(pte1p);
pmap_tlb_flush_pte1(pmap, va, npte1);
pte1_store(pte1p, npte1);
@ -3389,7 +3389,7 @@ pmap_change_pte1(pmap_t pmap, pt1_entry_t *pte1p, vm_offset_t va,
* mappings. It's absolutely safe in UP case when interrupts
* are disabled.
*/
cspr = disable_interrupts(PSR_I | PSR_F);
cspr = disable_interrupts(PSR_I);
pte1_clear(pte1p);
pmap_tlb_flush_pte1(pmap, va, npte1);
pte1_store(pte1p, npte1);

2
sys/arm/arm/syscall.c
View File

@ -160,8 +160,6 @@ swi_handler(struct trapframe *frame)
if (td->td_md.md_spinlock_count == 0) {
if (__predict_true(frame->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(frame->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
}
syscall(td, frame);

4
sys/arm/arm/trap-v6.c
View File

@ -408,8 +408,6 @@ abort_handler(struct trapframe *tf, int prefetch)
if (td->td_md.md_spinlock_count == 0) {
if (__predict_true(tf->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(tf->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
}
p = td->td_proc;
@ -565,7 +563,7 @@ abort_fatal(struct trapframe *tf, u_int idx, u_int fsr, u_int far,
mode = usermode ? "user" : "kernel";
rw_mode = fsr & FSR_WNR ? "write" : "read";
disable_interrupts(PSR_I|PSR_F);
disable_interrupts(PSR_I);
if (td != NULL) {
printf("Fatal %s mode data abort: '%s' on %s\n", mode,

2
sys/arm/arm/undefined.c
View File

@ -226,8 +226,6 @@ undefinedinstruction(struct trapframe *frame)
/* Enable interrupts if they were enabled before the exception. */
if (__predict_true(frame->tf_spsr & PSR_I) == 0)
enable_interrupts(PSR_I);
if (__predict_true(frame->tf_spsr & PSR_F) == 0)
enable_interrupts(PSR_F);
VM_CNT_INC(v_trap);

2
sys/arm/include/cpu.h
View File

@ -729,7 +729,7 @@ get_cyclecount(void)
#define cpu_spinwait() /* nothing */
#define cpu_lock_delay() DELAY(1)
#define ARM_NVEC 8
#define ARM_NVEC 7
#define ARM_VEC_ALL 0xffffffff
extern vm_offset_t vector_page;

71
sys/arm/include/fiq.h
View File

@ -1,71 +0,0 @@
/* $NetBSD: fiq.h,v 1.1 2001/12/20 01:20:23 thorpej Exp $ */
/*-
* SPDX-License-Identifier: BSD-4-Clause
*
* Copyright (c) 2001 Wasabi Systems, Inc.
* All rights reserved.
*
* Written by Jason R. Thorpe for Wasabi Systems, Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. All advertising materials mentioning features or use of this software
* must display the following acknowledgement:
* This product includes software developed for the NetBSD Project by
* Wasabi Systems, Inc.
* 4. The name of Wasabi Systems, Inc. may not be used to endorse
* or promote products derived from this software without specific prior
* written permission.
*
* THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*/
#ifndef _MACHINE_FIQ_H_
#define _MACHINE_FIQ_H_
#include <sys/queue.h>
struct fiqregs {
u_int fr_r8; /* FIQ mode r8 */
u_int fr_r9; /* FIQ mode r9 */
u_int fr_r10; /* FIQ mode r10 */
u_int fr_r11; /* FIQ mode r11 */
u_int fr_r12; /* FIQ mode r12 */
u_int fr_r13; /* FIQ mode r13 */
};
struct fiqhandler {
TAILQ_ENTRY(fiqhandler) fh_list;/* link in the FIQ handler stack */
void *fh_func; /* FIQ handler routine */
size_t fh_size; /* size of FIQ handler */
int fh_flags; /* flags; see below */
struct fiqregs *fh_regs; /* pointer to regs structure */
};
#define FH_CANPUSH 0x01 /* can push this handler out of the way */
int fiq_claim(struct fiqhandler *);
void fiq_release(struct fiqhandler *);
void fiq_getregs(struct fiqregs *);
void fiq_setregs(struct fiqregs *);
#endif /* _MACHINE_FIQ_H_ */

2
sys/conf/files.arm
View File

@ -25,8 +25,6 @@ arm/arm/elf_machdep.c standard
arm/arm/elf_note.S standard
arm/arm/exception.S standard
arm/arm/exec_machdep.c standard
arm/arm/fiq.c standard
arm/arm/fiq_subr.S standard
arm/arm/fusu.S standard
arm/arm/gdb_machdep.c optional gdb
arm/arm/generic_timer.c optional generic_timer