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- remove the unused parent DMA tag argument from
_nexus_dmamap_load_buffer() - implement nexus_dmamap_load() in terms of _nexus_dmamap_load_buffer(). Note that this is untested, as this code is not currently used (but might be later for UPA devices). - move BUS_DMAMAP_NSEGS to bus_private.h - disable the ecache flushing in nexus_dmamap_sync(); it should not be needed, although the docs are not entirely clear on that.
This commit is contained in:
Thomas Moestl
parent
ceadf51064
commit
702f83a807
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=108821
@ -33,6 +33,8 @@
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#include <sys/queue.h>
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#define BUS_DMAMAP_NSEGS ((BUS_SPACE_MAXSIZE / PAGE_SIZE) + 1)
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struct bus_dmamap {
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bus_dma_tag_t dmat;
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void *buf; /* unmapped buffer pointer */
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@ -301,84 +301,6 @@ nexus_dmamap_destroy(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map)
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return (0);
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}
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#define BUS_DMAMAP_NSEGS ((BUS_SPACE_MAXSIZE / PAGE_SIZE) + 1)
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/*
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* Common function for loading a DMA map with a linear buffer. May
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* be called by bus-specific DMA map load functions.
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*
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* Most SPARCs have IOMMUs in the bus controllers. In those cases
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* they only need one segment and will use virtual addresses for DVMA.
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* Those bus controllers should intercept these vectors and should
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* *NEVER* call nexus_dmamap_load() which is used only by devices that
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* bypass DVMA.
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*/
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static int
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nexus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map,
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void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback,
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void *callback_arg, int flags)
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{
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vm_offset_t vaddr;
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vm_offset_t paddr;
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#ifdef __GNUC__
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bus_dma_segment_t dm_segments[ddmat->dt_nsegments];
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#else
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bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS];
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#endif
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bus_dma_segment_t *sg;
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int seg;
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int error;
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vm_offset_t nextpaddr;
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bus_size_t size;
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error = 0;
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vaddr = (vm_offset_t)buf;
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sg = &dm_segments[0];
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seg = 1;
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sg->ds_len = 0;
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map->buf = buf;
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map->buflen = buflen;
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map->start = (bus_addr_t)buf;
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nextpaddr = 0;
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do {
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paddr = pmap_kextract(vaddr);
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size = PAGE_SIZE - (paddr & PAGE_MASK);
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if (size > buflen)
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size = buflen;
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if (sg->ds_len == 0) {
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sg->ds_addr = paddr;
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sg->ds_len = size;
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} else if (paddr == nextpaddr) {
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sg->ds_len += size;
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} else {
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/* Go to the next segment */
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sg++;
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seg++;
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if (seg > ddmat->dt_nsegments)
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break;
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sg->ds_addr = paddr;
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sg->ds_len = size;
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}
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vaddr += size;
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nextpaddr = paddr + size;
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buflen -= size;
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} while (buflen > 0);
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if (buflen != 0) {
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printf("bus_dmamap_load: Too many segs! buf_len = 0x%lx\n",
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(u_long)buflen);
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error = EFBIG;
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}
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(*callback)(callback_arg, dm_segments, seg, error);
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return (0);
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}
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/*
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* Utility function to load a linear buffer. lastaddrp holds state
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* between invocations (for multiple-buffer loads). segp contains
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@ -386,10 +308,9 @@ nexus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map,
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* first indicates if this is the first invocation of this function.
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*/
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static int
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_nexus_dmamap_load_buffer(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat,
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bus_dma_segment_t segs[], void *buf, bus_size_t buflen,
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struct thread *td, int flags, vm_offset_t *lastaddrp,
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int *segp, int first)
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_nexus_dmamap_load_buffer(bus_dma_tag_t ddmat, bus_dma_segment_t segs[],
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void *buf, bus_size_t buflen, struct thread *td, int flags,
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vm_offset_t *lastaddrp, int *segp, int first)
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{
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bus_size_t sgsize;
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bus_addr_t curaddr, lastaddr, baddr, bmask;
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@ -466,6 +387,40 @@ _nexus_dmamap_load_buffer(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat,
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return (buflen != 0 ? EFBIG : 0); /* XXX better return value here? */
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}
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/*
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* Common function for loading a DMA map with a linear buffer. May
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* be called by bus-specific DMA map load functions.
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*
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* Most SPARCs have IOMMUs in the bus controllers. In those cases
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* they only need one segment and will use virtual addresses for DVMA.
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* Those bus controllers should intercept these vectors and should
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* *NEVER* call nexus_dmamap_load() which is used only by devices that
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* bypass DVMA.
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*/
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static int
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nexus_dmamap_load(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map,
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void *buf, bus_size_t buflen, bus_dmamap_callback_t *callback,
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void *callback_arg, int flags)
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{
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#ifdef __GNUC__
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bus_dma_segment_t dm_segments[ddmat->dt_nsegments];
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#else
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bus_dma_segment_t dm_segments[BUS_DMAMAP_NSEGS];
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#endif
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vm_offset_t lastaddr;
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int error, nsegs;
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error = _nexus_dmamap_load_buffer(ddmat, dm_segments, buf, buflen,
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NULL, flags, &lastaddr, &nsegs, 1);
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if (error == 0) {
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(*callback)(callback_arg, dm_segments, nsegs + 1, 0);
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} else
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(*callback)(callback_arg, NULL, 0, error);
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return (0);
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}
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/*
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* Like nexus_dmamap_load(), but for mbufs.
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*/
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@ -492,7 +447,7 @@ nexus_dmamap_load_mbuf(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat,
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struct mbuf *m;
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for (m = m0; m != NULL && error == 0; m = m->m_next) {
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error = _nexus_dmamap_load_buffer(pdmat, ddmat,
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error = _nexus_dmamap_load_buffer(ddmat,
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dm_segments, m->m_data, m->m_len, NULL, flags,
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&lastaddr, &nsegs, first);
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first = 0;
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@ -551,8 +506,8 @@ nexus_dmamap_load_uio(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat,
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resid < iov[i].iov_len ? resid : iov[i].iov_len;
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caddr_t addr = (caddr_t) iov[i].iov_base;
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error = _nexus_dmamap_load_buffer(pdmat, ddmat, dm_segments,
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addr, minlen, td, flags, &lastaddr, &nsegs, first);
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error = _nexus_dmamap_load_buffer(ddmat, dm_segments, addr,
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minlen, td, flags, &lastaddr, &nsegs, first);
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first = 0;
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resid -= minlen;
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@ -600,15 +555,13 @@ nexus_dmamap_sync(bus_dma_tag_t pdmat, bus_dma_tag_t ddmat, bus_dmamap_t map,
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*/
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membar(Sync);
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}
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#if 0
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/* Should not be needed. */
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if (op == BUS_DMASYNC_POSTREAD) {
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/*
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* Invalidate the caches (it is unclear whether that is really
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* needed. The manual only mentions that PCI transactions are
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* cache coherent).
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*/
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ecache_flush((vm_offset_t)map->buf,
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(vm_offset_t)map->buf + map->buflen - 1);
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}
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#endif
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if (op == BUS_DMASYNC_POSTWRITE) {
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/* Nothing to do. Handled by the bus controller. */
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}
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