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The MDIO control register for the AR8327 has a different address to
previous chipsets. Obtained from: AR8327 datasheet
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svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=262016
@ -395,6 +395,8 @@
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#define AR8327_REG_MIB_FUNC 0x034
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#define AR8327_MIB_CPU_KEEP (1 << 20)
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#define AR8327_REG_MDIO_CTRL 0x03c
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#define AR8327_REG_SERVICE_TAG 0x048
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#define AR8327_REG_LED_CTRL0 0x050
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#define AR8327_REG_LED_CTRL1 0x054
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