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arm64: marvell: Add cp110 clock controller support
The cp110 clock controller controls the clocks and gate of the CP110
hardware block.
Every clock/gate are implemented except the NAND clock.
Sponsored by: Rubicon Communications, LLC ("Netgate")
This commit is contained in:
Emmanuel Vadot
parent
4f3a5b510b
commit
73450c4a7a
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=342014
375
sys/arm/mv/mv_cp110_clock.c
Normal file
375
sys/arm/mv/mv_cp110_clock.c
Normal file
@ -0,0 +1,375 @@
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/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/intr.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_gate.h>
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#include <arm/mv/mv_cp110_clock.h>
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#include "clkdev_if.h"
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/* Clocks */
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static struct clk_fixed_def cp110_clk_pll_0 = {
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.clkdef.id = CP110_PLL_0,
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.freq = 1000000000,
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};
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static const char *clk_parents_0[] = {"cp110-pll0-0"};
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static const char *clk_parents_1[] = {"cp110-pll0-1"};
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static struct clk_fixed_def cp110_clk_ppv2_core = {
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.clkdef.id = CP110_PPV2_CORE,
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.clkdef.parent_cnt = 1,
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.mult = 1,
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.div = 3,
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};
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static struct clk_fixed_def cp110_clk_x2core = {
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.clkdef.id = CP110_X2CORE,
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.clkdef.parent_cnt = 1,
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.mult = 1,
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.div = 2,
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};
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static const char *core_parents_0[] = {"cp110-x2core-0"};
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static const char *core_parents_1[] = {"cp110-x2core-1"};
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static struct clk_fixed_def cp110_clk_core = {
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.clkdef.id = CP110_CORE,
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.clkdef.parent_cnt = 1,
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.mult = 1,
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.div = 2,
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};
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static struct clk_fixed_def cp110_clk_sdio = {
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.clkdef.id = CP110_SDIO,
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.clkdef.parent_cnt = 1,
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.mult = 2,
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.div = 5,
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};
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/* Gates */
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static struct cp110_gate cp110_gates[] = {
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CCU_GATE(CP110_GATE_AUDIO, "cp110-gate-audio", 0)
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CCU_GATE(CP110_GATE_COMM_UNIT, "cp110-gate-comm_unit", 1)
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/* CCU_GATE(CP110_GATE_NAND, "cp110-gate-nand", 2) */
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CCU_GATE(CP110_GATE_PPV2, "cp110-gate-ppv2", 3)
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CCU_GATE(CP110_GATE_SDIO, "cp110-gate-sdio", 4)
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CCU_GATE(CP110_GATE_MG, "cp110-gate-mg", 5)
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CCU_GATE(CP110_GATE_MG_CORE, "cp110-gate-mg_core", 6)
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CCU_GATE(CP110_GATE_XOR1, "cp110-gate-xor1", 7)
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CCU_GATE(CP110_GATE_XOR0, "cp110-gate-xor0", 8)
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CCU_GATE(CP110_GATE_GOP_DP, "cp110-gate-gop_dp", 9)
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CCU_GATE(CP110_GATE_PCIE_X1_0, "cp110-gate-pcie_x10", 11)
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CCU_GATE(CP110_GATE_PCIE_X1_1, "cp110-gate-pcie_x11", 12)
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CCU_GATE(CP110_GATE_PCIE_X4, "cp110-gate-pcie_x4", 13)
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CCU_GATE(CP110_GATE_PCIE_XOR, "cp110-gate-pcie_xor", 14)
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CCU_GATE(CP110_GATE_SATA, "cp110-gate-sata", 15)
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CCU_GATE(CP110_GATE_SATA_USB, "cp110-gate-sata_usb", 16)
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CCU_GATE(CP110_GATE_MAIN, "cp110-gate-main", 17)
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CCU_GATE(CP110_GATE_SDMMC_GOP, "cp110-gate-sdmmc_gop", 18)
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CCU_GATE(CP110_GATE_SLOW_IO, "cp110-gate-slow_io", 21)
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CCU_GATE(CP110_GATE_USB3H0, "cp110-gate-usb3h0", 22)
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CCU_GATE(CP110_GATE_USB3H1, "cp110-gate-usb3h1", 23)
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CCU_GATE(CP110_GATE_USB3DEV, "cp110-gate-usb3dev", 24)
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CCU_GATE(CP110_GATE_EIP150, "cp110-gate-eip150", 25)
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CCU_GATE(CP110_GATE_EIP197, "cp110-gate-eip197", 26)
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};
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struct mv_cp110_clock_softc {
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struct simplebus_softc simplebus_sc;
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device_t dev;
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struct resource *res;
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struct mtx mtx;
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};
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static struct resource_spec mv_cp110_clock_res_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{"marvell,cp110-clock", 1},
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{NULL, 0}
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};
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#define RD4(sc, reg) bus_read_4((sc)->res, (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res, (reg), (val))
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static char *
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mv_cp110_clock_name(device_t dev, const char *name)
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{
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char *clkname = NULL;
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int unit;
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unit = device_get_unit(dev);
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if (asprintf(&clkname, M_DEVBUF, "%s-%d", name, unit) <= 0)
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panic("Cannot generate unique clock name for %s\n", name);
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return (clkname);
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}
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static int
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mv_cp110_clock_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell CP110 Clock Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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cp110_ofw_map(struct clkdom *clkdom, uint32_t ncells,
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phandle_t *cells, struct clknode **clk)
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{
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int id = 0;
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if (ncells != 2)
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return (ENXIO);
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id = cells[1];
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if (cells[0] == 1)
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id += CP110_MAX_CLOCK;
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*clk = clknode_find_by_id(clkdom, id);
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return (0);
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}
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static int
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mv_cp110_clock_attach(device_t dev)
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{
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struct mv_cp110_clock_softc *sc;
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struct clkdom *clkdom;
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struct clk_gate_def def;
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char *pll0_name;
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int unit, i;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, mv_cp110_clock_res_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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unit = device_get_unit(dev);
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if (unit > 1) {
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device_printf(dev, "Bogus cp110-system-controller unit %d\n", unit);
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return (ENXIO);
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}
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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clkdom = clkdom_create(dev);
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clkdom_set_ofw_mapper(clkdom, cp110_ofw_map);
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pll0_name = mv_cp110_clock_name(dev, "cp110-pll0");
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cp110_clk_pll_0.clkdef.name = pll0_name;
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clknode_fixed_register(clkdom, &cp110_clk_pll_0);
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cp110_clk_ppv2_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-ppv2");
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cp110_clk_ppv2_core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
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clknode_fixed_register(clkdom, &cp110_clk_ppv2_core);
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cp110_clk_x2core.clkdef.name = mv_cp110_clock_name(dev, "cp110-x2core");
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cp110_clk_x2core.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
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clknode_fixed_register(clkdom, &cp110_clk_x2core);
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cp110_clk_core.clkdef.name = mv_cp110_clock_name(dev, "cp110-core");
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cp110_clk_core.clkdef.parent_names = (unit == 0) ? core_parents_0 : core_parents_1;
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clknode_fixed_register(clkdom, &cp110_clk_core);
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/* NAND missing */
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cp110_clk_sdio.clkdef.name = mv_cp110_clock_name(dev, "cp110-sdio");
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cp110_clk_sdio.clkdef.parent_names = (unit == 0) ? clk_parents_0 : clk_parents_1;
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clknode_fixed_register(clkdom, &cp110_clk_sdio);
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for (i = 0; i < nitems(cp110_gates); i++) {
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if (cp110_gates[i].name == NULL)
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continue;
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memset(&def, 0, sizeof(def));
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def.clkdef.id = CP110_MAX_CLOCK + i;
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def.clkdef.name = mv_cp110_clock_name(dev, cp110_gates[i].name);
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def.clkdef.parent_cnt = 1;
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def.offset = CP110_CLOCK_GATING_OFFSET;
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def.shift = cp110_gates[i].shift;
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def.mask = 1;
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def.on_value = 1;
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def.off_value = 0;
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switch (i) {
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case CP110_GATE_MG:
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case CP110_GATE_GOP_DP:
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case CP110_GATE_PPV2:
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def.clkdef.parent_names = &cp110_clk_ppv2_core.clkdef.name;
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break;
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case CP110_GATE_SDIO:
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def.clkdef.parent_names = &cp110_clk_sdio.clkdef.name;
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break;
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case CP110_GATE_MAIN:
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case CP110_GATE_PCIE_XOR:
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case CP110_GATE_PCIE_X4:
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case CP110_GATE_EIP150:
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case CP110_GATE_EIP197:
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def.clkdef.parent_names = &cp110_clk_x2core.clkdef.name;
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break;
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default:
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def.clkdef.parent_names = &cp110_clk_core.clkdef.name;
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break;
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}
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clknode_gate_register(clkdom, &def);
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}
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clkdom_finit(clkdom);
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if (bootverbose)
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clkdom_dump(clkdom);
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return (0);
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}
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static int
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mv_cp110_clock_detach(device_t dev)
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{
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return (EBUSY);
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}
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static int
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mv_cp110_clock_write_4(device_t dev, bus_addr_t addr, uint32_t val)
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{
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struct mv_cp110_clock_softc *sc;
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sc = device_get_softc(dev);
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WR4(sc, addr, val);
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return (0);
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}
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static int
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mv_cp110_clock_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
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{
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struct mv_cp110_clock_softc *sc;
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sc = device_get_softc(dev);
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*val = RD4(sc, addr);
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return (0);
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}
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static int
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mv_cp110_clock_modify_4(device_t dev, bus_addr_t addr, uint32_t clr, uint32_t set)
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{
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struct mv_cp110_clock_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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reg = RD4(sc, addr);
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reg &= ~clr;
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reg |= set;
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WR4(sc, addr, reg);
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return (0);
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}
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static void
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mv_cp110_clock_device_lock(device_t dev)
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{
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struct mv_cp110_clock_softc *sc;
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sc = device_get_softc(dev);
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mtx_lock(&sc->mtx);
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}
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static void
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mv_cp110_clock_device_unlock(device_t dev)
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{
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struct mv_cp110_clock_softc *sc;
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sc = device_get_softc(dev);
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mtx_unlock(&sc->mtx);
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}
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static device_method_t mv_cp110_clock_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, mv_cp110_clock_probe),
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||||||
|
DEVMETHOD(device_attach, mv_cp110_clock_attach),
|
||||||
|
DEVMETHOD(device_detach, mv_cp110_clock_detach),
|
||||||
|
|
||||||
|
/* clkdev interface */
|
||||||
|
DEVMETHOD(clkdev_write_4, mv_cp110_clock_write_4),
|
||||||
|
DEVMETHOD(clkdev_read_4, mv_cp110_clock_read_4),
|
||||||
|
DEVMETHOD(clkdev_modify_4, mv_cp110_clock_modify_4),
|
||||||
|
DEVMETHOD(clkdev_device_lock, mv_cp110_clock_device_lock),
|
||||||
|
DEVMETHOD(clkdev_device_unlock, mv_cp110_clock_device_unlock),
|
||||||
|
|
||||||
|
DEVMETHOD_END
|
||||||
|
};
|
||||||
|
|
||||||
|
static devclass_t mv_cp110_clock_devclass;
|
||||||
|
|
||||||
|
static driver_t mv_cp110_clock_driver = {
|
||||||
|
"mv_cp110_clock",
|
||||||
|
mv_cp110_clock_methods,
|
||||||
|
sizeof(struct mv_cp110_clock_softc),
|
||||||
|
};
|
||||||
|
|
||||||
|
EARLY_DRIVER_MODULE(mv_cp110_clock, simplebus, mv_cp110_clock_driver,
|
||||||
|
mv_cp110_clock_devclass, 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE);
|
||||||
82
sys/arm/mv/mv_cp110_clock.h
Normal file
82
sys/arm/mv/mv_cp110_clock.h
Normal file
@ -0,0 +1,82 @@
|
|||||||
|
/*-
|
||||||
|
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
|
||||||
|
*
|
||||||
|
* Copyright (c) 2018 Rubicon Communications, LLC (Netgate)
|
||||||
|
*
|
||||||
|
* Redistribution and use in source and binary forms, with or without
|
||||||
|
* modification, are permitted provided that the following conditions
|
||||||
|
* are met:
|
||||||
|
* 1. Redistributions of source code must retain the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer.
|
||||||
|
* 2. Redistributions in binary form must reproduce the above copyright
|
||||||
|
* notice, this list of conditions and the following disclaimer in the
|
||||||
|
* documentation and/or other materials provided with the distribution.
|
||||||
|
*
|
||||||
|
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
|
||||||
|
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||||
|
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||||
|
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
|
||||||
|
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||||
|
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
||||||
|
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
||||||
|
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||||
|
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
||||||
|
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||||
|
* SUCH DAMAGE.
|
||||||
|
*
|
||||||
|
* $FreeBSD$
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef _MV_CP110_SYSCON_H_
|
||||||
|
#define _MV_CP110_SYSCON_H_
|
||||||
|
|
||||||
|
enum mv_cp110_clk_id {
|
||||||
|
CP110_PLL_0 = 0,
|
||||||
|
CP110_PPV2_CORE,
|
||||||
|
CP110_X2CORE,
|
||||||
|
CP110_CORE,
|
||||||
|
CP110_NAND,
|
||||||
|
CP110_SDIO,
|
||||||
|
CP110_MAX_CLOCK
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Gates */
|
||||||
|
#define CP110_CLOCK_GATING_OFFSET 0x220
|
||||||
|
|
||||||
|
struct cp110_gate {
|
||||||
|
const char *name;
|
||||||
|
uint32_t shift;
|
||||||
|
};
|
||||||
|
|
||||||
|
#define CCU_GATE(idx, clkname, s) \
|
||||||
|
[idx] = { \
|
||||||
|
.name = clkname, \
|
||||||
|
.shift = s, \
|
||||||
|
},
|
||||||
|
|
||||||
|
#define CP110_GATE_AUDIO 0
|
||||||
|
#define CP110_GATE_COMM_UNIT 1
|
||||||
|
#define CP110_GATE_NAND 2
|
||||||
|
#define CP110_GATE_PPV2 3
|
||||||
|
#define CP110_GATE_SDIO 4
|
||||||
|
#define CP110_GATE_MG 5
|
||||||
|
#define CP110_GATE_MG_CORE 6
|
||||||
|
#define CP110_GATE_XOR1 7
|
||||||
|
#define CP110_GATE_XOR0 8
|
||||||
|
#define CP110_GATE_GOP_DP 9
|
||||||
|
#define CP110_GATE_PCIE_X1_0 11
|
||||||
|
#define CP110_GATE_PCIE_X1_1 12
|
||||||
|
#define CP110_GATE_PCIE_X4 13
|
||||||
|
#define CP110_GATE_PCIE_XOR 14
|
||||||
|
#define CP110_GATE_SATA 15
|
||||||
|
#define CP110_GATE_SATA_USB 16
|
||||||
|
#define CP110_GATE_MAIN 17
|
||||||
|
#define CP110_GATE_SDMMC_GOP 18
|
||||||
|
#define CP110_GATE_SLOW_IO 21
|
||||||
|
#define CP110_GATE_USB3H0 22
|
||||||
|
#define CP110_GATE_USB3H1 23
|
||||||
|
#define CP110_GATE_USB3DEV 24
|
||||||
|
#define CP110_GATE_EIP150 25
|
||||||
|
#define CP110_GATE_EIP197 26
|
||||||
|
|
||||||
|
#endif
|
||||||
@ -92,6 +92,7 @@ arm/broadcom/bcm2835/bcm283x_dwc_fdt.c optional dwcotg fdt soc_brcm_bcm2837
|
|||||||
arm/mv/gpio.c optional mv_gpio fdt
|
arm/mv/gpio.c optional mv_gpio fdt
|
||||||
arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt
|
arm/mv/mvebu_pinctrl.c optional mvebu_pinctrl fdt
|
||||||
arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt
|
arm/mv/mv_ap806_clock.c optional SOC_MARVELL_8K fdt
|
||||||
|
arm/mv/mv_cp110_clock.c optional SOC_MARVELL_8K fdt
|
||||||
arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
|
arm/mv/armada38x/armada38x_rtc.c optional mv_rtc fdt
|
||||||
arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq
|
arm/xilinx/uart_dev_cdnc.c optional uart soc_xilinx_zynq
|
||||||
arm64/acpica/acpi_machdep.c optional acpi
|
arm64/acpica/acpi_machdep.c optional acpi
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user