mirror of
https://git.FreeBSD.org/src.git
synced 2025-01-11 14:10:34 +00:00
Unify and generalize PowerPC headers, adjust AIM code accordingly.
Rework of this area is a pre-requirement for importing e500 support (and other PowerPC core variations in the future). Mainly the following headers are refactored so that we can cover for low-level differences between various machines within PowerPC architecture: <machine/pcpu.h> <machine/pcb.h> <machine/kdb.h> <machine/hid.h> <machine/frame.h> Areas which use the above are adjusted and cleaned up. Credits for this rework go to marcel@ Approved by: cognet (mentor) MFp4: e500
This commit is contained in:
Rafal Jaworowski
parent
a0b0d286bc
commit
786e4a1b04
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=176742
@ -107,6 +107,7 @@ __FBSDID("$FreeBSD$");
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#include <machine/cpu.h>
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#include <machine/elf.h>
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#include <machine/fpu.h>
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#include <machine/kdb.h>
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#include <machine/md_var.h>
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#include <machine/metadata.h>
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#include <machine/mmuvar.h>
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@ -519,13 +520,13 @@ sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
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*/
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sf.sf_si = ksi->ksi_info;
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sf.sf_si.si_signo = sig;
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sf.sf_si.si_addr = (void *) ((tf->exc == EXC_DSI) ?
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tf->dar : tf->srr0);
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sf.sf_si.si_addr = (void *)((tf->exc == EXC_DSI) ?
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tf->cpu.aim.dar : tf->srr0);
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} else {
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/* Old FreeBSD-style arguments. */
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tf->fixreg[FIRSTARG+1] = code;
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tf->fixreg[FIRSTARG+3] = (tf->exc == EXC_DSI) ?
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tf->dar : tf->srr0;
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tf->cpu.aim.dar : tf->srr0;
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}
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mtx_unlock(&psp->ps_mtx);
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PROC_UNLOCK(p);
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@ -897,6 +898,20 @@ ptrace_clear_single_step(struct thread *td)
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return (0);
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}
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void
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kdb_cpu_clear_singlestep(void)
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{
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kdb_frame->srr1 &= ~PSL_SE;
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}
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void
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kdb_cpu_set_singlestep(void)
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{
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kdb_frame->srr1 |= PSL_SE;
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}
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/*
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* Initialise a struct pcpu.
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*/
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@ -88,7 +88,7 @@ ENTRY(cpu_switch)
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stw %r16,PCB_LR(%r5)
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mfsr %r16,USER_SR /* Save USER_SR for copyin/out */
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isync
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stw %r16,PCB_USR(%r5)
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stw %r16,PCB_AIM_USR(%r5)
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stw %r1,PCB_SP(%r5) /* Save the stack pointer */
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mr %r14,%r3 /* Copy the old thread ptr... */
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@ -125,7 +125,7 @@ ENTRY(cpu_switch)
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mtcr %r5
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lwz %r5,PCB_LR(%r3) /* Load the link register */
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mtlr %r5
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lwz %r5,PCB_USR(%r3) /* Load the USER_SR segment reg */
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lwz %r5,PCB_AIM_USR(%r3) /* Load the USER_SR segment reg */
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mtsr USER_SR,%r5
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isync
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lwz %r1,PCB_SP(%r3) /* Load the stack pointer */
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@ -292,7 +292,7 @@ printtrap(u_int vector, struct trapframe *frame, int isfatal, int user)
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trapname(vector));
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switch (vector) {
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case EXC_DSI:
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printf(" virtual address = 0x%x\n", frame->dar);
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printf(" virtual address = 0x%x\n", frame->cpu.aim.dar);
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break;
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case EXC_ISI:
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printf(" virtual address = 0x%x\n", frame->srr0);
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@ -510,8 +510,8 @@ trap_pfault(struct trapframe *frame, int user)
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eva = frame->srr0;
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ftype = VM_PROT_READ | VM_PROT_EXECUTE;
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} else {
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eva = frame->dar;
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if (frame->dsisr & DSISR_STORE)
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eva = frame->cpu.aim.dar;
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if (frame->cpu.aim.dsisr & DSISR_STORE)
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ftype = VM_PROT_WRITE;
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else
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ftype = VM_PROT_READ;
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@ -643,12 +643,12 @@ fix_unaligned(struct thread *td, struct trapframe *frame)
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int indicator, reg;
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double *fpr;
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indicator = EXC_ALI_OPCODE_INDICATOR(frame->dsisr);
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indicator = EXC_ALI_OPCODE_INDICATOR(frame->cpu.aim.dsisr);
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switch (indicator) {
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case EXC_ALI_LFD:
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case EXC_ALI_STFD:
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reg = EXC_ALI_RST(frame->dsisr);
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reg = EXC_ALI_RST(frame->cpu.aim.dsisr);
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fpr = &td->td_pcb->pcb_fpu.fpr[reg];
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fputhread = PCPU_GET(fputhread);
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@ -664,12 +664,12 @@ fix_unaligned(struct thread *td, struct trapframe *frame)
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save_fpu(td);
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if (indicator == EXC_ALI_LFD) {
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if (copyin((void *)frame->dar, fpr,
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if (copyin((void *)frame->cpu.aim.dar, fpr,
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sizeof(double)) != 0)
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return -1;
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enable_fpu(td);
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} else {
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if (copyout(fpr, (void *)frame->dar,
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if (copyout(fpr, (void *)frame->cpu.aim.dar,
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sizeof(double)) != 0)
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return -1;
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}
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@ -140,8 +140,8 @@
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stw %r29, FRAME_29+8(%r1); \
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stw %r30, FRAME_30+8(%r1); \
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stw %r31, FRAME_31+8(%r1); \
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lwz %r28,(savearea+CPUSAVE_DAR)(%r2); /* saved DAR */ \
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lwz %r29,(savearea+CPUSAVE_DSISR)(%r2);/* saved DSISR */ \
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lwz %r28,(savearea+CPUSAVE_AIM_DAR)(%r2); /* saved DAR */ \
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lwz %r29,(savearea+CPUSAVE_AIM_DSISR)(%r2);/* saved DSISR */\
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lwz %r30,(savearea+CPUSAVE_SRR0)(%r2); /* saved SRR0 */ \
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lwz %r31,(savearea+CPUSAVE_SRR1)(%r2); /* saved SRR1 */ \
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mfxer %r3; \
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@ -151,8 +151,8 @@
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stw %r3, FRAME_XER+8(1); /* save xer/ctr/exc */ \
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stw %r4, FRAME_CTR+8(1); \
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stw %r5, FRAME_EXC+8(1); \
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stw %r28,FRAME_DAR+8(1); \
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stw %r29,FRAME_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
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stw %r28,FRAME_AIM_DAR+8(1); \
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stw %r29,FRAME_AIM_DSISR+8(1); /* save dsisr/srr0/srr1 */ \
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stw %r30,FRAME_SRR0+8(1); \
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stw %r31,FRAME_SRR1+8(1)
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@ -272,8 +272,8 @@ CNAME(alitrap):
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stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
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mfdar %r30
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mfdsisr %r31
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stw %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
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stw %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
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stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
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stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
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mfsprg1 %r1 /* restore SP, in case of branch */
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mflr %r28 /* save LR */
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mfcr %r29 /* save CR */
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@ -356,8 +356,8 @@ disitrap:
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stw %r31,(PC_TEMPSAVE+CPUSAVE_R31)(%r1)
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mfdar %r30
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mfdsisr %r31
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stw %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1)
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stw %r31,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1)
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stw %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1)
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stw %r31,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1)
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#ifdef KDB
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/* Try and detect a kernel stack overflow */
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@ -373,10 +373,10 @@ disitrap:
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/* Now convert this DSI into a DDB trap. */
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GET_CPUINFO(%r1)
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lwz %r30,(PC_TEMPSAVE+CPUSAVE_DAR)(%r1) /* get DAR */
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stw %r30,(PC_DBSAVE +CPUSAVE_DAR)(%r1) /* save DAR */
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lwz %r30,(PC_TEMPSAVE+CPUSAVE_DSISR)(%r1) /* get DSISR */
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lwz %r30,(PC_DBSAVE +CPUSAVE_DSISR)(%r1) /* save DSISR */
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lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DAR)(%r1) /* get DAR */
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stw %r30,(PC_DBSAVE +CPUSAVE_AIM_DAR)(%r1) /* save DAR */
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lwz %r30,(PC_TEMPSAVE+CPUSAVE_AIM_DSISR)(%r1) /* get DSISR */
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lwz %r30,(PC_DBSAVE +CPUSAVE_AIM_DSISR)(%r1) /* save DSISR */
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lwz %r30,(PC_DISISAVE+CPUSAVE_R28)(%r1) /* get r28 */
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stw %r30,(PC_DBSAVE +CPUSAVE_R28)(%r1) /* save r28 */
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lwz %r31,(PC_DISISAVE+CPUSAVE_R29)(%r1) /* get r29 */
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@ -152,7 +152,7 @@ cpu_fork(struct thread *td1, struct proc *p2, struct thread *td2, int flags)
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pcb->pcb_sp = (register_t)cf;
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pcb->pcb_lr = (register_t)fork_trampoline;
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pcb->pcb_usr = kernel_pmap->pm_sr[USER_SR];
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pcb->pcb_cpu.aim.usr = kernel_pmap->pm_sr[USER_SR];
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/* Setup to release spin count in fork_exit(). */
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td2->td_md.md_spinlock_count = 1;
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@ -330,7 +330,7 @@ cpu_set_upcall(struct thread *td, struct thread *td0)
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pcb2->pcb_sp = (register_t)cf;
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pcb2->pcb_lr = (register_t)fork_trampoline;
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pcb2->pcb_usr = kernel_pmap->pm_sr[USER_SR];
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pcb2->pcb_cpu.aim.usr = kernel_pmap->pm_sr[USER_SR];
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/* Setup to release spin count in fork_exit(). */
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td->td_md.md_spinlock_count = 1;
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@ -50,15 +50,25 @@
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struct trapframe {
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register_t fixreg[32];
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register_t lr;
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int cr;
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int xer;
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int cr;
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int xer;
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register_t ctr;
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register_t srr0;
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register_t srr1;
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register_t dar; /* dar & dsisr are only filled on a DSI trap */
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int dsisr;
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int exc;
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int exc;
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union {
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struct {
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/* dar & dsisr are only filled on a DSI trap */
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register_t dar;
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int dsisr;
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} aim;
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struct {
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register_t dear;
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register_t esr;
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} booke;
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} cpu;
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};
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/*
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* This is to ensure alignment of the stackpointer
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*/
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@ -38,7 +38,6 @@
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#define HID0_EBD 0x10000000 /* Enable 60x bus data parity checking */
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#define HID0_BCLK 0x08000000 /* CLK_OUT clock type selection */
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#define HID0_EICE 0x04000000 /* Enable ICE output */
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#define HID0_TBEN 0x04000000 /* Time base enable (7450) */
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#define HID0_ECLK 0x02000000 /* CLK_OUT clock type selection */
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#define HID0_PAR 0x01000000 /* Disable precharge of ARTRY */
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#define HID0_STEN 0x01000000 /* Software table search enable (7450) */
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@ -71,6 +70,12 @@
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#define HID0_BHT 0x00000004 /* Enable branch history table */
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#define HID0_NOPTI 0x00000001 /* No-op the dcbt(st) */
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#define HID0_AIM_TBEN 0x04000000 /* Time base enable (7450) */
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#define HID0_BOOKE_TBEN 0x00004000 /* Time Base and decr. enable */
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#define HID0_BOOKE_SEL_TBCLK 0x00002000 /* Select Time Base clock */
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#define HID0_BOOKE_MAS7UPDEN 0x00000080 /* Enable MAS7 update (e500v2) */
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#define HID0_BITMASK \
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"\20" \
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"\040EMCP\037DBP\036EBA\035EBD\034BCLK\033EICE\032ECLK\031PAR" \
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@ -95,39 +100,39 @@
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/*
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* HID0 bit definitions per cpu model
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*
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* bit 603 604 750 7400 7410 7450 7457
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* 0 EMCP EMCP EMCP EMCP EMCP - -
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* 1 - ECP DBP - - - -
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* 2 EBA EBA EBA EBA EDA - -
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* 3 EBD EBD EBD EBD EBD - -
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* 4 SBCLK - BCLK BCKL BCLK - -
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* 5 EICE - - - - TBEN TBEN
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* 6 ECLK - ECLK ECLK ECLK - -
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* 7 PAR PAR PAR PAR PAR STEN STEN
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* 8 DOZE - DOZE DOZE DOZE - HBATEN
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* 9 NAP - NAP NAP NAP NAP NAP
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* 10 SLEEP - SLEEP SLEEP SLEEP SLEEP SLEEP
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* 11 DPM - DPM DPM DPM DPM DPM
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* 12 RISEG - - RISEG - - -
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* 13 - - - EIEC EIEC BHTCLR BHTCLR
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* 14 - - - - - XAEN XAEN
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* 15 - NHR NHR NHR NHR NHR NHR
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* 16 ICE ICE ICE ICE ICE ICE ICE
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* 17 DCE DCE DCE DCE DCE DCE DCE
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* 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK
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* 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK
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* 20 ICFI ICFI ICFI ICFI ICFI ICFI ICFI
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* 21 DCFI DCFI DCFI DCFI DCFI DCFI DCFI
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* 22 - - SPD SPD SPG SPD SPD
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* 23 - - IFEM IFTT IFTT - XBSEN
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* 24 - SIE SGE SGE SGE SGE SGE
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* 25 - - DCFA DCFA DCFA - -
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* 26 - - BTIC BTIC BTIC BTIC BTIC
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* 27 FBIOB - - - - LRSTK LRSTK
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* 28 - - ABE - - FOLD FOLD
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* 29 - BHT BHT BHT BHT BHT BHT
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* 30 - - - NOPDST NOPDST NOPDST NOPDST
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* 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI NOPTI
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* bit 603 604 750 7400 7410 7450 7457 e500
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* 0 EMCP EMCP EMCP EMCP EMCP - - EMCP
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* 1 - ECP DBP - - - - -
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* 2 EBA EBA EBA EBA EDA - - -
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* 3 EBD EBD EBD EBD EBD - - -
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* 4 SBCLK - BCLK BCKL BCLK - - -
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* 5 EICE - - - - TBEN TBEN -
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* 6 ECLK - ECLK ECLK ECLK - - -
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* 7 PAR PAR PAR PAR PAR STEN STEN -
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* 8 DOZE - DOZE DOZE DOZE - HBATEN DOZE
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* 9 NAP - NAP NAP NAP NAP NAP NAP
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* 10 SLEEP - SLEEP SLEEP SLEEP SLEEP SLEEP SLEEP
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* 11 DPM - DPM DPM DPM DPM DPM -
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* 12 RISEG - - RISEG - - - -
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* 13 - - - EIEC EIEC BHTCLR BHTCLR -
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* 14 - - - - - XAEN XAEN -
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* 15 - NHR NHR NHR NHR NHR NHR -
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* 16 ICE ICE ICE ICE ICE ICE ICE -
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* 17 DCE DCE DCE DCE DCE DCE DCE TBEN
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* 18 ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK ILOCK SEL_TBCLK
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* 19 DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK DLOCK -
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* 20 ICFI ICFI ICFI ICFI ICFI ICFI ICFI -
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* 21 DCFI DCFI DCFI DCFI DCFI DCFI DCFI -
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* 22 - - SPD SPD SPG SPD SPD -
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* 23 - - IFEM IFTT IFTT - XBSEN -
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* 24 - SIE SGE SGE SGE SGE SGE EN_MAS7_UPDATE
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* 25 - - DCFA DCFA DCFA - - DCFA
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* 26 - - BTIC BTIC BTIC BTIC BTIC -
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* 27 FBIOB - - - - LRSTK LRSTK -
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* 28 - - ABE - - FOLD FOLD -
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* 29 - BHT BHT BHT BHT BHT BHT -
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* 30 - - - NOPDST NOPDST NOPDST NOPDST -
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* 31 NOOPTI - NOOPTI NOPTI NOPTI NOPTI NOPTI NOPTI
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*
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* 604: ECP = Enable cache parity checking
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* 604: SIE = Serial instruction execution disable
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@ -33,22 +33,15 @@
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#include <machine/frame.h>
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#include <machine/md_var.h>
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#include <machine/psl.h>
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#include <machine/spr.h>
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static __inline void
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kdb_cpu_clear_singlestep(void)
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{
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kdb_frame->srr1 &= ~PSL_SE;
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}
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static __inline void
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kdb_cpu_set_singlestep(void)
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{
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kdb_frame->srr1 |= PSL_SE;
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}
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void kdb_cpu_clear_singlestep(void);
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void kdb_cpu_set_singlestep(void);
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static __inline void
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kdb_cpu_sync_icache(unsigned char *addr, size_t size)
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{
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__syncicache(addr, size);
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}
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@ -35,16 +35,14 @@
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#ifndef _MACHINE_PCB_H_
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#define _MACHINE_PCB_H_
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typedef int faultbuf[23];
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typedef int faultbuf[25];
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struct pcb {
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register_t pcb_context[20]; /* non-volatile r14-r31 */
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register_t pcb_cr; /* Condition register */
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register_t pcb_sp; /* stack pointer */
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register_t pcb_lr; /* link register */
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register_t pcb_usr; /* USER_SR segment register */
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struct pmap *pcb_pm; /* pmap of our vmspace */
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struct pmap *pcb_pmreal; /* real address of above */
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faultbuf *pcb_onfault; /* For use during
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copyin/copyout */
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int pcb_flags;
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@ -55,6 +53,16 @@ struct pcb {
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} pcb_fpu; /* Floating point processor */
|
||||
unsigned int pcb_fpcpu; /* which CPU had our FPU
|
||||
stuff. */
|
||||
|
||||
union {
|
||||
struct {
|
||||
register_t usr; /* USER_SR segment */
|
||||
} aim;
|
||||
struct {
|
||||
register_t ctr;
|
||||
register_t xer;
|
||||
} booke;
|
||||
} pcb_cpu;
|
||||
};
|
||||
|
||||
#ifdef _KERNEL
|
||||
|
||||
@ -36,24 +36,75 @@
|
||||
struct pmap;
|
||||
#define CPUSAVE_LEN 8
|
||||
|
||||
#define PCPU_MD_FIELDS \
|
||||
#define PCPU_MD_COMMON_FIELDS \
|
||||
int pc_inside_intr; \
|
||||
struct pmap *pc_curpmap; /* current pmap */ \
|
||||
struct thread *pc_fputhread; /* current fpu user */ \
|
||||
struct thread *pc_fputhread; /* current fpu user */ \
|
||||
register_t pc_tempsave[CPUSAVE_LEN]; \
|
||||
register_t pc_disisave[CPUSAVE_LEN]; \
|
||||
register_t pc_dbsave[CPUSAVE_LEN];
|
||||
|
||||
#define PCPU_MD_AIM_FIELDS
|
||||
|
||||
#define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2)
|
||||
#define BOOKE_TLB_MAXNEST 3
|
||||
#define BOOKE_TLB_SAVELEN 16
|
||||
#define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
|
||||
|
||||
#define PCPU_MD_BOOKE_FIELDS \
|
||||
register_t pc_booke_critsave[BOOKE_CRITSAVE_LEN]; \
|
||||
register_t pc_booke_mchksave[CPUSAVE_LEN]; \
|
||||
register_t pc_booke_tlbsave[BOOKE_TLBSAVE_LEN]; \
|
||||
register_t pc_booke_tlb_level;
|
||||
|
||||
/* Definitions for register offsets within the exception tmp save areas */
|
||||
#define CPUSAVE_R28 0 /* where r28 gets saved */
|
||||
#define CPUSAVE_R29 1 /* where r29 gets saved */
|
||||
#define CPUSAVE_R30 2 /* where r30 gets saved */
|
||||
#define CPUSAVE_R31 3 /* where r31 gets saved */
|
||||
#define CPUSAVE_DAR 4 /* where SPR_DAR gets saved */
|
||||
#define CPUSAVE_DSISR 5 /* where SPR_DSISR gets saved */
|
||||
#define CPUSAVE_AIM_DAR 4 /* where SPR_DAR gets saved */
|
||||
#define CPUSAVE_AIM_DSISR 5 /* where SPR_DSISR gets saved */
|
||||
#define CPUSAVE_BOOKE_DEAR 4 /* where SPR_DEAR gets saved */
|
||||
#define CPUSAVE_BOOKE_ESR 5 /* where SPR_ESR gets saved */
|
||||
#define CPUSAVE_SRR0 6 /* where SRR0 gets saved */
|
||||
#define CPUSAVE_SRR1 7 /* where SRR1 gets saved */
|
||||
|
||||
/* Book-E TLBSAVE is more elaborate */
|
||||
#define TLBSAVE_BOOKE_LR 0
|
||||
#define TLBSAVE_BOOKE_CR 1
|
||||
#define TLBSAVE_BOOKE_SRR0 2
|
||||
#define TLBSAVE_BOOKE_SRR1 3
|
||||
#define TLBSAVE_BOOKE_R20 4
|
||||
#define TLBSAVE_BOOKE_R21 5
|
||||
#define TLBSAVE_BOOKE_R22 6
|
||||
#define TLBSAVE_BOOKE_R23 7
|
||||
#define TLBSAVE_BOOKE_R24 8
|
||||
#define TLBSAVE_BOOKE_R25 9
|
||||
#define TLBSAVE_BOOKE_R26 10
|
||||
#define TLBSAVE_BOOKE_R27 11
|
||||
#define TLBSAVE_BOOKE_R28 12
|
||||
#define TLBSAVE_BOOKE_R29 13
|
||||
#define TLBSAVE_BOOKE_R30 14
|
||||
#define TLBSAVE_BOOKE_R31 15
|
||||
|
||||
#ifndef COMPILING_LINT
|
||||
#ifdef AIM
|
||||
#define PCPU_MD_FIELDS \
|
||||
PCPU_MD_COMMON_FIELDS \
|
||||
PCPU_MD_AIM_FIELDS
|
||||
#endif
|
||||
#ifdef E500
|
||||
#define PCPU_MD_FIELDS \
|
||||
PCPU_MD_COMMON_FIELDS \
|
||||
PCPU_MD_BOOKE_FIELDS
|
||||
#endif
|
||||
#else
|
||||
#define PCPU_MD_FIELDS \
|
||||
PCPU_MD_COMMON_FIELDS \
|
||||
PCPU_MD_AIM_FIELDS \
|
||||
PCPU_MD_BOOKE_FIELDS
|
||||
#endif
|
||||
|
||||
#define PCPUP ((struct pcpu *) powerpc_get_pcpup())
|
||||
|
||||
#define PCPU_GET(member) (PCPUP->pc_ ## member)
|
||||
|
||||
@ -92,8 +92,14 @@ struct db_variable db_regs[] = {
|
||||
{ "ctr", DB_OFFSET(ctr), db_frame },
|
||||
{ "cr", DB_OFFSET(cr), db_frame },
|
||||
{ "xer", DB_OFFSET(xer), db_frame },
|
||||
{ "dar", DB_OFFSET(dar), db_frame },
|
||||
{ "dsisr", DB_OFFSET(dsisr), db_frame },
|
||||
#ifdef AIM
|
||||
{ "dar", DB_OFFSET(cpu.aim.dar), db_frame },
|
||||
{ "dsisr", DB_OFFSET(cpu.aim.dsisr), db_frame },
|
||||
#endif
|
||||
#ifdef E500
|
||||
{ "dear", DB_OFFSET(cpu.booke.dear), db_frame },
|
||||
{ "esr", DB_OFFSET(cpu.booke.esr), db_frame },
|
||||
#endif
|
||||
};
|
||||
struct db_variable *db_eregs = db_regs + sizeof (db_regs)/sizeof (db_regs[0]);
|
||||
|
||||
@ -194,29 +200,33 @@ db_backtrace(struct thread *td, db_addr_t fp, int count)
|
||||
db_printf("%s ", tf->srr1 & PSL_PR ? "user" : "kernel");
|
||||
switch (tf->exc) {
|
||||
case EXC_DSI:
|
||||
/* XXX take advantage of the union. */
|
||||
db_printf("DSI %s trap @ %#x by ",
|
||||
tf->dsisr & DSISR_STORE ? "write" : "read",
|
||||
tf->dar);
|
||||
(tf->cpu.aim.dsisr & DSISR_STORE) ? "write"
|
||||
: "read", tf->cpu.aim.dar);
|
||||
goto print_trap;
|
||||
case EXC_ALI:
|
||||
db_printf("ALI trap @ %#x (DSISR %#x) ",
|
||||
tf->dar, tf->dsisr);
|
||||
/* XXX take advantage of the union. */
|
||||
db_printf("ALI trap @ %#x (xSR %#x) ",
|
||||
tf->cpu.aim.dar, tf->cpu.aim.dsisr);
|
||||
goto print_trap;
|
||||
case EXC_ISI: trapstr = "ISI"; break;
|
||||
case EXC_PGM: trapstr = "PGM"; break;
|
||||
case EXC_SC: trapstr = "SC"; break;
|
||||
case EXC_EXI: trapstr = "EXI"; break;
|
||||
case EXC_MCHK: trapstr = "MCHK"; break;
|
||||
#ifndef E500
|
||||
case EXC_VEC: trapstr = "VEC"; break;
|
||||
case EXC_FPU: trapstr = "FPU"; break;
|
||||
case EXC_FPA: trapstr = "FPA"; break;
|
||||
case EXC_DECR: trapstr = "DECR"; break;
|
||||
case EXC_BPT: trapstr = "BPT"; break;
|
||||
case EXC_TRC: trapstr = "TRC"; break;
|
||||
case EXC_RUNMODETRC: trapstr = "RUNMODETRC"; break;
|
||||
case EXC_PERF: trapstr = "PERF"; break;
|
||||
case EXC_SMI: trapstr = "SMI"; break;
|
||||
case EXC_RST: trapstr = "RST"; break;
|
||||
#endif
|
||||
case EXC_FPU: trapstr = "FPU"; break;
|
||||
case EXC_DECR: trapstr = "DECR"; break;
|
||||
case EXC_PERF: trapstr = "PERF"; break;
|
||||
default: trapstr = NULL; break;
|
||||
}
|
||||
if (trapstr != NULL) {
|
||||
@ -240,7 +250,7 @@ db_backtrace(struct thread *td, db_addr_t fp, int count)
|
||||
db_printf("%-10s r1=%#x cr=%#x xer=%#x ctr=%#x",
|
||||
"", tf->fixreg[1], tf->cr, tf->xer, tf->ctr);
|
||||
if (tf->exc == EXC_DSI)
|
||||
db_printf(" dsisr=%#x", tf->dsisr);
|
||||
db_printf(" sr=%#x", tf->cpu.aim.dsisr);
|
||||
db_printf("\n");
|
||||
stackframe = (db_addr_t) tf->fixreg[1];
|
||||
if (kernel_only && (tf->srr1 & PSL_PR))
|
||||
|
||||
@ -62,21 +62,60 @@ ASSYM(PC_TEMPSAVE, offsetof(struct pcpu, pc_tempsave));
|
||||
ASSYM(PC_DISISAVE, offsetof(struct pcpu, pc_disisave));
|
||||
ASSYM(PC_DBSAVE, offsetof(struct pcpu, pc_dbsave));
|
||||
|
||||
ASSYM(CPUSAVE_R28,CPUSAVE_R28*4);
|
||||
ASSYM(CPUSAVE_R29,CPUSAVE_R29*4);
|
||||
ASSYM(CPUSAVE_R30,CPUSAVE_R30*4);
|
||||
ASSYM(CPUSAVE_R31,CPUSAVE_R31*4);
|
||||
ASSYM(CPUSAVE_DAR,CPUSAVE_DAR*4);
|
||||
ASSYM(CPUSAVE_DSISR,CPUSAVE_DSISR*4);
|
||||
ASSYM(CPUSAVE_SRR0,CPUSAVE_SRR0*4);
|
||||
ASSYM(CPUSAVE_SRR1,CPUSAVE_SRR1*4);
|
||||
#ifdef E500
|
||||
ASSYM(PC_BOOKE_CRITSAVE, offsetof(struct pcpu, pc_booke_critsave));
|
||||
ASSYM(PC_BOOKE_MCHKSAVE, offsetof(struct pcpu, pc_booke_mchksave));
|
||||
ASSYM(PC_BOOKE_TLBSAVE, offsetof(struct pcpu, pc_booke_tlbsave));
|
||||
ASSYM(PC_BOOKE_TLB_LEVEL, offsetof(struct pcpu, pc_booke_tlb_level));
|
||||
#endif
|
||||
|
||||
ASSYM(CPUSAVE_R28, CPUSAVE_R28*4);
|
||||
ASSYM(CPUSAVE_R29, CPUSAVE_R29*4);
|
||||
ASSYM(CPUSAVE_R30, CPUSAVE_R30*4);
|
||||
ASSYM(CPUSAVE_R31, CPUSAVE_R31*4);
|
||||
ASSYM(CPUSAVE_SRR0, CPUSAVE_SRR0*4);
|
||||
ASSYM(CPUSAVE_SRR1, CPUSAVE_SRR1*4);
|
||||
ASSYM(CPUSAVE_AIM_DAR, CPUSAVE_AIM_DAR*4);
|
||||
ASSYM(CPUSAVE_AIM_DSISR, CPUSAVE_AIM_DSISR*4);
|
||||
ASSYM(CPUSAVE_BOOKE_DEAR, CPUSAVE_BOOKE_DEAR*4);
|
||||
ASSYM(CPUSAVE_BOOKE_ESR, CPUSAVE_BOOKE_ESR*4);
|
||||
|
||||
ASSYM(TLBSAVE_BOOKE_LR, TLBSAVE_BOOKE_LR*4);
|
||||
ASSYM(TLBSAVE_BOOKE_CR, TLBSAVE_BOOKE_CR*4);
|
||||
ASSYM(TLBSAVE_BOOKE_SRR0, TLBSAVE_BOOKE_SRR0*4);
|
||||
ASSYM(TLBSAVE_BOOKE_SRR1, TLBSAVE_BOOKE_SRR1*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R20, TLBSAVE_BOOKE_R20*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R21, TLBSAVE_BOOKE_R21*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R22, TLBSAVE_BOOKE_R22*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R23, TLBSAVE_BOOKE_R23*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R24, TLBSAVE_BOOKE_R24*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R25, TLBSAVE_BOOKE_R25*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R26, TLBSAVE_BOOKE_R26*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R27, TLBSAVE_BOOKE_R27*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R28, TLBSAVE_BOOKE_R28*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R29, TLBSAVE_BOOKE_R29*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R30, TLBSAVE_BOOKE_R30*4);
|
||||
ASSYM(TLBSAVE_BOOKE_R31, TLBSAVE_BOOKE_R31*4);
|
||||
|
||||
ASSYM(MTX_LOCK, offsetof(struct mtx, mtx_lock));
|
||||
ASSYM(MTX_RECURSECNT, offsetof(struct mtx, mtx_recurse));
|
||||
|
||||
#if defined(AIM)
|
||||
ASSYM(PM_KERNELSR, offsetof(struct pmap, pm_sr[KERNEL_SR]));
|
||||
ASSYM(PM_USRSR, offsetof(struct pmap, pm_sr[USER_SR]));
|
||||
ASSYM(PM_SR, offsetof(struct pmap, pm_sr));
|
||||
#elif defined(E500)
|
||||
ASSYM(PM_PDIR, offsetof(struct pmap, pm_pdir));
|
||||
#endif
|
||||
|
||||
#if defined(E500)
|
||||
ASSYM(PTE_RPN, offsetof(struct pte_entry, rpn));
|
||||
ASSYM(PTE_FLAGS, offsetof(struct pte_entry, flags));
|
||||
ASSYM(TLB0TABLE_MAS1, offsetof(struct tlb_entry, mas1));
|
||||
ASSYM(TLB0TABLE_MAS2, offsetof(struct tlb_entry, mas2));
|
||||
ASSYM(TLB0TABLE_MAS3, offsetof(struct tlb_entry, mas3));
|
||||
ASSYM(TLB0_ENTRY_SIZE, sizeof(struct tlb_entry));
|
||||
#endif
|
||||
|
||||
ASSYM(FSP, 8);
|
||||
ASSYM(FRAMELEN, FRAMELEN);
|
||||
@ -118,9 +157,11 @@ ASSYM(FRAME_CTR, offsetof(struct trapframe, ctr));
|
||||
ASSYM(FRAME_XER, offsetof(struct trapframe, xer));
|
||||
ASSYM(FRAME_SRR0, offsetof(struct trapframe, srr0));
|
||||
ASSYM(FRAME_SRR1, offsetof(struct trapframe, srr1));
|
||||
ASSYM(FRAME_DAR, offsetof(struct trapframe, dar));
|
||||
ASSYM(FRAME_DSISR, offsetof(struct trapframe, dsisr));
|
||||
ASSYM(FRAME_EXC, offsetof(struct trapframe, exc));
|
||||
ASSYM(FRAME_AIM_DAR, offsetof(struct trapframe, cpu.aim.dar));
|
||||
ASSYM(FRAME_AIM_DSISR, offsetof(struct trapframe, cpu.aim.dsisr));
|
||||
ASSYM(FRAME_BOOKE_DEAR, offsetof(struct trapframe, cpu.booke.dear));
|
||||
ASSYM(FRAME_BOOKE_ESR, offsetof(struct trapframe, cpu.booke.esr));
|
||||
|
||||
ASSYM(CF_FUNC, offsetof(struct callframe, cf_func));
|
||||
ASSYM(CF_ARG0, offsetof(struct callframe, cf_arg0));
|
||||
@ -129,14 +170,16 @@ ASSYM(CF_SIZE, sizeof(struct callframe));
|
||||
|
||||
ASSYM(PCB_CONTEXT, offsetof(struct pcb, pcb_context));
|
||||
ASSYM(PCB_CR, offsetof(struct pcb, pcb_cr));
|
||||
ASSYM(PCB_PMR, offsetof(struct pcb, pcb_pmreal));
|
||||
ASSYM(PCB_SP, offsetof(struct pcb, pcb_sp));
|
||||
ASSYM(PCB_LR, offsetof(struct pcb, pcb_lr));
|
||||
ASSYM(PCB_USR, offsetof(struct pcb, pcb_usr));
|
||||
ASSYM(PCB_ONFAULT, offsetof(struct pcb, pcb_onfault));
|
||||
ASSYM(PCB_FLAGS, offsetof(struct pcb, pcb_flags));
|
||||
ASSYM(PCB_FPU, PCB_FPU);
|
||||
|
||||
ASSYM(PCB_AIM_USR, offsetof(struct pcb, pcb_cpu.aim.usr));
|
||||
ASSYM(PCB_BOOKE_CTR, offsetof(struct pcb, pcb_cpu.booke.ctr));
|
||||
ASSYM(PCB_BOOKE_XER, offsetof(struct pcb, pcb_cpu.booke.xer));
|
||||
|
||||
ASSYM(TD_LOCK, offsetof(struct thread, td_lock));
|
||||
ASSYM(TD_PROC, offsetof(struct thread, td_proc));
|
||||
ASSYM(TD_PCB, offsetof(struct thread, td_pcb));
|
||||
|
||||
Loading…
Reference in New Issue
Block a user