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Code Issues Releases Activity

Correctly set the interrupt enable and disable bits. The previous

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code interfered with Performant mode and legacy interrupts.  Also
remove a register read operation on the Simplq code that was
effectively a time-wasting no-op.
This commit is contained in:
Scott Long 2008-08-02 13:04:26 +00:00
parent 08cfba5d14
commit 8792c6abd8
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=181177
2 changed files with 11 additions and 15 deletions
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4
sys/dev/ciss/ciss.c
View File

@ -2028,10 +2028,6 @@ ciss_done(struct ciss_softc *sc, cr_qhead_t *qh)
*/
for (;;) {
/* see if the OPQ contains anything */
if (!CISS_TL_SIMPLE_OPQ_INTERRUPT(sc))
break;
tag = CISS_TL_SIMPLE_FETCH_CMD(sc);
if (tag == CISS_TL_SIMPLE_OPQ_EMPTY)
break;

22
sys/dev/ciss/cissreg.h
View File

@ -736,17 +736,17 @@ struct ciss_bmic_flush_cache {
#define CISS_MSI_COUNT 4
/*
* XXX documentation conflicts with the Linux driver as to whether setting or clearing
* bits masks interrupts
* XXX Here we effectively trust the BIOS to set the IMR correctly. But if
* we don't trust it, will we get into trouble with wrongly assuming what it
* should be?
*/
#define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \
CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \
CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) | (sc)->ciss_interrupt_mask)
#define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \
CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \
CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) & ~(sc)->ciss_interrupt_mask)
#define CISS_TL_SIMPLE_OPQ_INTERRUPT(sc) \
(CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_ISR) & (sc)->ciss_interrupt_mask)
#define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \
do { \
(sc)->ciss_interrupt_mask = \
CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR); \
CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, ~0); \
} while (0)
#define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \
CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, (sc)->ciss_interrupt_mask)
#endif /* _KERNEL */