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o Determine the number of LAWs in a way the is future proof. Only the

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MPC8555(E) has 8 LAWs, so don't make that the default case. Current
    processors have 12 LAWs so use that as the default instead.
o   Determine the target ID of the PCI/PCI-X and PCI-E controllers in
    a way that's more future proof. There's almost a perfect mapping
    from HC register offset to target ID, so use that as the default.
    Handle the MPC8548(E) specially, since it has a non-standard target
    ID for the PCI-E controller. Don't worry about whether the processor
    implements the target ID here, because we should not get called for
    PCI/PCI-X or PCI-E host controllers that don't exist.
This commit is contained in:
Marcel Moolenaar 2011-05-28 19:14:16 +00:00
parent 7591d5a373
commit 8a4b7c64b3
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=222428
1 changed files with 14 additions and 7 deletions
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21
sys/powerpc/mpc85xx/mpc85xx.c
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@ -69,12 +69,13 @@ law_getmax(void)
uint32_t ver;
ver = SVR_VER(mfspr(SPR_SVR));
if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
return (12);
else if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
return (10);
else
if (ver == SVR_MPC8555E || ver == SVR_MPC8555)
return (8);
if (ver == SVR_MPC8548E || ver == SVR_MPC8548 ||
ver == SVR_MPC8533E || ver == SVR_MPC8533)
return (10);
return (12);
}
#define _LAW_SR(trgt,size) (0x80000000 | (trgt << 20) | (ffsl(size) - 2))
@ -152,10 +153,16 @@ law_pci_target(struct resource *res, int *trgt_mem, int *trgt_io)
trgt = 1;
break;
case 0xa000:
if (ver == SVR_MPC8572E || ver == SVR_MPC8572)
trgt = 2;
if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
trgt = 3;
else
trgt = 2;
break;
case 0xb000:
if (ver == SVR_MPC8548E || ver == SVR_MPC8548)
rv = EINVAL;
else
trgt = 3;
break;
default:
rv = ENXIO;