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synced 2024-12-20 11:11:24 +00:00
MFp4:
o Fix the packet statistics o Make sure we set the FD bit when in full duplex o Improve TX side efficency by eliminating a data copy for unfragmented mbufs (the hardware can't do s/g). o Minor busdma pedantry o better comments in some places, more XXX in others o Minor style nits. This solves a problem I was seeing where I'd get no ethernet when not booting with a NFS root. Well, unless I unplugged the cable and plugged it back in first so I'd get the same up down up messages I get for NFS root... Thanks to sam and scottl for suggestions on making this driver more efficient through better use of approrpiate APIs.
This commit is contained in:
Warner Losh
parent
1df1b94714
commit
8cd5dc08c3
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=163937
@ -195,7 +195,6 @@ ate_attach(device_t dev)
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ate_get_mac(sc, eaddr);
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ate_set_mac(sc, eaddr);
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sc->ifp = ifp = if_alloc(IFT_ETHER);
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if (mii_phy_probe(dev, &sc->miibus, ate_ifmedia_upd, ate_ifmedia_sts)) {
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device_printf(dev, "Cannot find my PHY.\n");
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@ -271,10 +270,12 @@ ate_load_rx_buf(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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* For the last buffer, set the wrap bit so the controller
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* restarts from the first descriptor.
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*/
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bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_PREWRITE);
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if (i == ATE_MAX_RX_BUFFERS - 1)
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sc->rx_descs[i].addr = segs[0].ds_addr | ETH_WRAP_BIT;
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else
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sc->rx_descs[i].addr = segs[0].ds_addr;
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bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map, BUS_DMASYNC_POSTWRITE);
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sc->rx_descs[i].status = 0;
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/* Flush the memory in the mbuf */
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bus_dmamap_sync(sc->rxtag, sc->rx_map[i], BUS_DMASYNC_PREREAD);
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@ -488,12 +489,31 @@ ate_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
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ATE_UNLOCK(sc);
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}
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static void
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ate_stat_update(struct ate_softc *sc, int active)
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{
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/*
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* The speed and full/half-duplex state needs to be reflected
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* in the ETH_CFG register.
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*/
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if (IFM_SUBTYPE(active) == IFM_10_T)
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_SPD);
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else
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_SPD);
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if (active & IFM_FDX)
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) | ETH_CFG_FD);
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else
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) & ~ETH_CFG_FD);
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}
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static void
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ate_tick(void *xsc)
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{
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struct ate_softc *sc = xsc;
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struct ifnet *ifp = sc->ifp;
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struct mii_data *mii;
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int active;
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uint32_t c;
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/*
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* The KB920x boot loader tests ETH_SR & ETH_SR_LINK and will ask
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@ -506,25 +526,8 @@ ate_tick(void *xsc)
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active = mii->mii_media_active;
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mii_tick(mii);
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if (mii->mii_media_status & IFM_ACTIVE &&
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active != mii->mii_media_active) {
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/*
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* The speed and full/half-duplex state needs
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* to be reflected in the ETH_CFG register, it
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* seems.
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*/
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if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) &
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~ETH_CFG_SPD);
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else
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) |
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ETH_CFG_SPD);
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if (mii->mii_media_active & IFM_FDX)
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) |
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ETH_CFG_FD);
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else
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WR4(sc, ETH_CFG, RD4(sc, ETH_CFG) &
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~ETH_CFG_FD);
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}
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active != mii->mii_media_active)
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ate_stat_update(sc, mii->mii_media_active);
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}
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/*
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@ -535,16 +538,25 @@ ate_tick(void *xsc)
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* the dot3Stats mib, so for those we just count them as general
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* errors. Stats for iframes, ibutes, oframes and obytes are
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* collected elsewhere. These registers zero on a read to prevent
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* races.
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* races. For all the collision stats, also update the collision
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* stats for the interface.
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*/
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sc->mibdata.dot3StatsAlignmentErrors += RD4(sc, ETH_ALE);
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sc->mibdata.dot3StatsFCSErrors += RD4(sc, ETH_SEQE);
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sc->mibdata.dot3StatsSingleCollisionFrames += RD4(sc, ETH_SCOL);
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sc->mibdata.dot3StatsMultipleCollisionFrames += RD4(sc, ETH_MCOL);
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c = RD4(sc, ETH_SCOL);
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ifp->if_collisions += c;
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sc->mibdata.dot3StatsSingleCollisionFrames += c;
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c = RD4(sc, ETH_MCOL);
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sc->mibdata.dot3StatsMultipleCollisionFrames += c;
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ifp->if_collisions += c;
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sc->mibdata.dot3StatsSQETestErrors += RD4(sc, ETH_SQEE);
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sc->mibdata.dot3StatsDeferredTransmissions += RD4(sc, ETH_DTE);
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sc->mibdata.dot3StatsLateCollisions += RD4(sc, ETH_LCOL);
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sc->mibdata.dot3StatsExcessiveCollisions += RD4(sc, ETH_ECOL);
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c = RD4(sc, ETH_LCOL);
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sc->mibdata.dot3StatsLateCollisions += c;
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ifp->if_collisions += c;
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c = RD4(sc, ETH_ECOL);
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sc->mibdata.dot3StatsExcessiveCollisions += c;
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ifp->if_collisions += c;
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sc->mibdata.dot3StatsCarrierSenseErrors += RD4(sc, ETH_CSE);
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sc->mibdata.dot3StatsFrameTooLongs += RD4(sc, ETH_ELR);
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sc->mibdata.dot3StatsInternalMacReceiveErrors += RD4(sc, ETH_DRFC);
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@ -552,7 +564,7 @@ ate_tick(void *xsc)
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* not sure where to lump these, so count them against the errors
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* for the interface.
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*/
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sc->ifp->if_oerrors += RD4(sc, ETH_CSE) + RD4(sc, ETH_TUE);
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sc->ifp->if_oerrors += RD4(sc, ETH_TUE);
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sc->ifp->if_ierrors += RD4(sc, ETH_CDE) + RD4(sc, ETH_RJB) +
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RD4(sc, ETH_USF);
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@ -577,9 +589,9 @@ ate_get_mac(struct ate_softc *sc, u_char *eaddr)
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uint32_t low, high;
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/*
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* The KB920x loaders will setup the MAC with an address, if one
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* is set in the loader. The TSC loader will also set the MAC address
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* in a similar way. Grab the MAC address from the SA1[HL] registers.
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* The boot loader setup the MAC with an address, if one is set in
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* the loader. The TSC loader will also set the MAC address in a
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* similar way. Grab the MAC address from the SA1[HL] registers.
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*/
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low = RD4(sc, ETH_SA1L);
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high = RD4(sc, ETH_SA1H);
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@ -595,6 +607,7 @@ static void
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ate_intr(void *xsc)
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{
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struct ate_softc *sc = xsc;
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struct ifnet *ifp = sc->ifp;
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int status;
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int i;
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void *bp;
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@ -614,15 +627,18 @@ ate_intr(void *xsc)
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rx_stat = sc->rx_descs[i].status;
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if ((rx_stat & ETH_LEN_MASK) == 0) {
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printf("ignoring bogus 0 len packet\n");
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sc->rx_descs[i].addr &= ~ETH_CPU_OWNER;
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bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
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BUS_DMASYNC_PREWRITE);
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sc->rx_descs[i].addr &= ~ETH_CPU_OWNER;
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bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
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BUS_DMASYNC_POSTWRITE);
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continue;
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}
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/* Flush memory for mbuf so we don't get stale bytes */
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bus_dmamap_sync(sc->rxtag, sc->rx_map[i],
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BUS_DMASYNC_POSTREAD);
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WR4(sc, ETH_RSR, RD4(sc, ETH_RSR)); // XXX WHY? XXX imp
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WR4(sc, ETH_RSR, RD4(sc, ETH_RSR));
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/*
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* The length returned by the device includes the
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* ethernet CRC calculation for the packet, but
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@ -630,25 +646,37 @@ ate_intr(void *xsc)
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*/
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mb = m_devget(sc->rx_buf[i],
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(rx_stat & ETH_LEN_MASK) - ETHER_CRC_LEN,
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ETHER_ALIGN, sc->ifp, NULL);
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sc->rx_descs[i].addr &= ~ETH_CPU_OWNER;
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ETHER_ALIGN, ifp, NULL);
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bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
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BUS_DMASYNC_PREWRITE);
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sc->rx_descs[i].addr &= ~ETH_CPU_OWNER;
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bus_dmamap_sync(sc->rx_desc_tag, sc->rx_desc_map,
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BUS_DMASYNC_POSTWRITE);
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bus_dmamap_sync(sc->rxtag, sc->rx_map[i],
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BUS_DMASYNC_PREREAD);
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if (mb != NULL)
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(*sc->ifp->if_input)(sc->ifp, mb);
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if (mb != NULL) {
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ifp->if_ipackets++;
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(*ifp->if_input)(ifp, mb);
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}
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}
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}
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if (status & ETH_ISR_TCOM) {
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ATE_LOCK(sc);
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/* XXX TSR register should be cleared */
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if (sc->sent_mbuf[0]) {
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bus_dmamap_sync(sc->rxtag, sc->tx_map[0],
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BUS_DMASYNC_POSTWRITE);
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m_freem(sc->sent_mbuf[0]);
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ifp->if_opackets++;
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sc->sent_mbuf[0] = NULL;
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}
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if (sc->sent_mbuf[1]) {
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if (RD4(sc, ETH_TSR) & ETH_TSR_IDLE) {
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bus_dmamap_sync(sc->rxtag, sc->tx_map[1],
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BUS_DMASYNC_POSTWRITE);
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m_freem(sc->sent_mbuf[1]);
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ifp->if_opackets++;
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sc->txcur = 0;
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sc->sent_mbuf[0] = sc->sent_mbuf[1] = NULL;
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} else {
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@ -684,6 +712,7 @@ ateinit_locked(void *xsc)
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{
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struct ate_softc *sc = xsc;
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struct ifnet *ifp = sc->ifp;
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struct mii_data *mii;
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ATE_ASSERT_LOCKED(sc);
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@ -731,6 +760,10 @@ ateinit_locked(void *xsc)
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*/
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ifp->if_drv_flags |= IFF_DRV_RUNNING;
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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mii = device_get_softc(sc->miibus);
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mii_pollstat(mii);
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ate_stat_update(sc, mii->mii_media_active);
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atestart_locked(ifp);
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callout_reset(&sc->tick_ch, hz, ate_tick, sc);
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@ -745,7 +778,7 @@ atestart_locked(struct ifnet *ifp)
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struct ate_softc *sc = ifp->if_softc;
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struct mbuf *m, *mdefrag;
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bus_dma_segment_t segs[1];
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int nseg;
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int nseg, e;
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ATE_ASSERT_LOCKED(sc);
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if (ifp->if_drv_flags & IFF_DRV_OACTIVE)
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@ -767,14 +800,19 @@ atestart_locked(struct ifnet *ifp)
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ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
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return;
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}
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mdefrag = m_defrag(m, M_DONTWAIT);
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if (mdefrag == NULL) {
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IFQ_DRV_PREPEND(&ifp->if_snd, m);
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return;
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e = bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m,
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segs, &nseg, 0);
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if (e == EFBIG) {
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mdefrag = m_defrag(m, M_DONTWAIT);
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if (mdefrag == NULL) {
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IFQ_DRV_PREPEND(&ifp->if_snd, m);
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return;
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}
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m = mdefrag;
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e = bus_dmamap_load_mbuf_sg(sc->mtag,
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sc->tx_map[sc->txcur], m, segs, &nseg, 0);
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}
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m = mdefrag;
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if (bus_dmamap_load_mbuf_sg(sc->mtag, sc->tx_map[sc->txcur], m,
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segs, &nseg, 0) != 0) {
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if (e != 0) {
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m_freem(m);
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continue;
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}
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