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Code Issues Releases Activity

No need to zero the softc. It's allocated with M_ZERO.

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Use pci_enable_busmaster instead of setting PCIM_CMD_BUSMASTEREN
directly. There's no need to set PCIM_CMD_MEMEN. The bit is set when a
SYS_RES_MEMORY resource is activated.

Remove redundant pci_* function calls from suspend/resume methods. The
bus driver already saves and restores the PCI configuration.

Write 1 byte instead of 4 when setting the HIFN_TRDY_TIMEOUT register.
It is only 1 byte according to the specification.

Reviewed by:	jhb
Approved by:	kib (mentor)
This commit is contained in:
Tijl Coosemans 2010-12-18 14:24:24 +00:00
parent 0e4e9e170c
commit 8dca9d3328
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=216519
1 changed files with 3 additions and 27 deletions
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30
sys/dev/hifn/hifn7751.c
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@ -355,14 +355,11 @@ static int
hifn_attach(device_t dev) hifn_attach(device_t dev)
{ {
struct hifn_softc *sc = device_get_softc(dev); struct hifn_softc *sc = device_get_softc(dev);
u_int32_t cmd;
caddr_t kva; caddr_t kva;
int rseg, rid; int rseg, rid;
char rbase; char rbase;
u_int16_t ena, rev; u_int16_t ena, rev;
KASSERT(sc != NULL, ("hifn_attach: null software carrier!"));
bzero(sc, sizeof (*sc));
sc->sc_dev = dev; sc->sc_dev = dev;
mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF); mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "hifn driver", MTX_DEF);
@ -401,31 +398,14 @@ hifn_attach(device_t dev)
hifn_getpllconfig(dev, &sc->sc_pllconfig); hifn_getpllconfig(dev, &sc->sc_pllconfig);
} }
/*
* Configure support for memory-mapped access to
* registers and for DMA operations.
*/
#define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN)
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
cmd |= PCIM_ENA;
pci_write_config(dev, PCIR_COMMAND, cmd, 4);
cmd = pci_read_config(dev, PCIR_COMMAND, 4);
if ((cmd & PCIM_ENA) != PCIM_ENA) {
device_printf(dev, "failed to enable %s\n",
(cmd & PCIM_ENA) == 0 ?
"memory mapping & bus mastering" :
(cmd & PCIM_CMD_MEMEN) == 0 ?
"memory mapping" : "bus mastering");
goto fail_pci;
}
#undef PCIM_ENA
/* /*
* Setup PCI resources. Note that we record the bus * Setup PCI resources. Note that we record the bus
* tag and handle for each register mapping, this is * tag and handle for each register mapping, this is
* used by the READ_REG_0, WRITE_REG_0, READ_REG_1, * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
* and WRITE_REG_1 macros throughout the driver. * and WRITE_REG_1 macros throughout the driver.
*/ */
pci_enable_busmaster(dev);
rid = HIFN_BAR0; rid = HIFN_BAR0;
sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, sc->sc_bar0res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE); RF_ACTIVE);
@ -727,10 +707,6 @@ hifn_resume(device_t dev)
{ {
struct hifn_softc *sc = device_get_softc(dev); struct hifn_softc *sc = device_get_softc(dev);
#ifdef notyet #ifdef notyet
/* reenable busmastering */
pci_enable_busmaster(dev);
pci_enable_io(dev, HIFN_RES);
/* reinitialize interface if necessary */ /* reinitialize interface if necessary */
if (ifp->if_flags & IFF_UP) if (ifp->if_flags & IFF_UP)
rl_init(sc); rl_init(sc);
@ -910,7 +886,7 @@ hifn_set_retry(struct hifn_softc *sc)
{ {
/* NB: RETRY only responds to 8-bit reads/writes */ /* NB: RETRY only responds to 8-bit reads/writes */
pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1); pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4); pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 1);
} }
/* /*