mirror of
https://git.FreeBSD.org/src.git
synced 2024-12-24 11:29:10 +00:00
Add driver for Altera SoftDMA® device.
SoftDMA is a software implementation of DMA engine built using Altera FIFO component. Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D9620
This commit is contained in:
Ruslan Bukin
parent
80b5058dcc
commit
8f89e7db08
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=332472
@ -837,6 +837,7 @@ dev/altera/sdcard/altera_sdcard_disk.c optional altera_sdcard
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dev/altera/sdcard/altera_sdcard_io.c optional altera_sdcard
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dev/altera/sdcard/altera_sdcard_fdt.c optional altera_sdcard fdt
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dev/altera/sdcard/altera_sdcard_nexus.c optional altera_sdcard
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dev/altera/softdma/softdma.c optional altera_softdma xdma fdt
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dev/altera/pio/pio.c optional altera_pio
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dev/altera/pio/pio_if.m optional altera_pio
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dev/amdpm/amdpm.c optional amdpm pci | nfpm pci
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@ -88,7 +88,7 @@ __FBSDID("$FreeBSD$");
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#include <dev/mii/miivar.h>
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#include <dev/altera/atse/if_atsereg.h>
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#include <dev/altera/atse/a_api.h>
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#include <dev/altera/softdma/a_api.h>
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MODULE_DEPEND(atse, ether, 1, 1, 1);
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MODULE_DEPEND(atse, miibus, 1, 1, 1);
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864
sys/dev/altera/softdma/softdma.c
Normal file
864
sys/dev/altera/softdma/softdma.c
Normal file
@ -0,0 +1,864 @@
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/*-
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* Copyright (c) 2017-2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* This is driver for SoftDMA device built using Altera FIFO component. */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/kthread.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#ifdef FDT
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#endif
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#include <dev/altera/softdma/a_api.h>
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#include <dev/xdma/xdma.h>
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#include "xdma_if.h"
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#define SOFTDMA_DEBUG
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#undef SOFTDMA_DEBUG
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#ifdef SOFTDMA_DEBUG
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#define dprintf(fmt, ...) printf(fmt, ##__VA_ARGS__)
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#else
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#define dprintf(fmt, ...)
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#endif
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#define AVALON_FIFO_TX_BASIC_OPTS_DEPTH 16
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#define SOFTDMA_NCHANNELS 1
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#define CONTROL_GEN_SOP (1 << 0)
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#define CONTROL_GEN_EOP (1 << 1)
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#define CONTROL_OWN (1 << 31)
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#define SOFTDMA_RX_EVENTS \
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(A_ONCHIP_FIFO_MEM_CORE_INTR_FULL | \
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A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW | \
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A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
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#define SOFTDMA_TX_EVENTS \
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(A_ONCHIP_FIFO_MEM_CORE_INTR_EMPTY | \
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A_ONCHIP_FIFO_MEM_CORE_INTR_OVERFLOW | \
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A_ONCHIP_FIFO_MEM_CORE_INTR_UNDERFLOW)
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struct softdma_channel {
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struct softdma_softc *sc;
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struct mtx mtx;
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xdma_channel_t *xchan;
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struct proc *p;
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int used;
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int index;
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int run;
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uint32_t idx_tail;
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uint32_t idx_head;
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struct softdma_desc *descs;
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uint32_t descs_num;
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uint32_t descs_used_count;
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};
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struct softdma_desc {
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uint64_t src_addr;
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uint64_t dst_addr;
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uint32_t len;
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uint32_t access_width;
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uint32_t count;
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uint16_t src_incr;
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uint16_t dst_incr;
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uint32_t direction;
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struct softdma_desc *next;
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uint32_t transfered;
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uint32_t status;
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uint32_t reserved;
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uint32_t control;
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};
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struct softdma_softc {
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device_t dev;
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struct resource *res[3];
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bus_space_tag_t bst;
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bus_space_handle_t bsh;
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bus_space_tag_t bst_c;
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bus_space_handle_t bsh_c;
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void *ih;
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struct softdma_channel channels[SOFTDMA_NCHANNELS];
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};
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static struct resource_spec softdma_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* fifo */
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{ SYS_RES_MEMORY, 1, RF_ACTIVE }, /* core */
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static int softdma_probe(device_t dev);
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static int softdma_attach(device_t dev);
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static int softdma_detach(device_t dev);
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static inline uint32_t
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softdma_next_desc(struct softdma_channel *chan, uint32_t curidx)
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{
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return ((curidx + 1) % chan->descs_num);
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}
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static void
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softdma_mem_write(struct softdma_softc *sc, uint32_t reg, uint32_t val)
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{
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bus_write_4(sc->res[0], reg, htole32(val));
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}
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static uint32_t
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softdma_mem_read(struct softdma_softc *sc, uint32_t reg)
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{
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uint32_t val;
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val = bus_read_4(sc->res[0], reg);
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return (le32toh(val));
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}
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static void
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softdma_memc_write(struct softdma_softc *sc, uint32_t reg, uint32_t val)
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{
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bus_write_4(sc->res[1], reg, htole32(val));
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}
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static uint32_t
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softdma_memc_read(struct softdma_softc *sc, uint32_t reg)
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{
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uint32_t val;
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val = bus_read_4(sc->res[1], reg);
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return (le32toh(val));
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}
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static uint32_t
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softdma_fill_level(struct softdma_softc *sc)
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{
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uint32_t val;
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val = softdma_memc_read(sc,
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A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_FILL_LEVEL);
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return (val);
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}
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static void
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softdma_intr(void *arg)
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{
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struct softdma_channel *chan;
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struct softdma_softc *sc;
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int reg;
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int err;
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sc = arg;
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chan = &sc->channels[0];
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reg = softdma_memc_read(sc, A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT);
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if (reg & (A_ONCHIP_FIFO_MEM_CORE_EVENT_OVERFLOW |
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A_ONCHIP_FIFO_MEM_CORE_EVENT_UNDERFLOW)) {
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/* Errors */
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err = (((reg & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) >> \
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A_ONCHIP_FIFO_MEM_CORE_ERROR_SHIFT) & 0xff);
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}
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if (reg != 0) {
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softdma_memc_write(sc,
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A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_EVENT, reg);
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chan->run = 1;
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wakeup(chan);
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}
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}
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static int
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softdma_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_is_compatible(dev, "altr,softdma"))
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return (ENXIO);
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device_set_desc(dev, "SoftDMA");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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softdma_attach(device_t dev)
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{
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struct softdma_softc *sc;
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phandle_t xref, node;
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int err;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, softdma_spec, sc->res)) {
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device_printf(dev,
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"could not allocate resources for device\n");
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return (ENXIO);
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}
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/* FIFO memory interface */
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sc->bst = rman_get_bustag(sc->res[0]);
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sc->bsh = rman_get_bushandle(sc->res[0]);
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/* FIFO control memory interface */
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sc->bst_c = rman_get_bustag(sc->res[1]);
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sc->bsh_c = rman_get_bushandle(sc->res[1]);
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/* Setup interrupt handler */
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err = bus_setup_intr(dev, sc->res[2], INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, softdma_intr, sc, &sc->ih);
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if (err) {
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device_printf(dev, "Unable to alloc interrupt resource.\n");
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return (ENXIO);
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}
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node = ofw_bus_get_node(dev);
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xref = OF_xref_from_node(node);
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OF_device_register_xref(xref, dev);
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return (0);
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}
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static int
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softdma_detach(device_t dev)
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{
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struct softdma_softc *sc;
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sc = device_get_softc(dev);
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return (0);
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}
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static int
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softdma_process_tx(struct softdma_channel *chan, struct softdma_desc *desc)
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{
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struct softdma_softc *sc;
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uint32_t src_offs, dst_offs;
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uint32_t reg;
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uint32_t fill_level;
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uint32_t leftm;
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uint32_t tmp;
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uint32_t val;
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uint32_t c;
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sc = chan->sc;
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fill_level = softdma_fill_level(sc);
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while (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH)
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fill_level = softdma_fill_level(sc);
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/* Set start of packet. */
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if (desc->control & CONTROL_GEN_SOP) {
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reg = 0;
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reg |= A_ONCHIP_FIFO_MEM_CORE_SOP;
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softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA, reg);
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}
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src_offs = dst_offs = 0;
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c = 0;
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while ((desc->len - c) >= 4) {
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val = *(uint32_t *)(desc->src_addr + src_offs);
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bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, val);
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if (desc->src_incr)
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src_offs += 4;
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if (desc->dst_incr)
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dst_offs += 4;
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fill_level += 1;
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while (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH) {
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fill_level = softdma_fill_level(sc);
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}
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c += 4;
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}
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val = 0;
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leftm = (desc->len - c);
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switch (leftm) {
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case 1:
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val = *(uint8_t *)(desc->src_addr + src_offs);
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val <<= 24;
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src_offs += 1;
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break;
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case 2:
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case 3:
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val = *(uint16_t *)(desc->src_addr + src_offs);
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val <<= 16;
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src_offs += 2;
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if (leftm == 3) {
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tmp = *(uint8_t *)(desc->src_addr + src_offs);
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val |= (tmp << 8);
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src_offs += 1;
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}
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break;
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case 0:
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default:
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break;
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}
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/* Set end of packet. */
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reg = 0;
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if (desc->control & CONTROL_GEN_EOP)
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reg |= A_ONCHIP_FIFO_MEM_CORE_EOP;
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reg |= ((4 - leftm) << A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT);
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softdma_mem_write(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA, reg);
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/* Ensure there is a FIFO entry available. */
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fill_level = softdma_fill_level(sc);
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while (fill_level == AVALON_FIFO_TX_BASIC_OPTS_DEPTH)
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fill_level = softdma_fill_level(sc);
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/* Final write */
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bus_write_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA, val);
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return (dst_offs);
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}
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static int
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softdma_process_rx(struct softdma_channel *chan, struct softdma_desc *desc)
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{
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uint32_t src_offs, dst_offs;
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struct softdma_softc *sc;
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uint32_t fill_level;
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uint32_t empty;
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uint32_t meta;
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uint32_t data;
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int sop_rcvd;
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int timeout;
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size_t len;
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int error;
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sc = chan->sc;
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empty = 0;
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src_offs = dst_offs = 0;
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error = 0;
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fill_level = softdma_fill_level(sc);
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if (fill_level == 0) {
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/* Nothing to receive. */
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return (0);
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}
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len = desc->len;
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sop_rcvd = 0;
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while (fill_level) {
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empty = 0;
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data = bus_read_4(sc->res[0], A_ONCHIP_FIFO_MEM_CORE_DATA);
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meta = softdma_mem_read(sc, A_ONCHIP_FIFO_MEM_CORE_METADATA);
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if (meta & A_ONCHIP_FIFO_MEM_CORE_ERROR_MASK) {
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error = 1;
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break;
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}
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if ((meta & A_ONCHIP_FIFO_MEM_CORE_CHANNEL_MASK) != 0) {
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error = 1;
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break;
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}
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if (meta & A_ONCHIP_FIFO_MEM_CORE_SOP) {
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sop_rcvd = 1;
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}
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if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP) {
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empty = (meta & A_ONCHIP_FIFO_MEM_CORE_EMPTY_MASK) >>
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A_ONCHIP_FIFO_MEM_CORE_EMPTY_SHIFT;
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}
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if (sop_rcvd == 0) {
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error = 1;
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break;
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}
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if (empty == 0) {
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*(uint32_t *)(desc->dst_addr + dst_offs) = data;
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dst_offs += 4;
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} else if (empty == 1) {
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*(uint16_t *)(desc->dst_addr + dst_offs) =
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((data >> 16) & 0xffff);
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dst_offs += 2;
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*(uint8_t *)(desc->dst_addr + dst_offs) =
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((data >> 8) & 0xff);
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dst_offs += 1;
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} else {
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panic("empty %d\n", empty);
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}
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if (meta & A_ONCHIP_FIFO_MEM_CORE_EOP)
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break;
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fill_level = softdma_fill_level(sc);
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timeout = 100;
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while (fill_level == 0 && timeout--)
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fill_level = softdma_fill_level(sc);
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if (timeout == 0) {
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/* No EOP received. Broken packet. */
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error = 1;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (error) {
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return (dst_offs);
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
softdma_process_descriptors(struct softdma_channel *chan,
|
||||
xdma_transfer_status_t *status)
|
||||
{
|
||||
struct xdma_channel *xchan;
|
||||
struct softdma_desc *desc;
|
||||
struct softdma_softc *sc;
|
||||
xdma_transfer_status_t st;
|
||||
int ret;
|
||||
|
||||
sc = chan->sc;
|
||||
|
||||
xchan = chan->xchan;
|
||||
|
||||
desc = &chan->descs[chan->idx_tail];
|
||||
|
||||
while (desc != NULL) {
|
||||
|
||||
if ((desc->control & CONTROL_OWN) == 0) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (desc->direction == XDMA_MEM_TO_DEV) {
|
||||
ret = softdma_process_tx(chan, desc);
|
||||
} else {
|
||||
ret = softdma_process_rx(chan, desc);
|
||||
if (ret == 0) {
|
||||
/* No new data available. */
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Descriptor processed. */
|
||||
desc->control = 0;
|
||||
|
||||
if (ret >= 0) {
|
||||
st.error = 0;
|
||||
st.transferred = ret;
|
||||
} else {
|
||||
st.error = ret;
|
||||
st.transferred = 0;
|
||||
}
|
||||
|
||||
xchan_seg_done(xchan, &st);
|
||||
atomic_subtract_int(&chan->descs_used_count, 1);
|
||||
|
||||
if (ret >= 0) {
|
||||
status->transferred += ret;
|
||||
} else {
|
||||
status->error = 1;
|
||||
break;
|
||||
}
|
||||
|
||||
chan->idx_tail = softdma_next_desc(chan, chan->idx_tail);
|
||||
|
||||
/* Process next descriptor, if any. */
|
||||
desc = desc->next;
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static void
|
||||
softdma_worker(void *arg)
|
||||
{
|
||||
xdma_transfer_status_t status;
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_softc *sc;
|
||||
|
||||
chan = arg;
|
||||
|
||||
sc = chan->sc;
|
||||
|
||||
while (1) {
|
||||
mtx_lock(&chan->mtx);
|
||||
|
||||
do {
|
||||
mtx_sleep(chan, &chan->mtx, 0, "softdma_wait", hz / 2);
|
||||
} while (chan->run == 0);
|
||||
|
||||
status.error = 0;
|
||||
status.transferred = 0;
|
||||
|
||||
softdma_process_descriptors(chan, &status);
|
||||
|
||||
/* Finish operation */
|
||||
chan->run = 0;
|
||||
xdma_callback(chan->xchan, &status);
|
||||
|
||||
mtx_unlock(&chan->mtx);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_proc_create(struct softdma_channel *chan)
|
||||
{
|
||||
struct softdma_softc *sc;
|
||||
|
||||
sc = chan->sc;
|
||||
|
||||
if (chan->p != NULL) {
|
||||
/* Already created */
|
||||
return (0);
|
||||
}
|
||||
|
||||
mtx_init(&chan->mtx, "SoftDMA", NULL, MTX_DEF);
|
||||
|
||||
if (kproc_create(softdma_worker, (void *)chan, &chan->p, 0, 0,
|
||||
"softdma_worker") != 0) {
|
||||
device_printf(sc->dev,
|
||||
"%s: Failed to create worker thread.\n", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_alloc(device_t dev, struct xdma_channel *xchan)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_softc *sc;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
for (i = 0; i < SOFTDMA_NCHANNELS; i++) {
|
||||
chan = &sc->channels[i];
|
||||
if (chan->used == 0) {
|
||||
chan->xchan = xchan;
|
||||
xchan->chan = (void *)chan;
|
||||
chan->index = i;
|
||||
chan->idx_head = 0;
|
||||
chan->idx_tail = 0;
|
||||
chan->descs_used_count = 0;
|
||||
chan->descs_num = 1024;
|
||||
chan->sc = sc;
|
||||
|
||||
if (softdma_proc_create(chan) != 0) {
|
||||
return (-1);
|
||||
}
|
||||
|
||||
chan->used = 1;
|
||||
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
||||
return (-1);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_free(device_t dev, struct xdma_channel *xchan)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
if (chan->descs != NULL) {
|
||||
free(chan->descs, M_DEVBUF);
|
||||
}
|
||||
|
||||
chan->used = 0;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_desc_alloc(struct xdma_channel *xchan)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
uint32_t nsegments;
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
nsegments = chan->descs_num;
|
||||
|
||||
chan->descs = malloc(nsegments * sizeof(struct softdma_desc),
|
||||
M_DEVBUF, (M_WAITOK | M_ZERO));
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_prep_sg(device_t dev, struct xdma_channel *xchan)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_desc *desc;
|
||||
struct softdma_softc *sc;
|
||||
int ret;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
ret = softdma_desc_alloc(xchan);
|
||||
if (ret != 0) {
|
||||
device_printf(sc->dev,
|
||||
"%s: Can't allocate descriptors.\n", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
for (i = 0; i < chan->descs_num; i++) {
|
||||
desc = &chan->descs[i];
|
||||
|
||||
if (i == (chan->descs_num - 1)) {
|
||||
desc->next = &chan->descs[0];
|
||||
} else {
|
||||
desc->next = &chan->descs[i+1];
|
||||
}
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_capacity(device_t dev, xdma_channel_t *xchan,
|
||||
uint32_t *capacity)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
uint32_t c;
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
/* At least one descriptor must be left empty. */
|
||||
c = (chan->descs_num - chan->descs_used_count - 1);
|
||||
|
||||
*capacity = c;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_submit_sg(device_t dev, struct xdma_channel *xchan,
|
||||
struct xdma_sglist *sg, uint32_t sg_n)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_desc *desc;
|
||||
struct softdma_softc *sc;
|
||||
uint32_t enqueued;
|
||||
uint32_t saved_dir;
|
||||
uint32_t tmp;
|
||||
uint32_t len;
|
||||
int i;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
enqueued = 0;
|
||||
|
||||
for (i = 0; i < sg_n; i++) {
|
||||
len = (uint32_t)sg[i].len;
|
||||
|
||||
desc = &chan->descs[chan->idx_head];
|
||||
desc->src_addr = sg[i].src_addr;
|
||||
desc->dst_addr = sg[i].dst_addr;
|
||||
if (sg[i].direction == XDMA_MEM_TO_DEV) {
|
||||
desc->src_incr = 1;
|
||||
desc->dst_incr = 0;
|
||||
} else {
|
||||
desc->src_incr = 0;
|
||||
desc->dst_incr = 1;
|
||||
}
|
||||
desc->direction = sg[i].direction;
|
||||
saved_dir = sg[i].direction;
|
||||
desc->len = len;
|
||||
desc->transfered = 0;
|
||||
desc->status = 0;
|
||||
desc->reserved = 0;
|
||||
desc->control = 0;
|
||||
|
||||
if (sg[i].first == 1)
|
||||
desc->control |= CONTROL_GEN_SOP;
|
||||
if (sg[i].last == 1)
|
||||
desc->control |= CONTROL_GEN_EOP;
|
||||
|
||||
tmp = chan->idx_head;
|
||||
chan->idx_head = softdma_next_desc(chan, chan->idx_head);
|
||||
atomic_add_int(&chan->descs_used_count, 1);
|
||||
desc->control |= CONTROL_OWN;
|
||||
enqueued += 1;
|
||||
}
|
||||
|
||||
if (enqueued == 0)
|
||||
return (0);
|
||||
|
||||
if (saved_dir == XDMA_MEM_TO_DEV) {
|
||||
chan->run = 1;
|
||||
wakeup(chan);
|
||||
} else
|
||||
softdma_memc_write(sc,
|
||||
A_ONCHIP_FIFO_MEM_CORE_STATUS_REG_INT_ENABLE,
|
||||
SOFTDMA_RX_EVENTS);
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_request(device_t dev, struct xdma_channel *xchan,
|
||||
struct xdma_request *req)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_desc *desc;
|
||||
struct softdma_softc *sc;
|
||||
int ret;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
ret = softdma_desc_alloc(xchan);
|
||||
if (ret != 0) {
|
||||
device_printf(sc->dev,
|
||||
"%s: Can't allocate descriptors.\n", __func__);
|
||||
return (-1);
|
||||
}
|
||||
|
||||
desc = &chan->descs[0];
|
||||
|
||||
desc->src_addr = req->src_addr;
|
||||
desc->dst_addr = req->dst_addr;
|
||||
desc->len = req->block_len;
|
||||
desc->src_incr = 1;
|
||||
desc->dst_incr = 1;
|
||||
desc->next = NULL;
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
static int
|
||||
softdma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
|
||||
{
|
||||
struct softdma_channel *chan;
|
||||
struct softdma_softc *sc;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
|
||||
chan = (struct softdma_channel *)xchan->chan;
|
||||
|
||||
switch (cmd) {
|
||||
case XDMA_CMD_BEGIN:
|
||||
case XDMA_CMD_TERMINATE:
|
||||
case XDMA_CMD_PAUSE:
|
||||
/* TODO: implement me */
|
||||
return (-1);
|
||||
}
|
||||
|
||||
return (0);
|
||||
}
|
||||
|
||||
#ifdef FDT
|
||||
static int
|
||||
softdma_ofw_md_data(device_t dev, pcell_t *cells,
|
||||
int ncells, void **ptr)
|
||||
{
|
||||
|
||||
return (0);
|
||||
}
|
||||
#endif
|
||||
|
||||
static device_method_t softdma_methods[] = {
|
||||
/* Device interface */
|
||||
DEVMETHOD(device_probe, softdma_probe),
|
||||
DEVMETHOD(device_attach, softdma_attach),
|
||||
DEVMETHOD(device_detach, softdma_detach),
|
||||
|
||||
/* xDMA Interface */
|
||||
DEVMETHOD(xdma_channel_alloc, softdma_channel_alloc),
|
||||
DEVMETHOD(xdma_channel_free, softdma_channel_free),
|
||||
DEVMETHOD(xdma_channel_request, softdma_channel_request),
|
||||
DEVMETHOD(xdma_channel_control, softdma_channel_control),
|
||||
|
||||
/* xDMA SG Interface */
|
||||
DEVMETHOD(xdma_channel_prep_sg, softdma_channel_prep_sg),
|
||||
DEVMETHOD(xdma_channel_submit_sg, softdma_channel_submit_sg),
|
||||
DEVMETHOD(xdma_channel_capacity, softdma_channel_capacity),
|
||||
|
||||
#ifdef FDT
|
||||
DEVMETHOD(xdma_ofw_md_data, softdma_ofw_md_data),
|
||||
#endif
|
||||
|
||||
DEVMETHOD_END
|
||||
};
|
||||
|
||||
static driver_t softdma_driver = {
|
||||
"softdma",
|
||||
softdma_methods,
|
||||
sizeof(struct softdma_softc),
|
||||
};
|
||||
|
||||
static devclass_t softdma_devclass;
|
||||
|
||||
EARLY_DRIVER_MODULE(softdma, simplebus, softdma_driver, softdma_devclass, 0, 0,
|
||||
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|
||||
Loading…
Reference in New Issue
Block a user