Add support for the 8139C+ chipset. Unlike the other chips in the 8139

series, the 8139C+ has a descriptor-based DMA mechanism, and its
performance is actually pretty respectable. Note: the 8139D chip does
not support C+ mode. Only the 8139C+ and 8169 gigE chips support C+ mode.

Supported features:

- RX and TX checksum offload
- hardware VLAN tag insertion/extraction
- TX interrupt moderation using the 8139's on-board timer

Everything should be properly busdma'ed and endian-independent, so
things should work ok on non-x86 platforms. Unfortunately, my call
for testers on this code was met with deafening silence, and I don't
have access to any non-x86 FreeBSD boxes at the moment, so this is
speculation.

The device detection code has been cleaned up a little as well
(thanks to Michal Mertl) for the patches.

There are also updates to the rl(4) man page (which I accidentally
checked in before when I updated the dc(4) man page. Oops.)

Todo: finish support for the 8169 gigabit ethernet chip. This
mainly requires writing an rlgphy driver to handle the 8169's built-in
PHY. This will have to wait until I actually get my hands on an 8169
card for testing though. (I still can't find a source for one in the
U.S. Suggestions/pointers welcome.)

sys/pci/if_rlreg.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 1997, 1998
+ * Copyright (c) 1997, 1998-2003
  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -99,6 +99,34 @@
 #define RL_RX_ER	0x0072		/* RX_ER counter */
 #define RL_CSCFG	0x0074		/* CS configuration register */
 
+/*
+ * When operating in special C+ mode, some of the registers in an
+ * 8139C+ chip have different definitions. These are also used for
+ * the 8169 gigE chip.
+ */
+#define RL_DUMPSTATS_LO		0x0010	/* counter dump command register */
+#define RL_DUMPSTATS_HI		0x0014	/* counter dump command register */
+#define RL_TXLIST_ADDR_LO	0x0020	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HI	0x0024	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HPRIO_LO	0x0028	/* 64 bits, 256 byte alignment */
+#define RL_TXLIST_ADDR_HPRIO_HI	0x002C	/* 64 bits, 256 byte alignment */
+#define RL_TIMERINT		0x0054	/* interrupt on timer expire */
+#define RL_TXSTART		0x00D9	/* 8 bits */
+#define RL_CPLUS_CMD		0x00E0	/* 16 bits */
+#define RL_RXLIST_ADDR_LO	0x00E4	/* 64 bits, 256 byte alignment */
+#define RL_RXLIST_ADDR_HI	0x00E8	/* 64 bits, 256 byte alignment */
+#define RL_EARLY_TX_THRESH	0x00EC	/* 8 bits */
+
+/*
+ * Registers specific to the 8169 gigE chip
+ */
+#define RL_PHYAR		0x0060
+#define RL_TBICSR		0x0064
+#define RL_TBI_ANAR		0x0068
+#define RL_TBI_LPAR		0x006A
+#define RL_GMEDIASTAT		0x006C	/* 8 bits */
+#define RL_MAXRXPKTLEN		0x00DA	/* 16 bits, chip multiplies by 8 */
+#define RL_GTXSTART		0x0038	/* 16 bits */
 
 /*
  * TX config register bits
@@ -108,6 +136,16 @@
 #define RL_TXCFG_CRCAPPEND	0x00010000	/* CRC append (0 = yes) */
 #define RL_TXCFG_LOOPBKTST	0x00060000	/* loopback test */
 #define RL_TXCFG_IFG		0x03000000	/* interframe gap */
+#define RL_TXCFG_HWREV		0x7CC00000
+
+#define RL_HWREV_8139		0x60000000
+#define RL_HWREV_8139A		0x70000000
+#define RL_HWREV_8139AG		0x70800000
+#define RL_HWREV_8139B		0x78000000
+#define RL_HWREV_8130		0x7C000000
+#define RL_HWREV_8139C		0x74000000
+#define RL_HWREV_8139D		0x74400000
+#define RL_HWREV_8139CPLUS	0x74800000
 
 #define RL_TXDMA_16BYTES	0x00000000
 #define RL_TXDMA_32BYTES	0x00000100
@@ -142,7 +180,11 @@
 #define RL_ISR_RX_OVERRUN	0x0010
 #define RL_ISR_PKT_UNDERRUN	0x0020
 #define RL_ISR_FIFO_OFLOW	0x0040	/* 8139 only */
+#define RL_ISR_TX_DESC_UNAVAIL	0x0080	/* C+ only */
+#define RL_ISR_SWI		0x0100	/* C+ only */
+#define RL_ISR_CABLE_LEN_CHGD	0x2000
 #define RL_ISR_PCS_TIMEOUT	0x4000	/* 8129 only */
+#define RL_ISR_TIMEOUT_EXPIRED	0x4000
 #define RL_ISR_SYSTEM_ERR	0x8000
 
 #define RL_INTRS	\
@@ -150,6 +192,11 @@
 	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
 	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR)
 
+#define RL_INTRS_CPLUS	\
+	(RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_TX_ERR|		\
+	RL_ISR_RX_OVERRUN|RL_ISR_PKT_UNDERRUN|RL_ISR_FIFO_OFLOW|	\
+	RL_ISR_PCS_TIMEOUT|RL_ISR_SYSTEM_ERR|RL_ISR_TIMEOUT_EXPIRED)
+
 /*
  * Media status register. (8139 only)
  */
@@ -281,6 +328,53 @@
 #define RL_CFG1_FULLDUPLEX	0x40	/* 8129 only */
 #define RL_CFG1_LED1		0x80
 
+/*
+ * 8139C+ register definitions
+ */
+
+/* RL_DUMPSTATS_LO register */
+
+#define RL_DUMPSTATS_START	0x00000008
+
+/* Transmit start register */
+
+#define RL_TXSTART_SWI		0x01	/* generate TX interrupt */
+#define RL_TXSTART_START	0x40	/* start normal queue transmit */
+#define RL_TXSTART_HPRIO_START	0x80	/* start hi prio queue transmit */
+
+/* C+ mode command register */
+
+#define RL_CPLUSCMD_TXENB	0x0001	/* enable C+ transmit mode */
+#define RL_CPLUSCMD_RXENB	0x0002	/* enable C+ receive mode */
+#define RL_CPLUSCMD_PCI_MRW	0x0008	/* enable PCI multi-read/write */
+#define RL_CPLUSCMD_PCI_DAC	0x0010	/* PCI dual-address cycle only */
+#define RL_CPLUSCMD_RXCSUM_ENB	0x0020	/* enable RX checksum offload */
+#define RL_CPLUSCMD_VLANSTRIP	0x0040	/* enable VLAN tag stripping */
+
+/* C+ early transmit threshold */
+
+#define RL_EARLYTXTHRESH_CNT	0x003F	/* byte count times 8 */ 
+
+/*
+ * Gigabit PHY access register (8169 only)
+ */
+
+#define RL_PHYAR_PHYDATA	0x0000FFFF
+#define RL_PHYAR_PHYREG		0x001F0000
+#define RL_PHYAR_BUSY		0x80000000
+
+/*
+ * Gigabit media status (8169 only)
+ */
+#define RL_GMEDIASTAT_FDX	0x01	/* full duplex */
+#define RL_GMEDIASTAT_LINK	0x02	/* link up */
+#define RL_GMEDIASTAT_10MBPS	0x04	/* 10mps link */
+#define RL_GMEDIASTAT_100MBPS	0x08	/* 100mbps link */
+#define RL_GMEDIASTAT_1000MPS	0x10	/* gigE link */
+#define RL_GMEDIASTAT_RXFLOW	0x20	/* RX flow control on */
+#define RL_GMEDIASTAT_TXFLOW	0x40	/* TX flow control on */
+#define RL_GMEDIASTAT_TBI	0x80	/* TBI enabled */
+
 /*
  * The RealTek doesn't use a fragment-based descriptor mechanism.
  * Instead, there are only four register sets, each or which represents
@@ -336,9 +430,16 @@ struct rl_chain_data {
 struct rl_type {
 	u_int16_t		rl_vid;
 	u_int16_t		rl_did;
+	int			rl_basetype;
 	char			*rl_name;
 };
 
+struct rl_hwrev {
+	u_int32_t		rl_rev;
+	int			rl_type;
+	char			*rl_desc;
+};
+
 struct rl_mii_frame {
 	u_int8_t		mii_stdelim;
 	u_int8_t		mii_opcode;
@@ -358,6 +459,167 @@ struct rl_mii_frame {
 
 #define RL_8129			1
 #define RL_8139			2
+#define RL_8139CPLUS		3
+#define RL_8169			4
+
+#define RL_ISCPLUS(x)		((x)->rl_type == RL_8139CPLUS ||	\
+				 (x)->rl_type == RL_8169)
+
+/*
+ * The 8139C+ and 8160 gigE chips support descriptor-based TX
+ * and RX. In fact, they even support TCP large send. Descriptors
+ * must be allocated in contiguous blocks that are aligned on a
+ * 256-byte boundary. The rings can hold a maximum of 64 descriptors.
+ */
+
+/*
+ * RX/TX descriptor definition. When large send mode is enabled, the
+ * lower 11 bits of the TX rl_cmd word are used to hold the MSS, and
+ * the checksum offload bits are disabled. The structure layout is
+ * the same for RX and TX descriptors
+ */
+
+struct rl_desc {
+	u_int32_t		rl_cmdstat;
+	u_int32_t		rl_vlanctl;
+	u_int32_t		rl_bufaddr_lo;
+	u_int32_t		rl_bufaddr_hi;
+};
+
+#define RL_TDESC_CMD_FRAGLEN	0x0000FFFF
+#define RL_TDESC_CMD_TCPCSUM	0x00010000	/* TCP checksum enable */
+#define RL_TDESC_CMD_UDPCSUM	0x00020000	/* UDP checksum enable */
+#define RL_TDESC_CMD_IPCSUM	0x00040000	/* IP header checksum enable */
+#define RL_TDESC_CMD_MSSVAL	0x07FF0000	/* Large send MSS value */
+#define RL_TDESC_CMD_LGSEND	0x08000000	/* TCP large send enb */
+#define RL_TDESC_CMD_EOF	0x10000000	/* end of frame marker */
+#define RL_TDESC_CMD_SOF	0x20000000	/* start of frame marker */
+#define RL_TDESC_CMD_EOR	0x40000000	/* end of ring marker */
+#define RL_TDESC_CMD_OWN	0x80000000	/* chip owns descriptor */
+
+#define RL_TDESC_VLANCTL_TAG	0x00020000	/* Insert VLAN tag */
+#define RL_TDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+
+/*
+ * Error bits are valid only on the last descriptor of a frame
+ * (i.e. RL_TDESC_CMD_EOF == 1)
+ */
+
+#define RL_TDESC_STAT_COLCNT	0x000F0000	/* collision count */
+#define RL_TDESC_STAT_EXCESSCOL	0x00100000	/* excessive collisions */
+#define RL_TDESC_STAT_LINKFAIL	0x00200000	/* link faulure */
+#define RL_TDESC_STAT_OWINCOL	0x00400000	/* out-of-window collision */
+#define RL_TDESC_STAT_TXERRSUM	0x00800000	/* transmit error summary */
+#define RL_TDESC_STAT_UNDERRUN	0x02000000	/* TX underrun occured */
+#define RL_TDESC_STAT_OWN	0x80000000
+
+/*
+ * RX descriptor cmd/vlan definitions
+ */
+
+#define RL_RDESC_CMD_EOR	0x40000000
+#define RL_RDESC_CMD_OWN	0x80000000
+#define RL_RDESC_CMD_BUFLEN	0x00001FFF
+
+#define RL_RDESC_STAT_OWN	0x80000000
+#define RL_RDESC_STAT_EOR	0x40000000
+#define RL_RDESC_STAT_SOF	0x20000000
+#define RL_RDESC_STAT_EOF	0x10000000
+#define RL_RDESC_STAT_FRALIGN	0x08000000	/* frame alignment error */
+#define RL_RDESC_STAT_MCAST	0x04000000	/* multicast pkt received */
+#define RL_RDESC_STAT_UCAST	0x02000000	/* unicast pkt received */
+#define RL_RDESC_STAT_BCAST	0x01000000	/* broadcast pkt received */
+#define RL_RDESC_STAT_BUFOFLOW	0x00800000	/* out of buffer space */
+#define RL_RDESC_STAT_FIFOOFLOW	0x00400000	/* FIFO overrun */
+#define RL_RDESC_STAT_GIANT	0x00200000	/* pkt > 4096 bytes */
+#define RL_RDESC_STAT_RXERRSUM	0x00100000	/* RX error summary */
+#define RL_RDESC_STAT_RUNT	0x00080000	/* runt packet received */
+#define RL_RDESC_STAT_CRCERR	0x00040000	/* CRC error */
+#define RL_RDESC_STAT_PROTOID	0x00030000	/* Protocol type */
+#define RL_RDESC_STAT_IPSUMBAD	0x00008000	/* IP header checksum bad */
+#define RL_RDESC_STAT_UDPSUMBAD	0x00004000	/* UDP checksum bad */
+#define RL_RDESC_STAT_TCPSUMBAD	0x00002000	/* TCP checksum bad */
+#define RL_RDESC_STAT_FRAGLEN	0x00001FFF	/* RX'ed frame/frag len */
+
+#define RL_RDESC_VLANCTL_TAG	0x00010000	/* VLAN tag available
+						   (rl_vlandata valid)*/
+#define RL_RDESC_VLANCTL_DATA	0x0000FFFF	/* TAG data */
+
+#define RL_PROTOID_NONIP	0x00000000
+#define RL_PROTOID_TCPIP	0x00010000
+#define RL_PROTOID_UDPIP	0x00020000
+#define RL_PROTOID_IP		0x00030000
+#define RL_TCPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_TCPIP)
+#define RL_UDPPKT(x)		(((x) & RL_RDESC_STAT_PROTOID) == \
+				 RL_PROTOID_UDPIP)
+
+/*
+ * Statistics counter structure (8139C+ and 8169 only)
+ */
+struct rl_stats {
+	u_int32_t		rl_tx_pkts_lo;
+	u_int32_t		rl_tx_pkts_hi;
+	u_int32_t		rl_tx_errs_lo;
+	u_int32_t		rl_tx_errs_hi;
+	u_int32_t		rl_tx_errs;
+	u_int16_t		rl_missed_pkts;
+	u_int16_t		rl_rx_framealign_errs;
+	u_int32_t		rl_tx_onecoll;
+	u_int32_t		rl_tx_multicolls;
+	u_int32_t		rl_rx_ucasts_hi;
+	u_int32_t		rl_rx_ucasts_lo;
+	u_int32_t		rl_rx_bcasts_lo;
+	u_int32_t		rl_rx_bcasts_hi;
+	u_int32_t		rl_rx_mcasts;
+	u_int16_t		rl_tx_aborts;
+	u_int16_t		rl_rx_underruns;
+};
+
+#define RL_RX_DESC_CNT		64
+#define RL_TX_DESC_CNT		64
+#define RL_RX_LIST_SZ		(RL_RX_DESC_CNT * sizeof(struct rl_desc))
+#define RL_TX_LIST_SZ		(RL_TX_DESC_CNT * sizeof(struct rl_desc))
+#define RL_RING_ALIGN		256
+#define RL_IFQ_MAXLEN		512
+#define RL_DESC_INC(x)		(x = (x + 1) % RL_TX_DESC_CNT)
+#define RL_OWN(x)		(le32toh((x)->rl_cmdstat) & RL_RDESC_STAT_OWN)
+#define RL_RXBYTES(x)		(le32toh((x)->rl_cmdstat) &	\
+				 RL_RDESC_STAT_FRAGLEN)
+#define RL_PKTSZ(x)		((x) >> 3)
+
+struct rl_softc;
+
+struct rl_dmaload_arg {
+	struct rl_softc		*sc;
+	int			rl_idx;
+	int			rl_maxsegs;
+	struct rl_desc		*rl_ring;
+};
+
+struct rl_list_data {
+	struct mbuf		*rl_tx_mbuf[RL_TX_DESC_CNT];
+	struct mbuf		*rl_rx_mbuf[RL_TX_DESC_CNT];
+	int			rl_tx_prodidx;
+	int			rl_rx_prodidx;
+	int			rl_tx_considx;
+	int			rl_tx_free;
+	bus_dmamap_t		rl_tx_dmamap[RL_TX_DESC_CNT];
+	bus_dmamap_t		rl_rx_dmamap[RL_RX_DESC_CNT];
+	bus_dma_tag_t		rl_mtag;	/* mbuf mapping tag */
+	bus_dma_tag_t		rl_stag;	/* stats mapping tag */
+	bus_dmamap_t		rl_smap;	/* stats map */
+	struct rl_stats		*rl_stats;
+	u_int32_t		rl_stats_addr;
+	bus_dma_tag_t		rl_rx_list_tag;
+	bus_dmamap_t		rl_rx_list_map;
+	struct rl_desc		*rl_rx_list;
+	u_int32_t		rl_rx_list_addr;
+	bus_dma_tag_t		rl_tx_list_tag;
+	bus_dmamap_t		rl_tx_list_map;
+	struct rl_desc		*rl_tx_list;
+	u_int32_t		rl_tx_list_addr;
+};
 
 struct rl_softc {
 	struct arpcom		arpcom;		/* interface info */
@@ -375,6 +637,7 @@ struct rl_softc {
 	u_int8_t		rl_stats_no_timeout;
 	int			rl_txthresh;
 	struct rl_chain_data	rl_cdata;
+	struct rl_list_data	rl_ldata;
 	struct callout_handle	rl_stat_ch;
 	struct mtx		rl_mtx;
 	int			suspended;	/* 0 = normal  1 = suspended */
@@ -424,6 +687,9 @@ struct rl_softc {
 #define	RT_DEVICEID_8129			0x8129
 #define	RT_DEVICEID_8138			0x8138
 #define	RT_DEVICEID_8139			0x8139
+#define RT_DEVICEID_8169			0x8169
+
+#define RT_REVID_8139CPLUS			0x20
 
 /*
  * Accton PCI vendor ID
@@ -503,12 +769,37 @@ struct rl_softc {
 /*
  * Planex Communications, Inc. vendor ID
  */
-#define PLANEX_VENDORID                      0x14ea
+#define PLANEX_VENDORID				0x14ea
 
 /*
  * Planex FNW-3800-TX device ID
  */
-#define PLANEX_DEVICEID_FNW3800TX                 0xab07
+#define PLANEX_DEVICEID_FNW3800TX		0xab07
+
+/*
+ * LevelOne vendor ID
+ */
+#define LEVEL1_VENDORID				0x018A
+
+/*
+ * LevelOne FPC-0106TX devide ID
+ */
+#define LEVEL1_DEVICEID_FPC0106TX		0x0106
+
+/*
+ * Compaq vendor ID
+ */
+#define CP_VENDORID				0x021B
+
+/*
+ * Edimax vendor ID
+ */
+#define EDIMAX_VENDORID				0x13D1
+
+/*
+ * Edimax EP-4103DL cardbus device ID
+ */
+#define EDIMAX_DEVICEID_EP4103DL		0xAB06
 
 /*
  * PCI low memory base and low I/O base register, and